DS80C310MCG ,High-Speed MicroFEATURES PACKAGE OUTLINE 80C32-compatible- 8051 pin- and instruction set-compatible- Full duplex s ..
DS80C310-MCG ,High-Speed Microfeatures a redesigned processorcore without wasted clock and memory cycles. As a result, it execute ..
DS80C310QCG ,High-Speed Microapplications will see aspeed improvement of 2.5 times using the same code and the same crystal. The ..
DS80C310QCG ,High-Speed Microapplications will see aspeed improvement of 2.5 times using the same code and the same crystal. The ..
DS80C310QCG ,High-Speed MicroDS80C310High-Speed Microwww.dalsemi.com
DS80C310-QCG+ ,High-Speed MicrocontrollerFEATURES PACKAGE OUTLINE § 80C32-compatible - 8051 pin- and instruction set-compatible - Full du ..
ECH8401 ,Medium Output MOSFETsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8402 ,Medium Output MOSFETsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8402 ,Medium Output MOSFETsOrdering number : ENN8148 ECH8402N-Channel Silicon MOSFETGeneral-Purpose Switching DeviceECH8402App ..
ECH8410 ,N-Channel Power MOSFET, 30V, 12A, 10mOhm, Single ECH8Maximum RatingsParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage V 30 VDSSGate-to-Sou ..
ECH8601 ,Nch+NchAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8604 ,N CHANNEL MOS SILICON TRANSISTOR
DS80C310-ECG-DS80C310MCG-DS80C310-MCG-DS80C310QCG
High-Speed Micro
FEATURES80C32-compatible8051 pin- and instruction set-compatibleFull duplex serial port- Three 16-bit timer/counters256 bytes scratchpad RAMMultiplexed address/data busAddresses 64 kB ROM and 64 kB RAMHigh-Speed Architecture- 4 clocks/machine cycle (8051 = 12)Runs DC to 33 MHz clock ratesSingle-cycle instruction in 121 nsDual data pointerOptional variable length MOVX to accessfast/slow RAM /peripherals10 total interrupt sources with 6 externalInternal power-on reset circuitUpwardly compatible with the DS80C320Available in 40-pin PDIP, 44-pin PLCC, and44-pin TQFP
PACKAGE OUTLINE
DESCRIPTIONThe DS80C310 is a fast 80C31/80C32-compatible microcontroller. It features a redesigned processorcore without wasted clock and memory cycles. As a result, it executes every 8051 instruction between 1.5
and 3 times faster than the original architecture for the same crystal speed. Typical applications will see a
speed improvement of 2.5 times using the same code and the same crystal. The DS80C310 offers a
maximum crystal speed of 33 MHz, resulting in apparent execution speeds of 82.5 MHz (approximately
DS80C310
High-Speed Micro
DS87C520/DS83C520
The DS80C310 is pin-compatible with the standard 80C32 and includes standard resources such as three
timer/counters, 256 bytes of RAM, and a serial port. It also provides dual data pointers (DPTRs) to speed
block data memory moves. It also can adjust the speed of MOVX data memory access between two and
nine machine cycles for flexibility in selecting external memory and peripherals. The DS80C310 offersupward compatibility with the DS80C320.
ORDERING INFORMATION:
DS80C310 BLOCK DIAGRAM Figure 1
DS87C520/DS83C520
PIN DESCRIPTION Table 1
DS87C520/DS83C520
DS87C520/DS83C520
COMPATIBILITYThe DS80C310 is a fully static CMOS 8051-compatible microcontroller designed for high performance.
In most cases the DS80C310 can drop into an existing socket for the 80C31 or 80C32 to improve the
operation significantly. In general, software written for existing 8051-based systems works without
modification on the DS80C310. The exception is critical timing since the High-Speed Micro performs its
instructions much faster than the original for any given crystal selection. The DS80C310 runs thestandard 8051 family instruction set and is pin compatible with DIP, PLCC or TQFP packages. The
DS80C310 is a streamlined version of the DS80C320. It maintains upward compatibility but has fewer
peripherals.
The DS80C310 provides three 16-bit timer/counters, a full-duplex serial port, and 256 bytes of directRAM. I/O ports have the same operation as a standard 8051 product. Timers will default to a 12-clock per
cycle operation to keep their timing compatible with original 8051 family systems. However, timers are
individually programmable to run at the new 4 clocks per cycle if desired.
The DS80C310 provides several new hardware functions that are controlled by Special Functionregisters. A summary of the Special Function Registers is provided in Table 2.
PERFORMANCE OVERVIEWThe DS80C310 features a high-speed 8051 compatible core. Higher speed comes not just from increasingthe clock frequency, but from a newer, more efficient design.
This updated core does not have the dummy memory cycles that are present in a standard 8051. A
conventional 8051 generates machine cycles using the clock frequency divided by 12. In the DS80C310,
the same machine cycle takes four clocks. Thus the fastest instruction, 1 machine cycle, executes threetimes faster for the same crystal frequency. Note that these are identical instructions. The majority of
instructions on the DS80C310 will see the full 3 to 1 speed improvement. Some instructions will get
between 1.5 and 2.4 to 1 improvement. All instructions are faster than the original 8051.
The numerical average of all opcodes gives approximately a 2.5 to 1 speed improvement. Improvement ofindividual programs will depend on the actual instructions used. Speed-sensitive applications would make
the most use of instructions that are three times faster. However, the sheer number of 3 to 1 improved
opcodes makes dramatic speed improvements likely for any code. These architecture improvements and
0.8 μm CMOS produce a peak instruction cycle in 121 ns (8.25 MIPs). The Dual Data Pointer featurealso allows the user to eliminate wasted instructions when moving blocks of memory.
INSTRUCTION SET SUMMARYAll instructions in the DS80C310 perform the same functions as their 8051 counterparts. Their effect onbits, flags, and other status functions is identical. However, the timing of each instruction is different.
This applies both in absolute and relative number of clocks.
For absolute timing of real time events, the timing of software loops can be calculated using a table in the
High-Speed Microcontroller User’s Guide. However, counter/timers default to run at the older 12 clocksper increment. In this way, timer-based events occur at the standard intervals with software executing at
higher speed. Timers optionally can run at 4 clocks per increment to take advantage of faster processor
operation.
The relative time of two instructions might be different in the new architecture than it was previously. For
DS87C520/DS83C520
time. In the DS80C310, the MOVX instruction takes as little as two machine cycles or eight oscillator
cycles but the “MOV direct, direct” uses three machine cycles or 12 oscillator cycles. While both are
faster than their original counterparts, they now have different execution times. This is because the
DS80C310 usually uses one instruction cycle for each instruction byte. The user concerned with preciseprogram timing should examine the timing of each instruction for familiarity with the changes. Note that
a machine cycle now requires just four clocks, and provides one ALE pulse per cycle. Many instructions
require only one cycle, but some require five. In the original architecture, all were one or two cycles
except for MUL and DIV. Refer to the High-Speed Microcontroller User’s Guide for details and
individual instruction timing.
DS87C520/DS83C520
SPECIAL FUNCTION REGISTERSSpecial Function Registers (SFRs) control most special features of the DS80C310. The High-Speed
Microcontroller User’s Guide describes all SFRs. Functions that are not part of the standard 80C32 are in
bold.
SPECIAL FUNCTION REGISTERS Table 2
DS87C520/DS83C520
MEMORY ACCESSThe DS80C310 contains no on-chip ROM, and 256 bytes of scratchpad RAM. Off-chip memory is
accessed using the multiplexed address/data bus on P0 and the MSB address on P2. Timing diagrams are
provided in the Electrical Specifications. Program memory (ROM) is accessed at a fixed rate determined
by the crystal frequency and the actual instructions. As mentioned above, an instruction cycle requires
four clocks. Data memory (RAM) is accessed according to a variable speed MOVX instruction asdescribed below.
STRETCH MEMORY CYCLEThe DS80C310 allows the application software to adjust the speed of data memory access. The micro is
capable of performing the MOVX in as few as two instruction cycles. However, this value can be
stretched as needed so that both fast memory and slow memory or peripherals can be accessed with no
glue logic. Even in highspeed systems, it may not be necessary or desirable to perform data memoryaccess at full speed. In addition, there are a variety of memory mapped peripherals such as LCD displays
or UARTs that are not fast.
The Stretch MOVX is controlled by the Clock Control Register at SFR location 8Eh as described below.This allows the user to select a stretch value between 0 and 7. A Stretch of 0 will result in a two-machine
cycle MOVX. A Stretch of 7 will result in a MOVX of nine machine cycles. Software can dynamically
change this value depending on the particular memory or peripheral.
On reset, the Stretch value will default to a one resulting in a three-cycle MOVX. Therefore, RAM accesswill not be performed at full speed. This is a convenience to existing designs that may not have fast RAM
in place. When maximum speed is desired, the software should select a Stretch value of 0. When using
very slow RAM or peripherals, a larger stretch value can be selected. Note that this affects data memory
only and the only way to slow program memory (ROM) access is to use a slower crystal.
Using a Stretch value between 1 and 7 causes the microcontroller to stretch the read/write strobe and all
related timing. This results in a wider read/write strobe allowing more time for memory/peripherals to
respond. The timing of the variable speed MOVX is shown in the Electrical Specifications. Note that full
speed access is not the reset default case. Table 3 shows the resulting strobe widths for each Stretch value.
The memory stretch is implemented using the Clock Control Special Function Register at SFR location8Eh. The stretch value is selected using bits CKCON.2-0. In the table, these bits are referred to as M2
through M0. The first stretch (default) allows the use of common 120 ns or 150 ns RAMs without
dramatically lengthening the memory access.
DATA MEMORY CYCLE STRETCH VALUES Table 3
CKCON.2-0 RD OR WR STROBE STROBE WIDTH TIME
M2 M1 M0 MEMORY CYCLES WIDTH IN CLOCKS @ 25 MHz @ 33 MHz002280 ns60ns013(default)4160 ns121ns1048320 ns242ns011512480 ns364ns00616640 ns485ns01720800 ns606ns10824960 ns727ns119281120 ns848ns
DS87C520/DS83C520
DUAL DATA POINTERData memory block moves can be accelerated using the DS80C310 Dual Data Pointer (DPTR). The
standard 8032 DPTR is a 16-bit value that is used to address off-chip data RAM or peripherals. In the
DS80C310, the standard data pointer is called DPTR and is located at SFR addresses 82h and 83h. These
are the standard locations. No modification of standard code is needed to use DPTR. The new DPTR is
located at SFR 84h and 85h and is called DPTR1. The DPTR Select bit (DPS) chooses the active pointerand is located at the lsb of the SFR location 86h. No other bits in register 86h have any effect and are set
to 0. The user switches between data pointers by toggling the lsb of register 86h. The increment (INC)
instruction is the fastest way to accomplish this. All DPTR-related instructions use the currently selected
DPTR for any activity. Therefore only one instruction is required to switch from a source to a destination
address. Using the Dual Data Pointer saves code from needing to save source and destination addresseswhen doing a block move. Once loaded, the software simply switches between DPTR0 and 1. The
relevant register locations are as follows.
DPL 82h Low byte original DPTR
DPH 83h High byte original DPTRDPL1 84h Low byte new DPTR
DPH1 85h High byte new DPTR
DPS 86h DPTR Select (lsb)
STOP MODE ENHANCEMENTSSetting bit 1 of the Power Control register (PCON; 87h) invokes the Stop mode. Stop mode is the lowest
power state since it turns off all internal clocking. The ICC of a standard Stop mode is approximately 1 μA
(but is specified in the Electrical Specifications). The CPU will exit Stop mode from an external interruptor a reset condition. Internally generated interrupts are not useful since they require clocking activity.
The DS80C310 allows a resume from Stop using an INT2-5, which are edge-triggered interrupts. The
start-up timing is managed by an internal crystal counter. A delay of 65,536 clocks occurs to give the
crystal enough time to start and stabilize.
PERIPHERAL OVERVIEWThe DS80C310 provides the same peripheral functions as the standard 80C32. It is compatible with the
DS80C320 but does not offer all of the peripherals.
TIMER RATE CONTROLThere is one important difference between the DS80C310 and 8051 regarding timers. The original 8051
used 12 clocks per cycle for timers as well as for machine cycles. The DS80C310 architecture normallyuses 4 clocks per machine cycle. However, in the area of timers and serial ports, the DS80C310 will
default to 12 clocks per cycle on reset. This allows existing code with real-time dependencies such as
baud rates to operate properly.
If an application needs higher speed timers or serial baud rates, the user can select individual timers to runat the 4-clock rate. The Clock Control register (CKCON; 8Eh) determines these timer speeds. When the
relevant CKCON bit is a logic 1, the DS80C310 uses 4 clocks per cycle to generate timer speeds. When
the bit is a 0, the DS80C310 uses 12 clocks for timer speeds. The reset condition is a 0. CKCON.5 selects
the speed of Timer 2. CKCON.4 selects Timer 1 and CKCON.3 selects Timer 0. Note that unless a user
desires very fast timing, it is unnecessary to alter these bits. Note that the timer controls are independent.
DS87C520/DS83C520
POWER ON RESETThe DS80C310 will hold itself in reset during a power-up until 65,536 clock cycles have elapsed. The
power-on reset used by the DS80C310 differs somewhat from other members of the High-Speed
Microcontroller family. The crystal oscillator may start anywhere between 1.0V and 4.5V but is not
specified. This eliminates the need for an RC reset circuit. For voltage-specific precision brownout
detection, an external component will be needed. When the device goes through a power-on reset, thePOR flag will be set in the WDCON (D8h) register at bit 6.
INTERRUPTSThe DS80C310 provides 10 interrupt sources with two priority levels. Software can assign high or lowpriority to all sources. All interrupts that are new to the 8051 have a lower natural priority than the
originals.
INTERRUPT SOURCES AND PRIORITIES Table 4
DS87C520/DS83C520
ABSOLUTE MAXIMUM RATINGS*Voltage on Any Pin Relative to Ground -0.3V to +7.0V
Operating Temperature 0°C to 70°C
Storage Temperature -55°C to +125°C
Soldering Temperature 260°C for 10 secondsThis is a stress rating only and functional operation of the device at these or any other conditions
above those indicated in the operation sections of this specification is not implied. Exposure to
absolute maximum rating conditions for extended periods of time may affect reliability.
DC ELECTRICAL CHARACTERISTICS
NOTES FOR DC ELECTRICAL CHARACTERISTICS:All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
1. All voltages are referenced to ground.
2. Active current is measured with a 33 MHz clock source driving XTAL1, VCC =RST=5.5V, all other
DS87C520/DS83C520
3. Idle mode current is measured with a 33 MHz clock source driving XTAL1, VCC =5.5V, RST at
ground, all other pins disconnected.
4. Stop mode current measured with XTAL1 and RST grounded, VCC =5.5V, all other pinsdisconnected.
5. When addressing external memory.
6. RST=VCC. This condition mimics operation of pins in I/O mode.
7. During a 0 to 1 transition, a one-shot drives the ports hard for two clock cycles. This measurement
reflects port in transition mode.
8. Ports 1 and 3 source transition current when being pulled down externally. It reaches its maximum atapproximately 2V.
9. 0.45
is dedicated as an address bus on the DS80C310. Peak current occurs near the input transition point of
the latch, approximately 2V.
10. Current required from external circuit to hold a logic low level on an I/O pin while the corresponding
port latch bit is set to 1. This is only the current required to hold the low level; transitions from 1 to 0
on an I/O pin will also have to overcome the transition current.
TYPICAL ICC VERSUS FREQUENCY Figure 2
