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DS8024
Smart Card Interface
DS8024
Smart Card Interface
General DescriptionThe DS8024 smart card interface IC is a low-cost, analog
front-end for a smart card reader, designed for all ISO
7816, EMV®, and GSM11-11 applications. The DS8024
is a pin-for-pin drop-in replacement for the NXP
TDA8024 and is offered in 28-pin TSSOP and SO pack-
ages.
Applications requiring support for 1.8V smart cards or
requiring low power should consider the DS8113, which
achieves lower active- and stop-mode power with mini-
mal changes to application hardware and software.
ApplicationsSet-Top Box Conditional Access
Access Control
Banking Applications
POS Terminals
Debit/Credit Payment Terminals
PIN Pads
Automated Teller Machines
Telecommunications
Pay/Premium Television
FeaturesAnalog Interface and Level Shifting for IC Card
Communication±8kV (min) ESD (IEC) Protection on Card
InterfacesInternal IC Card Supply-Voltage Generation:
5.0V ±5%, 80mA (max)
3.0V ±8%, 65mA (max)Automatic Card Activation and Deactivation
Controlled by Dedicated Internal SequencerI/O Lines from Host Directly Level Shifted for
Smart Card CommunicationFlexible Card Clock Generation, Supporting
External Crystal Frequency Divided by 1, 2, 4, or 8High-Current, Short-Circuit and High-Temperature
Protection
Ordering Information
Note:Contact the factory for availability of other variants and
package options.
+Denotes a lead(Pb)-free/RoHS-compliant package.
/V denotes an automotive-qualified part.
EMV is a registered trademark of EMVCo LLC. EMV Level 1 library and hardware reference design available. Contact factory for
details.
Note:Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
PARTTEMP RANGEPIN-PACKAGEDS8024-RJX+ -40°C to +85°C 28 TSSOP
DS8024-RJX/V+ -40°C to +85°C 28 TSSOP
DS8024-RRX+ -40°C to +85°C 28 SO
Selector Guide appears at end of data sheet.PGND
AUX2IN
AUX1IN
I/OIN
XTAL2
TOP VIEW
DS8024
XTAL1
OFF
GNDVDDRSTINCMDVCCN.C.VCCRSTCLK
5V/3V
CLKDIV2
CLKDIV1
CP1
VDDA
VUP
PRES
PRES
I/O
AUX2
AUX1CGND
CP2
SO/TSSOP
Pin Configuration
DS8024
Smart Card Interface
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS(VDD= +3.3V, VDDA= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VDDRelative to GND...............-0.5V to +6.5V
Voltage Range on VDDARelative to PGND...........-0.5V to +6.5V
Voltage Range on CP1, CP2, and VUP
Relative to PGND...............................................-0.5V to +7.5V
Voltage Range on All Other Pins
Relative to GND......................................-0.5V to (VDD+ 0.5V)
Maximum Junction Temperature.....................................+125°C
Continuous Power Dissipation (multilayer board, TA= +70°C)
TSSOP (derate 14mW/°C above +70°C).................1117.3mW
SO (derate 16.7mW/°C above +70°C).....................1355.9mW
Storage Temperature Range.............................-55°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
POWER SUPPLY Digital Supply Voltage VDD 2.7 6.0 V
VCC=5V, |ICC| < 80mA 4.0 6.0 Card Voltage-Generator Supply Voltage VDDAVCC=5V, |ICC| < 30mA 3.0 6.0 V
VTH2 Threshold voltage (falling) 2.30 2.45 2.60 V Reset Voltage Thresholds VHYS2 Hysteresis 50 100 150 mV
CURRENT CONSUMPTION Active VDD Current 5V Cards
(Including 80mA Draw from 5V Card) IDD_50VICC = 80mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V 215 mA
Active VDD Current 5V Cards
(Current Consumed by DS8024 Only) IDD_ICICC = 80mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2) 135 mA
Active VDD Current 3V Cards
(Including 65mA Draw from 3V Card) IDD_30VICC = 65mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V 100 mA
Active VDD Current 3V Cards
(Current Consumed by DS8024 Only) IDD_ICICC = 65mA, fXTAL = 20MHz,
fCLK = 10MHz, VDDA = 5.0V (Note 2) 35 mA
Inactive-Mode Current IDD Card inactive 500 μA
CLOCK SOURCE Crystal Frequency fXTAL External crystal 0 20 MHz
fXTAL1 0 20 MHz
VIL_XTAL1 Low-level input on XTAL1 (Note 3) -0.3 0.3 x
VDDXTAL1 Operating Conditions
VIH_XTAL1 High-level input on XTAL1 (Note 3) 0.7 x
VDD
VDD +
External Capacitance for Crystal CXTAL1,
CXTAL2(Note 3) 15 pF
Internal Oscillator fINT 2.7 MHz
SHUTDOWN TEMPERATURE Shutdown Temperature TSD (Note 3) +150 °C
DS8024
Smart Card Interface
RECOMMENDED DC OPERATING CONDITIONS (continued)(VDD= +3.3V, VDDA= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
RST PIN Output Low Voltage VOL_RST1 IOL_RST = 1mA 0 0.3 V Card-Inactive Mode Output Current IOL_RST1 VO_LRST = 0V 0 -1 mA
Output Low Voltage VOL_RST2 IOL_RST = 200μA 0 0.3 V
Output High
Voltage VOH_RST2 IOH_RST = -200μA VCC -
0.5 VCC V
Rise Time tR_RST CL= 30pF (Note 3) 0.1 μs
Fall Time tF_RST CL= 30pF (Note 3) 0.1 μs
Shutdown Current
Threshold IRST(SD) -20 mA
Current Limitation IRST(LIMIT) -20 +20 mA
Card-Active Mode
RSTIN to RST Delay tD(RSTIN-RST) 2 μs
CLK PIN Output Low Voltage VOL_CLK1 IOLCLK = 1mA 0 0.3 V Card-Inactive Mode Output Current IOL_CLK1 VOLCLK = 0V 0 -1 mA
Output Low Voltage VOL_CLK2 IOLCLK = 200μA 0 0.3 V
Output High
Voltage VOH_CLK2 IOHCLK = -200μA VCC -
0.5 VCC V
Rise Time tR_CLK CL= 30pF (Note 3) 8 ns
Fall Time tF_CLK CL= 30pF (Note 3) 8 ns
Current Limitation ICLK(LIMIT) -70 +70 mA
Clock Frequency fCLK Operational (Note 3) 0 10 MHz
Duty Factor CL= 30pF (Note 3) 45 55 %
Card-Active Mode
Slew Rate SR CL= 30pF (Note 3) 0.2 V/ns
VCC PIN Output Low Voltage VCC1 ICC= 1mA 0 0.3 V Card-Inactive Mode Output Current ICC1 VCC = 0V 0 -1 mA
ICC(5V) < 80mA 4.75 5.00 5.25
ICC(3V) < 65mA 2.78 3.00 3.22
5V card: current pulses of 40nC
with I < 200mA, t < 400ns,
f < 20MHz (Note 3)
4.6 5.4 Output Low Voltage VCC2
3V card: current pulses of 24nC
with I < 200mA, t < 400ns,
f < 20MHz (Note 3)
2.75 3.25
VCC(5V) = 0 to 5V -80 Output Current ICC2VCC(3V) = 0 to 3V -65 mA
Shutdown Current
Threshold ICC(SD) 120 mA
Card-Active Mode
Slew Rate VCCSR Up/down, C < 300nF 0.05 0.16 0.22 V/μs
DS8024
Smart Card Interface
RECOMMENDED DC OPERATING CONDITIONS (continued)(VDD= +3.3V, VDDA= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
DATA LINES (I/O AND I/OIN) I/O I/OINFalling Edge Delay tD(IO-IOIN) (Note 3) 200 ns
Pullup Pulse Active Time tPU (Note 3) 100 ns
Maximum Frequency fIOMAX 1 MHz
Input Capacitance CI (Note 3) 10 pF
I/O, AUX1, AUX2 PINS Output Low VoltageVOL_IO1 IOL_IO = 1mA0 0.3 V
Output Current IOL_IO1 VOL_IO = 0V 0 -1 mA Card-Inactive Mode
Internal Pullup
Resistor RPU_IO To VCC 9 11 19 k
Output Low VoltageVOL_IO2 IOL_IO = 1mA 0 0.3V
Output High
Voltage VOH_IO2 IOH_IO = < -40μA (3V/5V) 0.75 x VCC VCC V
Output Rise/Fall
Time tOT CL= 30pF (Note 3) 0.1 μs
Input Low Voltage VIL_IO -0.3 +0.8
Input High Voltage VIH_IO 1.5 VCCV
Input Low Current IIL_IO VIL_IO = 0V 700 μA
Input High Current IIH_IO VIH_IO = VCC 20 μA
Input Rise/Fall Time tIT (Note 3) 1.2 μs
Current Limitation IIO(LIMIT) CL= 30pF -15 +15 mA
Card-Active Mode
Current When
Pullup Active IPUCL= 80pF, VOH = 0.9 x VDD
(Note 3) -1 mA
I/OIN, AUX1IN, AUX2IN PINS Output Low Voltage VOL IOL = 1mA 0 0.3 V
Output High Voltage VOH IOH < -40μA 0.75 x
VDD
VDD +
0.1V
Output Rise/Fall Time tOT CL= 30pF, 10% to 90% (Note 3) 0.1 μs
Input Low Voltage VIL -0.3 0.3 x
VDDV
Input High Voltage VIH0.7 x
VDD
VDD +
0.3V
Input Low Current IIL_IO VIL = 0V 600 μA
Input High Current IIH_IO VIH = VDD 10 μA
Input Rise/Fall Time tIT VIL to VIH (Note 3) 1.2 μs
Integrated Pullup Resistor RPU Pullup to VDD 9 11 13 k
Current When Pullup Active IPUCL= 30pF, VOH = 0.9 x VDD
(Note 3) -1 mA
DS8024
Smart Card Interface
RECOMMENDED DC OPERATING CONDITIONS (continued)(VDD= +3.3V, VDDA= +5.0V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
CONTROL PINS (CLKDIV1, CLKDIV2, CMDVCC, RSTIN, 5V/3V)Input Low Voltage VIL -0.3 0.3 x
VDDV
Input High Voltage VIH0.7 x
VDD
VDD +
0.3V
Input Low Current IIL_IO 0 < VIL < VDD 5 μA
Input High Current IIH_IO 0 < VIH < VDD 5 μA
Integrated Pullup Resistor RPU Pullup to VDD, 5V/3V only 50 85 120 kĀ
INTERRUPT OUTPUT PIN (OFF) Output Low Voltage VOL IOL = 2mA 0 0.3 V
Output High Voltage VOH IOH = -15μA 0.75 x
VDD V
Integrated Pullup Resistor RPU Pullup to VDD 12 20 28 k
PRES, PRES PINS Input Low Voltage VIL_PRES 0.3 x
VDDV
Input High Voltage VIH_PRES 0.7 x
VDD V
Input Low Current IIL_PRES VIL_PRES = 0V 40 μA
Input High Current IIH_PRES VIH_PRES = VDD 40 μA
TIMING Activation Time tACT 160 μs
Deactivation Time tDEACT 80 μs
Window Start t3 95 CLK to Card Start
Time Window End t5 160 μs
PRES/PRES Debounce Time tDEBOUNCE 8 ms
Note 1:Operation guaranteed at TA= -40°C and TA= +85°C, but not tested.
Note 2:IDD_IC measures the amount of current used by the DS8024 to provide the smart card current minus the load.
Note 3:Guaranteed by design, but not production tested.
DS8024
Smart Card Interface
Pin Description
PINNAMEFUNCTION1, 2 CLKDIV1,
CLKDIV2
Clock Divider. Determines the divided-down input clock frequency (presented at XTAL1 or from a
crystal at XTAL1 and XTAL2) on the CLK output pin. Dividers of 1, 2, 4, and 8 are available.
3 5V/3V
5V/3V Selection Pin. Allows selection of 5V or 3V for communication with an IC card. Logic-high selects
5V operation; logic-low selects 3V operation. See Table 3 for a complete description of choosing card
voltages.
4 PGND Analog Ground
5, 7 CP2, CP1 Step-Up Converter Contact. Charge-pump capacitor. Connect a 100nF capacitor (ESR < 100mĀ)
between CP1 and CP2.
6 VDDA Charge-Pump Supply. Must be equal to or higher than VDD. Connect a supply of at least 3.3V.
8 VUP Charge-Pump Output. Connect a 100nF capacitor (ESR < 100mĀ) between VUP and GND. PRESCard Presence Indicator. Active-low card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
10 PRES Card Presence Indicator. Active-high card presence inputs. When the presence indicator becomes
active, a debounce timeout begins. After 8ms (typ) the OFF signal becomes active.
11 I/O Smart Card Data-Line Output. Card data communication line, contact C7.
12, 13 AUX2,
AUX1
Smart Card Auxiliary Line (C4, C8) Output. Data line connected to card reader contacts C4 (AUX1) and
C8 (AUX2).
14 CGND Smart Card Ground
15 CLK Smart Card Clock. Card clock, contact C3.
16 RST Smart Card Reset. Card reset output from contact C2.
17 VCCSmart Card Supply Voltage. Decouple to CGND (card ground) with 2 x 100nF or 100 + 220nF
capacitors (ESR < 100m).
18 N.C. No Connection. Unused on the DS8024. CMDVCC Activation Sequence Initiate. Active-low input from host.
20 RSTIN Card Reset Input. Reset input from the host.
21 VDD Supply Voltage
22 GND Digital Ground OFF Status Output. Active-low interrupt output to the host. Use a 20k integrated pullup resistor to VDD.
24, 25 XTAL1,
XTAL2
Crystal/Clock Input. Connect an input from an external clock to XTAL1 or connect a crystal across
XTAL1 and XTAL2. For the low idle-mode current variant, an external clock must be driven on XTAL1.
26 I/OIN I/O Input. Host-to-interface chip data I/O line.
27, 28 AUX1IN,
AUX2IN C4/C8 Input. Host-to-interface I/O line for auxiliary connections to C4 and C8.
DS8024
Smart Card Interface
Detailed DescriptionThe DS8024 is an analog front-end for communicating
with 3V and 5V smart cards. Using an integrated
charge pump, the DS8024 can operate from a single
input voltage. The device translates all communication
lines to the correct voltage level and provides power for
smart card operation. It can operate from a wide input
voltage range (3.3V to 6.0V). The DS8024 is compatible
with the NXP TDA8024 and is provided in the same
packages. (Note that the PORADJ pin is not present in
the DS8024. Most applications do not make use of this
input pin, instead using the DS8024’s default reset
threshold.)
Power SupplyThe DS8024 can operate from a single supply or a dual
supply. The supply pins for the device are VDD, GND,
VDDA, and PGND. VDDshould be in the range of 2.7V
to 6.0V, and is the supply for signals that interface with
the host controller. It should, therefore, be the same
supply as used by the host controller. All smart card
contacts remain inactive during power on or power off.
The internal circuits are kept in the reset state until VDD
reaches VTH2+ VHYS2and for the duration of the inter-
nal power-on reset pulse, tW. A deactivation sequence
is executed when VDDfalls below VTH2.
An internal charge pump and regulator generate the
3V or 5V card supply voltage (VCC). The charge pump
and regulator are supplied by VDDAand PGND. VDDA
should be connected to a minimum 3.3V (maximum
6.0V) supply and should be at a potential that is equal
to or higher than VDD.
The charge pump operates in a 1x (voltage follower) or
2x (voltage doubler) mode depending on the input
VDDAand the selected card voltage (5V or 3V).For 5V cards, the DS8024 operates in a 1x mode
for VDDA> 5.8V and in a 2x mode for VDDA< 5.8V.For 3V cards, the DS8024 operates in a 1x mode
for VDDA> 4.1V and in a 2x mode for VDDA< 4.0V.
Voltage SupervisorThe voltage supervisor monitors the VDDsupply. A
220µs reset pulse (tW) is used internally to keep the
device inactive during power on or power off of the VDD
supply. See Figure 2.
TEMPERATURE
MONITOR
CARD VOLTAGE
GENERATOR
AND
CHARGE PUMP
CLOCK
GENERATION
CONTROL
SEQUENCER
POWER-SUPPLY
SUPERVISOR
I/O TRANSCEIVER
VDD
GND
VDDA
PGND
CP1
CP2
VUP
VCC
XTAL1
XTAL2
CLKDIV1
CLKDIV2
5V/3V
CMDVCC
RSTIN
CGND
RST
CLK
PRES
PRES
I/O
AUX1
AUX2
OFF
I/OIN
AUX1IN
AUX2IN
DS8024
Figure 1. Functional Diagram
VDD
ALARM
(INTERNAL SIGNAL)
POWER ONtW
POWER OFF
VTH2 + VHYS2
VTH2
SUPPLY DROPOUT
Figure 2. Voltage Supervisor Behavior
DS8024
Smart Card InterfaceThe DS8024 card interface remains inactive no matter
the levels on the command lines until duration tWafter
VDDhas reached a level higher than VTH2+ VHYS2.
When VDDfalls below VTH2, the DS8024 executes a
card deactivation sequence if its card interface is
active.
Clock CircuitryThe clock signal from the DS8024 to the smart card
(CLK) is generated from the clock input on XTAL1 or
from a crystal operating at up to 20MHz connected
between pins XTAL1 and XTAL2. The inputs CLKDIV1
and CLKDIV2 determine the frequency of the CLK sig-
nal, which can be fXTAL, fXTAL/2, fXTAL/4, or fXTAL/8.
Table 1 shows the relationship between CLKDIV1 and
CLKDIV2 and the frequency of CLK.
Do not change the state of pins CLKDIV1 and CLKDIV2
simultaneously; a delay of 10ns minimum between
changes is required. The minimum duration of any state
of CLK is 8 periods of XTAL1.
The hardware in the DS8024 guarantees that the fre-
quency change is synchronous. During a transition of
the clock divider, no pulse is shorter than 45% of the
smallest period, and the clock pulses before and after
the instant of change have the correct width.
To achieve a 45% to 55% duty factor on pin CLK when
no crystal is present, the input signal on XTAL1 should
have a 48% to 52% duty factor. Transition time on
XTAL1 should be less than 5% of the period.
With a crystal, the duty factor on pin CLK may be 45%
to 55% depending on the circuit layout and on the crys-
tal characteristics and frequency.
The DS8024 crystal oscillator runs when the device is
powered up. If the crystal oscillator is used or the clock
pulse on pin XTAL1 is permanent, the clock pulse is
applied to the card at time t4(see Figures 7 and 8). If
the signal applied to XTAL1 is controlled by the host
microcontroller, the clock pulse is applied to the card
when it is sent by the system microcontroller (after
completion of the activation sequence).
I/O TransceiversThe three data lines I/O, AUX1, and AUX2 are identical.
This section describes the characteristics of I/O and
I/OIN but also applies to AUX1, AUX1IN, AUX2, and
AUX2IN.
I/O and I/OIN are pulled high with an 11kΩresistor (I/O
to VCCand I/OIN to VDD) in the inactive state. The first
side of the transceiver to receive a falling edge
becomes the master. When the master is decided, the
opposite side switches to slave mode, ignoring subse-
quent edges until the master releases. After a time delay
tD(EDGE), an n transistor on the slave side is turned on,
thus transmitting the logic 0 present on the master side.
When the master side asserts a logic 1, a p transistor
on the slave side is activated during the time delay tPU
and then both sides return to their inactive (pulled up)
states. This active pullup provides fast low-to-high tran-
sitions. After the duration of tPU, the output voltage
depends only on the internal pullup resistor and the
load current. Current to and from the card I/O lines is
limited internally to 15mA. The maximum frequency on
these lines is 1MHz.
Inactive ModeThe DS8024 powers up with the card interface in the
inactive mode. Minimal circuitry is active while waiting
for the host to initiate a smart card session.All card contacts are inactive (approximately 200Ω
to GND).Pins I/OIN, AUX1IN, and AUX2IN are in the high-
impedance state (11kΩpullup resistor to VDD).Voltage generators are stopped.XTAL oscillator is running (if included in the device).Voltage supervisor is active.The internal oscillator is running at its low frequency.
Activation SequenceAfter power-on and the reset delay, the host microcon-
troller can monitor card presence with signals OFFand
CMDVCC, as shown in Table 2.
Table 1. Clock Frequency Selection
CLKDIV1CLKDIV2fCLK0 0 fXTAL/8
0 1 fXTAL/4
1 1 fXTAL/2
1 0 fXTAL
Table 2. Card Presence IndicationOFFCMDVCC
STATUSHigh High Card present.
Low High Card not present.
