DS8007-ENG+ ,Multiprotocol Dual Smart Card InterfaceELECTRICAL CHARACTERISTICS(V = +3.3V, V = +3.3V, T = +25°C, unless otherwise noted.) (Note 1)DD DDA ..
DS8007-ENG+ ,Multiprotocol Dual Smart Card InterfaceApplications (Point-of-Sale Terminals,Debit/Credit Payment Terminals, PIN Pads,Automated Teller Mac ..
DS8007-KIT ,DS8007 EMV Evaluation KitApplications Usingto conveniently evaluate the capabilities of the DS8007EMV Certified Library and ..
DS8023 ,Smart Card Interfaceapplications. The♦ ±8kV (min) ESD (IEC) Protection on Card InterfaceDS8023 supports 5V, 3V, and 1.8 ..
DS8024 ,Smart Card InterfaceApplications requiring support for 1.8V smart cards or5.0V ±5%, 80mA (max)requiring low power shoul ..
DS80C310 ,High-Speed Microapplications will see a speed improvement of 2.5 times using the same code and the same crystal. Th ..
ECH8401 ,Medium Output MOSFETsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8402 ,Medium Output MOSFETsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8402 ,Medium Output MOSFETsOrdering number : ENN8148 ECH8402N-Channel Silicon MOSFETGeneral-Purpose Switching DeviceECH8402App ..
ECH8410 ,N-Channel Power MOSFET, 30V, 12A, 10mOhm, Single ECH8Maximum RatingsParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage V 30 VDSSGate-to-Sou ..
ECH8601 ,Nch+NchAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8604 ,N CHANNEL MOS SILICON TRANSISTOR
DS8007-DS8007-ENG+
Multiprotocol Dual Smart Card Interface
DS8007
Multiprotocol Dual Smart Card Interface
General DescriptionThe DS8007 multiprotocol dual smart card interface is a
low-cost, dual smart card reader interface supporting
all ISO 7816, EMV®, and GSM11-11 requirements.
Through its 8-bit parallel bus and dedicated address
selects (AD3–AD0), the DS8007 can easily and directly
connect to the nonmultiplexed byte-wide bus of a
Maxim secure microcontroller. Optionally, the parallel
bus can be multiplexed to allow direct access to the
multiplexed bus of an 80C51-compatible microcon-
troller through MOVX memory addressing.
One integrated ISO 7816 UART is multiplexed among
the interfaces to allow high-speed automatic smart card
processing with each card-possessing, independent,
variable, baud-rate capability. The card interface is con-
trolled by internal sequencers that support automatic
activation and deactivation sequencing, handling all
actions required for T = 0, T = 1, and synchronous pro-
tocols. Emergency deactivation is also supported in
case of supply dropout. A third card is supported
through the auxiliary I/O. The same set of I/O can option-
ally be used as additional serial interface for the UART.
The DS8007 provides all electrical signals necessary to
interface with two smart cards. The integrated voltage
converter ensures full cross-compatibility between 1.8V/
3V/5V cards and a 1.8V/3V/5V environment, and allows
operation within a 2.7V to 6V supply voltage range.
ApplicationsBanking Applications (Point-of-Sale Terminals,
Debit/Credit Payment Terminals, PIN Pads,
Automated Teller Machines)
Telecommunications
Pay Television
Access Control
FeaturesIntegrated ISO 7816 UART Provides Complete
Interface/Control for Two Separate Smart CardDevices8kV (min) ESD Protection on Card InterfacesInternal IC Card Supply Voltage Generation
5.0V ±5%, 65mA (max)
3.0V ±8%, 50mA (max)
1.8V ±10%, 30mA (max)Automatic Card Activation, Deactivation, and Data
Communication Controlled by Dedicated Internal
SequencerHost Interface Through an 8-Bit Parallel Bus (User-
Selectable Multiplexed or Nonmultiplexed Modes)Chip Select and Three-State Bus Allow Multiple
Devices (Card Readers and Memories) on Bus8-Character Receive FIFO with Optional
Programmable Depth/ThresholdI/O Interface Pin to External ISO 7816 UART for
Auxiliary InterfaceSeparate Card Clock Generation (Up to 10MHz)with 2x Frequency DoublingSelectable Card Clock Stop High, Stop Low, or
Internally Generated 1.25MHz (for Card Power-
Down)EMV-Certified Reference Design and Evaluation
Kit Available (DS8007-KIT)19-5972; Rev 3; 7/11
EVALUATION KIT
AVAILABLE
Ordering Information
PARTTEMP RANGE
SMART
CARDS
SUPPORTED
PIN-
PACKAGEDS8007-ENG-40°C to +85°C2 + auxiliary48 LQFP
DS8007-ENG+-40°C to +85°C2 + auxiliary48 LQFP
+Denotes a lead(Pb)-free/RoHS-compliant package.
EMV is a registered trademark of EMVCo LLC.
MAXQ is a registered trademark of Maxim Integrated Products, Inc.
Note:Some revisions of this device may incorporate devia-
tions from published specifications known as errata. Multiple
revisions of any device may be simultaneously available
through various sales channels. For information about device
VDD
CPA2
AGND
RSTOUT
I/OAUX
I/OA
C8A
PRESA
C4A
GNDA
CLKA
VCCA
RSTA
I/OB
C8B14151617181920212223244746454443424140393837
PRESB
C4B
GNDB
CLKB
CCB
RSTB
GND
CPA1CPB1
DDA
CPB2
DELAYXTAL1XTAL2AD0AD1AD2AD3INTAUXINTALECSWR
LQFPDS8007
Pin Configuration
DS8007
Multiprotocol Dual Smart Card Interface
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= +3.3V, VDDA= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VDDRelative to Ground...........-0.5V to +6.5V
Voltage Range on VDDARelative to Ground.........-0.5V to +6.5V
Voltage Range on Any Pin Relative to Ground
Pins CPA1, CPA2, CPB1, CPB2, and VUP.........-0.5V to +7.5V
All Other Pins...........................................-0.5V to (VDD+ 0.5V)
Maximum Junction Temperature.....................................+150°C
Continuous Power Dissipation (TA= +70°C)
LQFP Multilayer Board
(derate 22mW/°C above +70°C).................................1782mW
Operating Temperature Range...........................-40°C to +85°C
Storage Temperature Range.............................-65°C to +150°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Digital Supply Voltage VDD 2.7 6.0 V
Step-Up Converter Supply
Voltage VDDA VDD 6.0 V
Cards Inactive fXTAL = 0MHz 0.9 Power-Down
VDD Current Cards Active
IPD
fXTAL = 0MHz, fCLK = 0MHz, VCCx = 5V 2.2
mA
Sleep Mode VDD Current
(Cards Active) ISTOP fCLK = 0MHz, VCCx = 5V 24 mA
Active VDD Current
5V Cards IDD
3x VDD step-up:
ICCA + ICCB = 80mA, VDD = 2.7V,
fXTAL = 20MHz, fCLK = 10MHz 325 mA
2x VDD step-up:
ICCA + ICCB = 80mA, fXTAL = 20MHz,
fCLK = 10MHz, VDD = 2.7V 225
Active VDD Current
3V Cards IDDNo step-up:
ICCA + ICCB = 80mA, fXTAL = 20MHz,
fCLK = 10MHz, VDD = 5V 120
mA
VRST Threshold voltage (falling) 2.1 2.5 V Power-Fail Reset Voltage VHYS Hysteresis 50 170 mV
Reset
Threshold VDRST 1.25
Output Voltage VDO VDD +
0.3
VDELAY = 0V -2 μA Output Current IDOVDELAY = VDD +2 mA
Delay Pin
Output
Capacitance CDO 1 nF
RSTOUT PIN Output High Voltage VOHRSTO IOH = -1mA 0.8 x
VDD
VDD +
0.3 V
Output Low Voltage VOLRSTO IOL = 2mA -0.3 +0.4 V
Leakage Current IL VOL = 0V, VOH = 5V -10 +10 μA
DS8007
Multiprotocol Dual Smart Card Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= +3.3V, VDDA= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Alarm Pulse Width tW CDELAY = 22nF 10 ms
External crystal 4 20 External Clock Frequency fXTALExternal oscillator 0 20 MHz
Internal Oscillator fINT 1.6 2.5 3.7 MHz
3x step-up 5.7 Voltage on VUP Pin VUP2x step-up 4.1 V
Voltage Detection of VDDA for 2x,
3x Step-Up VDET 3.35 3.50 3.60 V
Shutdown Temperature TSD +150 °C
Output Low
Voltage VOLRST IOLRST = 1mA 0 0.3 V Card
Inactive
Mode Output Current IOLRST VOLRST = 0V 0 -1 mA
Output Low
Voltage VOLRSTL IOLRST = +200μA 0 0.3
Output High
Voltage VOHRSTH IOHRST = -200μA VCCx –
0.5 VCCx
Rise Time tRRST CL = 30pF 0.1
Fall Time tFRST CL = 30pF 0.1 μs
Shutdown
Current IRST(SD) -25
RSTx
Pins Card
Active
Mode
Current
Limitation IRST(LIMIT) -25 +25
mA
Output Low
Voltage VOLCLK IOLCLK = 1mA 0 0.3 V Card
Inactive
Mode Output Current IOLCLK VOLCLK = 0V 0 -1 mA
Output Low
Voltage VOLCLK IOLCLK = +200μA 0 0.3
Output High
Voltage VOHCLK IOHCLK = -200μA VCCx –
0.5 VCCx
Rise Time tRCLK CL = 30pF (Note 2) 8
Fall Time tFCLK CL = 30pF (Note 2) 8 ns
Card
Active
Mode
Current
Limitation ICLK(LIMIT) -70 +70 mA
Idle configuration (1MHz) 1 1.85
CLKx
Pins
Clock Frequency fCLKOperational 0 10 MHz
Duty Factor CL = 30pF 45 55 %
DS8007
Multiprotocol Dual Smart Card Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= +3.3V, VDDA= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Low
Voltage VCCx ICC = 1mA 0 0.3 V Card
Inactive
Mode Output Current ICC VCCx = 0V 0 -1 mA
ICC(5V) < 65mA 4.75 5.00 5.25
ICC(3V) < 50mA 2.78 3.00 3.22
ICC(1.8V) < 30mA 1.65 1.80 1.95
5V card, current pulses of 40nC with
I < 200mA, t < 400ns, f < 20MHz 4.6 5.4
3V card, current pulses of 24nC with
I < 200mA, t < 400ns, f < 20MHz 2.75 3.25
Output Low
Voltage VCCx
1.8V card, current pulses of 12nC with
I < 200mA, t < 400ns, f < 20MHz 1.62 1.98
VCCx(5V) = 0 to 5V -65
VCCx(3V) = 0 to 3V -50 Output Current ICC
VCCx(1.8V) = 0 to 1.8V -30
Total Current
(Two Cards) ICC(A+B) -80
Shutdown
Current ICC(SD) -100
mA
VCCx
Pins Card
Active
Mode
Slew Rate VCCSR Up/down, C < 300nF (Note 3) 0.05 0.16 0.05 V/μs
Output Low
Voltage VOLIO IOLIO = 1mA 0 0.3 V
Output Current IOLIO VOLIO = 0V 0 -1 mA
Card
Inactive
Mode Internal Pullup
Resistor RPULLUP To VCCx 9 14 19 k
Output Low
Voltage VOLIO IOLIO = 1mA 0 0.3
IOHIO -20μA 0.8 x VCCx VCCxOutput High
Voltage VOHIOIOHIO -40μA (3V/5V) 0.75 x VCCx VCCx
Output
Rise/Fall Time tOT CL = 30pF 0.1 μs
Input Low
Voltage VILIO -0.3 +0.8
Input High
Voltage VIHIO 1.5 VCCx
Input Low
Current IILIO VILIO = 0V 700
Input High
Current IIHIO VIHIO = VCCx 20
μA
Input Rise/Fall
Time tIT CL = 30pF 1.2 μs
I/Ox
Pins
Card
Active
Mode
Current
Limitation IIO(LIMIT) -25 +25 mA
DS8007
Multiprotocol Dual Smart Card Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= +3.3V, VDDA= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Low
Voltage VOLC48 IOLC48 = 1mA 0 0.3 V
Output Current IOLC48 VOLC48 = 0V 0 -1 mA
Card
Inactive
Mode Internal Pullup
Resistor RPULLUP Between C4 or C8 and VCCx 6 10 14 k
Output Low
Voltage VOLC48 IOLC48 = 1mA 0 0.3
IOHC48 -20μA 0.8 x VCCx VCCxOutput High
Voltage VOHC48IOHC48 -40μA (3V/5V) 0.75 x VCCx VCCx
Output
Rise/Fall Time tOT CL = 30pF 0.1 μs
Input Low
Voltage VILC48 -0.3 +0.8
Input High
Voltage VIHC48 1.5 VCCx
Input Low
Current IILC48 VILIO = 0V 850
Input High
Current IIHC48 VIHIO = VCCx 20
μA
Input Rise/Fall
Time tIT CL = 30pF 1.2 μs
Pullup Pulse
Width tWPU Active pullup 200 ns
C4x,
C8x
Pins
Card
Active
Mode
Operating
Frequency fMAX On card contact pins 1 MHz
TIMING Activation Sequence Duration tACT See Figure 9 130 μs
Deactivation Sequence Duration tDE See Figure 9 150 μs
PRESA/PRESB PINS Input Low Voltage VILPRES 0.25 x VDD V
Input High Voltage VIHPRES 0.7 x VDD V
Input Low Current IILPRES VILPRES = 0V 40 μA
Input High Current IIHPRES VIHPRES = VDD 40 μA
I/OAUX PIN Internal Pullup Resistor RPULLUP Between I/OAUX and VDD 9 14 19 k
Output Low Voltage VOLAUX IOLAUX = 1mA 0.3 V
Output High Voltage VOHAUX IOHAUX = 40μA (3V/5V) 0.75 x VDD VDD V
Output Rise/Fall Time tOT CL = 30pF 0.1 μs
DS8007
Multiprotocol Dual Smart Card Interface
ELECTRICAL CHARACTERISTICS (continued)(VDD= +3.3V, VDDA= +3.3V, TA= +25°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Low Voltage VILAUX -0.3 0.3 x
VDDV
Input High Voltage VIHAUX0.7 x
VDD VDD V
Input Low Current IILAUX VILAUX = 0V 700 μA
Input High Current IIHAUX VIHAUX = VDD -20 +20 μA
Input Rise/Fall Time tIT CL = 30pF 1.2 μs
INTERRUPT PIN Output Low Voltage VOLINT IOH = 2mA 0.3 V
Input High Leakage Current ILIHINT 10 μA
D7 TO D0, ALL OTHER LOGIC PINS Output Low Voltage VOLD IOLD = +5mA 0.2 x
VDDV
Output High Voltage VOHD IOHD = -5mA 0.8 x
VDD VDD V
Output Rise/Fall Time tOT CL = 50pF 25 ns
Input Low Voltage VILD 0.3 x
VDDV
Input High Voltage VIHD0.7 x
VDD V
Input Low Current IILD -20 +20 μA
Input High Current IIHD -20 +20 μA
Load Capacitance CLD 10 pF
Note 1:Operation guaranteed at -40°C and +85°C but not tested.
Note 2:Parameters are guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the maxi-
mum rise and fall time is 10ns.
Note 3:Parameter is guaranteed to meet all ISO 7816, GSM11-11, and EMV 2000 requirements. For the 1.8V card, the minimum
slew rate is 0.05V/µs and the maximum slew rate is 0.5V/µs.
DS8007
Multiprotocol Dual Smart Card Interface
AC ELECTRICAL SPECIFICATIONS—TIMING PARAMETERS FOR MULTIPLEXED
PARALLEL BUS(VDD= 3.3V, VDDA= 3.3V, TA= +25°C, unless otherwise noted.) (Figure 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS XTAL1 Cycle Time tCY(XTAL1) 50 ns
ALE Pulse Width tW(ALE) 20 ns
Address Valid to ALE Low tAVLL 10 ns
ALE Low to RD or WR Low t(AL-RWL) 10 ns
Register URR 2 x tCY(XTAL1)RD Pulse Width tW(RD)Other registers 10 ns
RD Low to Data Read Valid t(RL-DV) 50 ns
WR/RD High to ALE High t(RWH-AH) 10 ns
WR Pulse Width tW(WR) 10 ns
Data Write Valid to WR Low t(DV-WL) 10 ns
ALE
D7–D0
ADDRESSADDRESSDATA
(READ)
DATA
(WRITE)
tW(ALE)
tAVLLt(AL-RWL)
tW(RD)
t(RL-DV)
t(RWH-AH)
t(DV-WL)
t(RWH-AH)
tW(WR)
Figure 1. Multiplexed Parallel Bus Timing
DS8007
Multiprotocol Dual Smart Card InterfaceDATA IN
ADDRESS
WRITE
RELEASE
WITH CS
WRITE
RELEASE
WITH EN
DATA OUT
ADDRESS
READ
WRITEWR (EN)
RD (R/W)
AD3–AD0
D7–D0
WR (EN)
WR (EN)
RD (R/W)
AD3–AD0
D7–D0t3
AC ELECTRICAL SPECIFICATIONS—TIMING PARAMETERS FOR NONMULTIPLEXED
PARALLEL BUS (READ AND WRITE)(VDD= 3.3V, VDDA= 3.3V, TA= +25°C, unless otherwise noted.) (See Figure 2.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSRD High to CS Lowt110ns
Access Time CS Low to Data Out Validt250ns
CS High to Data Out High Impedancet310ns
Data Valid to End of Writet410ns
Data Hold Timet510ns
RD Low to CS or WR Lowt610ns
Address Stable to CS or WR Hight710ns
Address to CS Lowt810ns
DS8007
Multiprotocol Dual Smart Card Interface
AC ELECTRICAL SPECIFICATIONS—TIMING PARAMETERS FOR CONSECUTIVE
READ/WRITE TO URR/UTR/TOC(VDD= 3.3V, VDDA= 3.3V, TA = +25°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
SEE FIGURE 3 RD Pulse Width tW(RD) 10 ns
RD Low to Bit CRED = 1 tRD(URR)tW(RD) +
2tCY(CLK)
tW(RD) +
3tCY(CLK)ns
Set Time Bit FE tSB(FE) 10.5 ETU
Set Time Bit RBF tSB(RBF) 10.5 ETU
SEE FIGURE 4 WR/CS Pulse Width tW(WR) (Note 4) 10 ns
WR/CS Low to I/Ox Low tWR(UTR)tW(WR) +
2tCY(CLK)
tW(WR) +
3tCY(CLK)ns
SEE FIGURE 5 WR/CS Pulse Width tW(WR) 10 ns
WR/CS High to Bit CRED = 1 tWR(TOC) (Notes 4 and 5) 1 / PSC 2 / PSC ETU
tSB(RBF)
tW(RD)
tSB(FE)
I/Ox
RBF BIT
FE BIT
INT
CRED BITtRD(URR)
Figure 3. Timing Between Two Read Operations in Register URR
Note 4:Depends on the leading edge of WRor CS(whichever is deasserted first). Reference this specification to the rising edge
of CS/WRinstead of the falling edge.
Note 5:PSC is the programmed prescaler value (31 or 32).
DS8007
Multiprotocol Dual Smart Card InterfacetW(WR)
tWR(UTR)
I/Ox
TBE BIT
WR/CS
CRED BIT
INT
Figure 4. Timing Between Two Write Operations in Register UTR
tWR(TOC)
tW(WR)WR/CS
CRED BIT
Figure 5. Timing Between Two Write Operations in Register TOC
DS8007
Multiprotocol Dual Smart Card Interface
Pin Description
PINNAMEFUNCTION1 RSTOUT
Reset Output. This active-high output is provided for resetting external devices. The RSTOUT pin is driven
high until the DELAY pin reaches VDRST. Once the DELAY pin reaches VDRST, the RSTOUT pin is three-
stated so it can externally be pulled down. The SUPL bit is set for each RSTOUT pulse. I/OAUX Auxiliary I/O. This I/O pin allows connection to an auxiliary smart card interface.
3 I/OA Smart Card A I/O Data Line. This is the I/O data line associated with smart card A. This is also referred to
as the ISO C7 contact.
4 C8A Smart Card A Auxiliary I/O. This is an auxiliary I/O associated with smart card A. This is also referred to
as the ISO C8 contact. This can be associated with synchronous cards. PRESA Smart Card A Presence Contact. This is the active-high presence contact associated with smart card A.
6 C4A Smart Card A Auxiliary I/O. This is an auxiliary I/O associated with smart card A. This is also referred to
as the ISO C4 contact. This can be associated with synchronous cards. GNDA Smart Card A Ground. This must be connected to GND.
8 CLKA Smart Card A Clock Output. This is the clock output associated with smart card A. This is also referred to
as the ISO C3 contact.
9 VCCASmart Card A Supply Voltage. This is the supply voltage output associated with smart card A. This is also
referred to as the ISO C1 contact.
10 RSTA Smart Card A Reset. This is the reset output associated with smart card A. This is also referred to as the
ISO C2 contact.
11 I/OB Smart Card B I/O Data Line. This is the I/O data line associated with smart card B. This is also referred to
as the ISO C7 contact.
12 C8B Smart Card B Auxiliary I/O. This is an auxiliary I/O associated with smart card B. This is also referred to
as the ISO C8 contact. This can be associated with synchronous cards.
13 PRESB Smart Card B Presence Contact. This is the active-high presence contact associated with smart card B.
14 C4B Smart Card B Auxiliary I/O. This is an auxiliary I/O associated with smart card B. This is also referred to
as the ISO C4 contact. This can be associated with synchronous cards.
15 GNDB Smart Card B Ground. This must be connected to GND.
16 CLKB Smart Card B Clock Output. This is the clock output associated with smart card B. This is also referred to
as the ISO C3 contact.
17 VCCBSmart Card B Supply Voltage. This is the supply voltage output associated with smart card B. This is also
referred to as the ISO C1 contact.
18 RSTB Smart Card B Reset. This is the reset output associated with smart card B. This is also referred to as the
ISO C2 contact.
19 GND Ground
20 VUP Step-Up Converter Connection. Connect a low-ESR capacitor of 220nF between this pin and ground.
21 CPA1 Step-Up Converter Contact 1. Connect a low-ESR capacitor of 220nF between CPA1 and CPA2.
22 CPB1 Step-Up Converter Contact 3. Connect a low-ESR capacitor of 220nF between CPB1 and CPB2.
23 VDDAAnalog Supply Voltage. Positive analog-supply voltage for the step-up converter; can be higher but not
lower than VDD. This pin should be decoupled to AGND with a good quality capacitor.
DS8007
Multiprotocol Dual Smart Card Interface
Pin Description (continued)
PINNAMEFUNCTION24 CPB2 Step-Up Converter Contact 4. Connect a low-ESR capacitor of 220nF between CPB1 and CPB2.
25 AGND Analog Ground
26 CPA2 Step-Up Converter Contact 2. Connect a low-ESR capacitor of 220nF between CPA1 and CPA2.
27 VDD Digital Supply Voltage. This pin should be decoupled to GND with a good quality capacitor.
28–35 D0–D7 8-Bit Digital I/O. This port functions as the data or address/data communication lines between the host
controller and the DS8007 for the nonmultiplexed and multiplexed operating modes, respectively. RD
Active-Low Parallel Bus Read Strobe Input. In multiplexed mode, this input indicates when the host
processor is reading information from the DS8007. In nonmultiplexed mode, this pin signals the current
operation is a read (RD = 1) or a write (RD = 0) when CS and WR are low. WR
Active-Low Parallel Bus Write Strobe Input. In multiplexed mode, this input indicates when the host
processor is writing information to the DS8007. In nonmultiplexed mode, a low on this pin signals the bus
is engaged in a read or write operation. CS Active-Low Chip-Select Input. This input indicates when the DS8007 is active on the parallel bus.
39 ALE Address Latch Enable Input. This signal monitors the ALE signal when the host processor bus is
operating in multiplexed mode. Connect this signal to VDD when operating in nonmultiplexed mode. INT Active-Low Interrupt. This output indicates an interrupt is active.
41 INTAUX Auxiliary Interrupt Input. This pin serves as an auxiliary interrupt.
42–45 AD3–AD0 Register Selection Address Inputs. These pins function as the address input lines for the nonmultiplexed
configuration and should be connected to ground or VDD in the multiplexed configuration.
46, 47 XTAL2,
XTAL1
Crystal Oscillators. Place a crystal with appropriate load capacitors between these pins if that is the
desired clock source. XTAL1 also acts as an input if there is an external clock source in place of a
crystal.
48 DELAY External Delay Capacitor Connection. Connect a capacitor from this pin to ground to set the power-on
reset delay.
DS8007
Multiprotocol Dual Smart Card Interface
Detailed DescriptionThe following describes the major functional features of
the device. Use of this document requires the reader
have a basic understanding of ISO 7816 terminology.
Parallel Bus InterfaceThe device interfaces to a host computer/processor
through a multiplexed or demultiplexed, parallel, 8-bit
data bus (D0–D7). The parallel bus interface monitors
the ALE signal and automatically detects whether a
multiplexed or nonmultiplexed external bus interface is
intended. The nonmultiplexed external bus interface is
the default configuration and is maintained so long as
no edge (activity) is detected on the ALE pin. Once a
rising edge is detected on the ALE pin, the DS8007 is
placed into the multiplexed mode of operation. Once in
the multiplexed mode of operation, a reset/power cycle
or the deassertion of CSforces the device to the non-
multiplexed mode. Connecting the ALE pin to VDDor
ground forces the device into nonmultiplexed parallel
bus mode. Figure 7 shows that the bus recognition dic-
tates whether the external address lines (AD3–AD0)
can be used directly or whether the external data lines
(D7–D0) must be latched according to the ALE input
signal. In the multiplexed mode of operation, a new
address is latched irrespective of the state of CS.
ANALOG
INTERFACE
POWER-SUPPLY
SUPERVISOR
CONTROL
SEQUENCERS
ISO
UART
DIGITAL
INTERFACE
CLOCK
GENERATION
TIMEOUT
COUNTER
GNDB
I/OB
C4B
C8B
PRESB
RSTB
INT
INTAUX
I/OAUX
AD0
AD1
AD2
AD3
ALE
CLKB
VCCB
GNDA
I/OA
C4A
C8A
PRESA
RSTA
CLKA
VCCA
RSTOUT
DELAY
VDD
GND
VDDA
AGND
VUP
DC-DC
CONVERTER
CPA1
CPA2
CPB1
CPB2
XTAL1
XTAL2
DS8007
Figure 6. Block Diagram
Multiplexed ModeIn the multiplexed mode of operation, the D7–D0 sig-
nals are multiplexed between address and data. The
falling edge of the address latch enable (ALE) signal
from the host microcontroller latches the address
(D3–D0), and the RDand WRstrobe input signals are
used to enable a read or write operation, respectively, if
the DS8007 is selected (i.e., CS= 0). See the AC timing
for the multiplexed parallel bus mode found earlier in
this data sheet.
Nomultiplexed ModeIn the nonmultiplexed mode of operation, the address is
always provided on the AD3–AD0 signals, and the data
is always transacted on the D7–D0 signals. The RDinput
signal is used as a read/write (R/W) operation select. Theand CSinput signals serve as active-low enables,
and must be asserted for the read or write operation to
take place. See the AC timing for the nonmultiplexed
parallel bus mode found earlier in this data sheet.
DS8007
Multiprotocol Dual Smart Card InterfaceREGISTERSAD3–AD0
D3–D0
D7–D0
LATCH
ALE
RST
CONTROLLOGIC
VDD
RST
Figure 7. Parallel Bus Interface
DS8007*u = unchanged, x = always reflects state of external device pin, even when RIU= 0.
Note:Writes to unimplemented bits have no effect. Reads of unimplemented bits return 0.
Table 1. Special Function Register Map
ADDRESS
(HEX)
REGISTER
NAME R/W BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0 RESET RIU = 0*
00 CSR R/W CSR7 CSR6 CSR5 CSR4 RIU SC3 SC2 SC1 0011 0000 0011 0uuu
01 CCR R/W — — SHL CST SC AC2 AC1 AC0 0000 0000 00uu uuuu
02 PDR R/W PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 0000 0000 uuuu uuuu
03 UCR2 R/W — DISTBE/
RBF DISAUX PDWN SAN AUTOC CKU PSC 0000 0000 uuuu uuuu
05 GTR R/W GTR.7 GTR.6 GTR.5 GTR.4 GTR.3 GTR.2 GTR.1 GTR.0 0000 0000 uuuu uuuu
06 UCR1 R/W FTE0 FIP — PROT T/R LCT SS CONV 0000 0000 0uuu 00uu
07 PCR R/W — — C8 C4 1V8 RSTIN 3V/5V START 0011 0000 0011 uuuu
08 TOC R/W TOC7 TOC6 TOC5 TOC4 TOC3 TOC2 TOC1 TOC0 0000 0000 0000 0000
09 TOR1 W TOL7 TOL6 TOL5 TOL4 TOL3 TOL2 TOL1 TOL0 0000 0000 uuuu uuuu
0A TOR2 W TOL15 TOL14 TOL13 TOL12 TOL11 TOL10 TOL9 TOL8 0000 0000 uuuu uuuu
0B TOR3 W TOL23 TOL22 TOL21 TOL20 TOL19 TOL18 TOL17 TOL16 0000 0000 uuuu uuuu
0C MSR R CLKSW FE BGT CRED PRB PRA INTAUX TBE/
RBF 0101 0000 u1u1 uuu0
0C FCR W — PEC2 PEC1 PEC0 FTE1 FL2 FL1 FL0 0000 0000 0uuu 0uuu
0D URR R UR7 UR6 UR5 UR4 UR3 UR2 UR1 UR0 0000 0000 0000 0000
0D UTR W UT7 UT6 UT5 UT4 UT3 UT2 UT1 UT0 0000 0000 0000 0000
0E USR R TO3 TO2 TO1 EA PE OVR FER TBE/
RBF 0000 0000 0000 0000
0F HSR R — PRTLB PRTLA SUPL PRLB PRLA INTAUXL PTL 0001 0000 0uuu xxxu
Multiprotocol Dual Smart Card Interface
Control RegistersSpecial control registers that the host computer/micro-
controller accesses through the parallel bus manage
most DS8007 features. Many of the registers, although
only mentioned once in the listing, are duplicated for
each card interface. The PDR, GTR, UCR1, UCR2, and
CCR registers exist separately for each of the three
card interfaces. The PCR register is provided only for
card interface A and card interface B.
The specific register to be accessed is controlled by
the current setting of the SC3–SC1 bits in the Card
Select Register. For example, there are three instances
of the UART Control Register 1 (UCR1) at address 06h.
If the SC3–SC1 bits are configured so that card A is
selected, then all reads and writes to address 06h only
affect card A. If SC3–SC1 are changed to select card
B, then all reads and writes to address 06h only affect
card B, etc.
In addition, some registers have different functions
based on whether the register is being read from or writ-
ten to. An example of this are the UART Receive
(URR)/UART Transmit (UTR) registers located at address
0Dh. Although they share the same address, during read
operations the receive register is read, and write opera-
tions go to a separate transmit register. This selection
requires no extra configuration by the software.
DS8007
Multiprotocol Dual Smart Card Interface
Card Select Register (CSR)R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00110uuub on RIU= 0.543210
Address 00hCSR7CSR6CSR5CSR4RIUSC3SC2SC1
R-0R-0R-1R-1RW-0RW-0RW-0RW-0
Clock Configuration Register (CCR)R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00uuuuuub on RIU= 0.
Address 01h——SHLCSTSCAC2AC1AC0
R-0R-0RW-0RW-0RW-0RW-0RW-0RW-0
Bits 7 to 4: Identification Bits (CSR7 to CSR4). Thesebits provide a method for software to identify the device
as follows:
0011 = DS8007 revision Ax
Bit 3:Reset ISO UART (RIU). When this bit is cleared(0), most of the ISO UART registers are reset to their
initial values. This bit must be cleared for at least 10ns
prior to initiating an activation sequence. This bit must
be set (1) by software before any action on the UART
can take place.
Bits 2 to 0: Select Card Bits (SC3 to SC1).These bits
determine which IC card interface is active as shown
below. Only one bit should be active at any time, and
no card is selected after reset (i.e., SC3–SC1 = 000b).
Other combinations are invalid.
000 = No card is selected.
001 = Card A is selected.
010 = Card B is selected.
100 = AUX card interface is selected.
Bits 7 and 6: Reserved.
Bit 5: Stop High or Low (SHL).This bit determines if
the card clock stops in the low or high state when the
CST bit is active. It forces the clock to stop in a low
state when SHL = 0 or in a high state when SHL = 1.
Bit 4: Clock Stop (CST).For an asynchronous card,
this bit allows the clock to the selected card to be
stopped. When this bit is set (1), the card clock is
stopped in the state determined by the SHL bit. When
this bit is cleared (0), the card clock operation is
defined by CCR bits AC2–AC0.
Bit 3: Synchronous Clock (SC).For a synchronous
card, the card clock is controlled by software manipu-
lation of this SC, and the contact CLKx is the copy of
the value in this bit. In synchronous transmit mode, a
write to the UTR results in the least significant bit (LSb)
of the data written to the UTR being driven out on the
I/Ox pin. In synchronous receive mode, the state of the
I/Ox pin can be read from the LSb of the URR.
Bits 2 to 0: Alternating Clock Select (AC2 to AC0).These bits select the frequency of the clock provided to
the active card interface and to the UART for the ele-
mentary time unit (ETU) generation as shown below. All
frequency changes are synchronous so that there are
no spikes or unwanted pulse widths during transitions.
fINTis the frequency of the internal oscillator.
AC2–AC0
000 = fXTAL
001 = fXTAL/ 2
010 = fXTAL/ 4
011 = fXTAL/ 8
1xx = fINT/ 2
DS8007
Bits 7 to 0:Programmable ETU Divider Register Bits
7 to 0 (PD7 to PD0). These bits, in conjunction with thedefined UART input clock (based upon CKU,
AC2–AC0) and the prescaler selection (PSC bit), are
used to define the ETU for the UART when interfaced to
the associated card interface. The output of the
prescaler block is further divided according to the
PD7–PD0 bits as follows:ETU = Prescaler output / (PD7–PD0), when
PD7–PD0 = 02h–FFhETU = Prescaler output / 1, when PD7–PD0=00h–01hPrescaler output / 256 is not supported
Programmable Divider Register (PDR)R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU= 0.
Address 02hPD7PD6PD5PD4PD3PD2PD1PD0
RW-0RW-0RW-0RW-0RW-0RW-0RW-0RW-0
UART Control Register 2 (UCR2)R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU= 0.543210
Address 03h—DISTBE/RBFDISAUXPDWNSANAUTOCCKUPSC
R-0RW-0RW-0RW-0RW-0RW-0RW-0RW-0
Bit 7: Reserved.
Bit 6: Disable TBE/RBF Interrupt(DISTBE/RBF). Thisbit controls whether the TBE/RBF flag can generate an
interrupt on the INTpin. When this bit is cleared to 0,
an interrupt is signaled on the INTpin in response to
the TBE/RBF flag getting set. When DISTBE/RBF is set
to 1, interrupts are not generated in response to the
TBE/RBF flag. Disabling the TBE/RBF interrupt can
allow faster communication speed with the card, but
requires that a copy of TBE/RBF in register MSR be
polled to not lose priority interrupts that can occur in
register USR.
Bit 5: Disable Auxiliary Interrupt (DISAUX). This bitcontrols whether the external INTAUX pin can generate
an interrupt on the INToutput pin. When this bit is
cleared to 0, a change on the INTAUX input pin results
in assertion of the INToutput pin. When DISAUX is set
to 1, a change on INTAUX does not result in assertion
of the INToutput pin. The INTAUXL bit is set by a
change on the INTAUX pin independent of the DISAUX
bit state. Since the INTAUX bit is set independent of the
DISAUX bit, it is advisable to read HSR (thus clearing
INTAUX) prior to clearing DISAUX to avoid an interrupt
on the INTpin. To avoid an interrupt when selecting a
different card, the DISAUX bit should be set to 1 in all
UCR2 registers.
Multiprotocol Dual Smart Card Interface
DS8007
Multiprotocol Dual Smart Card Interface
Bit 4: Power-Down Mode Enable (PDWN).This bit
controls entry into the power-down mode. Power-down
mode can only be entered if the SUPL bit has been
cleared. When PDWN is set to 1, the XTAL1 and XTAL2
crystal oscillator is stopped, and basic functions such
as the sequencers are supported by the internal ring
oscillator. The UART is put in a suspended state, and
the clocks to the UART, the ETU unit, and the timeout
counter are gated off. During the power-down mode, it
is not possible to select a card other than the one cur-
rently selected (advisory to the programmer, selecting
another card during power-down mode is not recom-
mended). There are five ways of exiting the power-
down mode:Insertion of card A or card B (detected by PRLA or
PRLB).Withdrawal of card A or card B (detected by PRLA
or PRLB).Reassertion of the CSpin to select the DS8007 (CS
must be deasserted after setting PDWN = 1 for this
event to exit from power-down).INTAUXL bit is set due to change in INTAUX
(INTAUXL bit must be cleared first).Clearing of PDWN bit by software (if CSpin is
always tied to 0).
Except in the case of a read operation of register HSR,
the INTpin remains asserted in the active-low state.
The host device can read the status registers after the
oscillator warmup time, and the INTsignal returns to
the high state.
Bit 3:Synchronous/Asynchronous Card Select
(SAN). This bit selects whether a synchronous or asyn-chronous card interface is enabled. When this bit is
cleared to 0, an asynchronous card interface is expect-
ed. When this bit is set to 1, a synchronous interface is
expected. In synchronous mode, the UART is
bypassed; the SC bit controls the CLK, and I/O is trans-
acted in the LSb of UTR/URR. Card interface AUX can-
not operate in the true synchronous mode since it does
not have a CLK signal to accompany I/OAUX. However,
the SAN bit invokes the same control of I/OAUX through
UTR/URR as is given for card interfaces A and B.
Bit 2:Auto Convention Disable (AUTOC). This active-low bit controls whether the decoding convention
should automatically be detected during the first
received character in answer-to-reset (ATR). If AUTOC
= 0, the character decoding convention is automatically
detected (while SS = 1) and the UCR1.CONV bit is writ-
ten accordingly by hardware. If AUTOC= 1, the
UCR1.CONV bit must be set by software to assign the
character decoding convention. The AUTOCbit must
not be changed during a card session.
Bit 1:Clock UART Doubler Enable (CKU). This bitenables the effective ETU defined for the UART to last
half the number of clock cycles defined by the
AC2–AC0 and PD7–PD0 configuration (except in the
case when AC2–AC0 = 000b, where fCLK= fXTAL).
When CKU is cleared to 0, the AC2–AC0 defined fCLK
is used for ETU timing generation. When CKU is set to
1, a clock frequency of 2 x fCLKis used for ETU gener-
ation.
Bit 0:Prescaler Select (PSC). When PSC = 0, theprescaler value is 31. When PSC = 1, the prescaler
value is 32.
Guard Time Register (GTR)R = unrestricted read, W = unrestricted write, -n = value after reset; all bits unaffected by RIU= 0.543210
Address 05hGTR.7GTR.6GTR.5GTR.4GTR.3GTR.2GTR.1GTR.0
RW-0RW-0RW-0RW-0RW-0RW-0RW-0RW-0
Bits 7 to 0:Guard Time Register Bits 7 to 0 (GTR.7
to GTR.0). These bits are used for storing the numberof guard time units (ETU) requested during ATR. When
transmitting, the DS8007 UART delays these numbers
of extra guard time ETU before transmitting a character
written to UTR.
DS8007
Multiprotocol Dual Smart Card Interface
UART Control Register 1 (UCR1)R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0uuu00uub on RIU= 0.543210
Address 06hFTE0FIP—PROTT/RLCTSSCONV
R-0RW-0R-0RW-0RW-0RW-0RW-0RW-0
Bit 7:FIFO Threshold Enable 0 (FTE0).When this bit
and the FTE1 (FCR.3) bit are set, the programmable
FIFO threshold feature is enabled. This bit always
reads 0 for compatibility.
Bit 6:Force Inverse Parity (FIP).When this bit is con-
figured to 0, the correct parity is transmitted with each
character, and receive characters are checked for the
correct parity. When FIP = 1, an inverse parity bit is
transmitted with each character and correctly received
characters are NAK’d.
Bit 5:Reserved.This bit must be left 0. Setting this bit
to 1 causes improper device operation.
Bit 4:Protocol Select (PROT).This bit is set to 1 by
software to select the asynchronous T = 1 protocol and
is cleared to 0 to select the T = 0 protocol.
Bit 3:Transmit/Receive (T/R).This bit should be set
by software to operate the UART in transmit mode.
When this bit is changed from 0 to 1 (UART changed
from receive to transmit mode), hardware sets the
USR.RBF/TBE bit, indicating an empty transmit buffer.
The T/R bit is automatically cleared to 0 following suc-
cessful transmission if UCR1.LCT is configured to 1
prior to the transmission. This bit cannot be written to
when RIU= 0 (holding in reset).
Bit 2: Last Character to Transmit (LCT).This bit is
optionally set by software prior to writing the last char-
acter to be transmitted to the UART transmit register
(UTR). If LCT is set to 1 prior to writing to UTR, hard-
ware resets the LCT, T/R, and TBE/RBF bits following a
successful transmission. Setting this bit to 1 allows
automatic change to the reception mode after the last
character is sent. This bit can be set during and before
the transmission. This bit cannot be written to when RIU
= 0 (holding in reset).
Bit 1:Software Convention Setting (SS).This bit
should be set by software prior to ATR to allow automat-
ic convention detection. Hardware automatically resets
the SS bit at 10.5 ETU after the detection of the start bit
of the first character of the ATR.
Bit 0:Convention (CONV).This bit defines the charac-
ter decoding convention of the ISO UART. If CONV = 1,
the convention is direct. If CONV = 0, the convention is
inverted. If automatic convention detection is enabled
(AUTOC= 0), hardware detects the character conven-
tion and configures the CONV bit appropriately at 10.5
ETU. Otherwise (AUTOC= 1), software must configure
the CONV bit.
DS8007
Multiprotocol Dual Smart Card Interface
Bits 7 to 0:Timeout Counter Configuration Register
Bits (TOC7 to TOC0).These register bits determine
the counting configuration for the three timeout counter
registers. The available configurations are detailed in
the Timeout Counter Operationsection. These registers
can be written when RIU= 1 before activation and can-
not be written to when RIU= 0.
Bits 7 and 6: Reserved.
Bit 5:Contact 8 (C8).Writes to this register bit are out-
put on the C8 pin of the card interface. Reads of this
register bit reflect the value on the C8 pin.
Bit 4:Contact 4 (C4).Writes to this register bit are out-
put on the C4 pin of the card interface. Reads of this
register bit reflect the value on the C4 pin.
Bit 3:1.8V Card Select (1V8).If this bit is set to 1, the
VCCxsupplied to the card interface is 1.8V. This bit
overrides the 3V/5V bit.
Bit 2:Reset Bit (RSTIN).When a card interface is acti-
vated, the RSTx pin is driven according to the value
contained in this register bit.
Bit 1:3V/5V Card Select (3V/5V).This bit determines
the VCCxlevel for the card interface. When this bit is set
to 1, VCCxis defined as 3V. When this bit is cleared to
0, VCCxis defined as 5V. When the 1V8 and 3V/5V bits
are set to 1, priority is given to 1V8.
Bit 0: Start (START).This bit controls software activa-
tion/deactivation of the card interface. When this bit is
written to 1, the activation sequence for the selected
card is performed. When this bit is written to 0, the
deactivation sequence for the selected card is per-
formed. Hardware automatically resets the START bit
for the associated card interface when emergency
deactivation occurs. This bit can be written regardless
of the state of the RIUbit.
Power Control Register (PCR)R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 0011uuuub on RIU= 0.
Note:The AUX card interface does not have register PCR. C4 and C8 are external ports that are internally pulled up (10kΩto VCCx),
writing a 1 to C4, C8 configures the weak pullup. Reads are made of the pin state to a different physical bit. Writing a 0 to C4, C8
configures the pulldown. C4 and C8 bits can be written irrespective of the state of the T/R bit.
Address 07h——C8C41V8RSTIN3V/5VSTART
R-0R-0RW-1RW-1RW-0RW-0RW-0RW-0
Timeout Configuration Register (TOC)R = unrestricted read, W = unrestricted write, -n = value after reset. This register is reset to 00000000b on RIU= 0.6543210
Address 08hTOC7TOC6TOC5TOC4TOC3TOC2TOC1TOC0
RW-0RW-0RW-0RW-0RW-0RW-0RW-0RW-0
DS8007
Bits 7 to 0:Timeout Counter Register 2 Bits (TOL15
to TOL8).This register can be configured to operate as
the lower 8 bits of a 16-bit counter or as the middle 8
bits of a 24-bit counter. See the Timeout Counter
Operation section for details on configurable modes.
Timeout Counter Register 2 (TOR2)R = unrestricted read, W = unrestricted write, -n = value after reset. This register is unchanged on RIU= 0.543210
Address 0AhTOL15TOL14TOL13TOL12TOL11TOL10TOL9TOL8
W-0W-0W-0W-0W-0W-0W-0W-0
Timeout Counter Register 3 (TOR3)R = unrestricted read, W = unrestricted write, -n = value after reset. This register is unchanged on RIU= 0.543210
Address 0BhTOL23TOL22TOL21TOL20TOL19TOL18TOL17TOL16
W-0W-0W-0W-0W-0W-0W-0W-0
Bits 7 to 0:Timeout Counter Register 3 Bits (TOL23
to TOL16).This register can be configured to operate
as the high 8 bits of a 16-bit counter or as the high 8
bits of a 24-bit counter. See the Timeout Counter
Operationsection for details on configurable modes.
Timeout Counter Register 1 (TOR1)R = unrestricted read, W = unrestricted write, -n = value after reset. This register is unchanged on RIU= 0.
Address 09hTOL7TOL6TOL5TOL4TOL3TOL2TOL1TOL0
W-0W-0W-0W-0W-0W-0W-0W-0
Bits 7 to 0:Timeout Counter Register 1 Bits (TOL7 to
TOL0).This register can be configured to operate as an
8-bit counter or as the lowest 8 bits of a 24-bit counter.
TOR1, TOR2, and TOR3 are concatenated to form a 24-
bit ETU counter or a pair of independent 16- and 8-bit
counters. These counters are only used when a card is
supplied an active clock. See the Timeout Counter
Operationsection for details on configurable modes.
Multiprotocol Dual Smart Card Interface
