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DS5250F-125+-DS5250F-1N5+-DS5250F-825+
High-Speed Secure Microcontroller
General DescriptionThe DS5250 is a highly secure, four clocks-per-
machine cycle, 100% 8051-instruction-set-compatible
microprocessor in Maxim’s secure microcontroller fami-
ly.It was designed to be the cryptographic engine of
PIN pads, financial terminals, and any other application
in which data security is paramount. A key feature of
the device is that it encrypts its program memory and
optionally its data memory with a hardware-based sin-
gle- or triple-DES (data encryption standard) algorithm,
making it almost impossible to extract information. It
also implements block cipher encoding that uses block
addresses to modify the encrypted data, further
strengthening security. This makes the device ideal for
storage and transmission of passwords, personal iden-
tification numbers, encryption keys, and other highly
confidential information.
ApplicationsPIN Pads
Financial Terminals
Data Security Applications
FeaturesFeature-Rich, 8051-Compatible MicroprocessorAccesses Up to 4MB Program and 4MB Data
Memory (All Nonvolatile)
In-System Programmable Through Serial Port
In-Application Programmable Through User Software
Allows Self-Modification of Program/Data Memory
Four 8-Bit Ports/One 6-Bit Port
Three 16-Bit Timer/Counters
256 Bytes of Scratchpad RAM
Advanced FeaturesCRC-16/32 Generator
5KB Internal SRAM (Optional 1KB Stack)
Single or 3DES Engine
Partitionable Memory Segments Variable from 4KB to
256KB
High-Speed ArchitectureFour Clocks-per-Machine Cycle
DC-to-25MHz Operation
Single-Cycle Instruction in 160ns
Dual Data Pointers Can Increment or Decrement
Independently
Automatic Data Pointer (DPTR) Selection Available
Programmable Speed MOVX Instructions
1KB On-Chip Instruction Cache
High-Reliability OperationPower-Fail/Overvoltage Reset
Early-Warning Power-Fail Interrupt
Watchdog Timer
Nonvolatile FunctionsOn-Chip Real-Time Clock with Alarm Interrupt
2KB Battery-Backed Internal SRAM
Interrupts15 Interrupts with Seven External Sources
Security FeaturesExecutes Single/3DES-Encrypted Programs to
Prevent Observation
Two Self-Destruct Inputs
4096-Bit Modulo-Arithmetic Accelerator (MAA) for
Public/Private Key Operations
Tamper Sensors Detect Thermal/Voltage/Probe Attacks
Programmable Attack Countermeasures
Secure-Loader Mode
True Random-Number Generator (RNG)
Unique ID Number in Every Device
Separate Program/Data Cryptograph
Program Memory Integrity Checking
Evaluation Kit Available (DS5250-KIT)
DS5250
High-Speed Secure Microcontroller
Ordering InformationRev 4; 11/08
Note:Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be
ABRIDGED DATASHEET
EVALUATION KIT
AVAILABLE
PARTTEMP RANGEPIN-PACKAGE DS5250F-825 0°C to +70°C 80 MQFP
DS5250F-825+ 0°C to +70°C 80 MQFP
DS5250F-8N5 -40°C to +85°C 80 MQFP
DS5250F-8N5+ -40°C to +85°C 80 MQFP
DS5250F-125 0°C to +70°C 100 MQFP
DS5250F-125+ 0°C to +70°C 100 MQFP
DS5250F-1N5 -40°C to +85°C 100 MQFP
DS5250F-1N5+ -40°C to +85°C 100 MQFP
Pin Configurations and Selector Guide appear at end of
data sheet.+Denotes a lead-free/RoHS-compliant package.
DS5250
High-Speed Secure Microcontroller
ABRIDGED DATASHEETREAL-TIME
CLOCK
SERIAL
PORTS
0, 1
STACK
POINTER
PC AND
DPTRs
TIMERS
0, 1, 2
MODULO-
ARITHMETIC
ACCEL.
USER
DES
ENGINE
INTERRUPT
LOGIC
CRC
GENERATOR
INSTRUCTION
DECODER
AND
CONTROLS
CPUINTERNAL
REGISTERS
RANDOM-
NUMBER
GENERATOR
WATCHDOG
AND POWER
CONTROL
ROM
LOADER
INTERNAL CONTROL/DATA BUS
INTERNAL
SRAMINSTRUCTION
CACHE
1KB x 8
3KB x 8
1KB x 8
PROGRAM
MEMORY
CRYPTOGRAPH
BYTE-WIDE BUS INTERFACE
DATA
MEMORY
CRYPTOGRAPH
RESETCLOCKS
POWER AND
TEMPERATURE
MONITOR
XTAL1XTAL2
CC0
GND
BAT
RTCX1
RTCX2
GND2
RST
SDI2SDI1
VRST
INTERNAL ADDRESS BUS
I/O PORTS88821
PE3, PE4, AND CExNP2P3P4
MMU
MSEL
ALE
PPH
BDx
BAxCEx
PROG
PE1, PE2
R/WFOE
FWP
DS5250
Figure 4. Block Diagram
Note to readers: This document is an abridged version of the full data sheet. To request the full data sheet, go to
/DS5250and click on Request Full Data Sheet.
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Datasheets for electronic components.