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DS5003FPM-16+
Secure Microprocessor Chip
General DescriptionThe DS5003 secure microprocessor incorporates
sophisticated security features including an array of
mechanisms that are designed to resist all levels of
threat, including observation, analysis, and physical
attack. As a result, a massive effort is required to obtain
any information about its memory contents.
Furthermore, the “soft” nature of the DS5003 allows fre-
quent modification of the secure information, thereby
minimizing the value of any secure information obtained
by such a massive effort. The device is an enhanced
version of the DS5002FP secure microprocessor chip
with additional scratchpad RAM.
Differences from the DS5002FPThe DS5003 implements only one additional feature
from the DS5002FP: it adds 128 bytes of internal
scratchpad memory (for a total of 256 bytes) similar to
that used in 8032/8052 architectures. This additional
memory is accessible through indirect addressing 8051
instructions such as “mov a, @r1,” where r1 now can
have a value between 0 and 255. It is also usable as
stack space for pushes, pops, calls, and returns.
Register indirect addressing is used to access the
scratchpad RAM locations above 7Fh. It can also be
used to reach the lower RAM (0h–7Fh) if needed. The
address is supplied by the contents of the working reg-
ister specified in the instruction. Thus, one instruction
can be used to reach many values by altering the con-
tents of the designated working register. Note that only
R0 and R1 can be used as pointers. An example of reg-
ister indirect addressing is as follows:
ANL A, @R0;Logical AND the Accumulator with
the contents of
;the register pointed to by the
value stored in R0
ApplicationsPIN Pads
Gaming Machines
Any Application Requiring Software Protection
Features8051-Compatible Microprocessor for
Secure/Sensitive Applications
Access 32kB, 64kB, or 128kB of Nonvolatile
SRAM for Program and/or Data Storage
128 Bytes of RAM
128 Bytes of Indirect Scratchpad RAM
In-System Programming Through On-Chip
Serial Port
Can Modify Its Own Program or Data Memory in
the End SystemFirmware Security Features
Memory Stored in Encrypted Form
Encryption Using On-Chip 64-Bit Key
Automatic True Random-Key Generator
Self-Destruct Input (SDI)
Top Coating Prevents Microprobing
Protects Memory Contents from PiracyCrash-Proof Operation
Maintains All Nonvolatile Resources for Over
10 Years (at Room Temperature) in the
Absence of Power
Power-Fail Reset
Early Warning Power-Fail Interrupt
Watchdog Timer
DS5003
Secure Microprocessor ChipRev 0; 3/08
Pin Configuration appears at end of data sheet.
Ordering Information+Denotes a lead(Pb)-free/RoHS-compliant package.
PART TEMP
RANGE
INTERNAL
MICRO
PROBE
SHIELD
PIN-
PACKAGE DS5003FPM-16+ 0°C to +70°C Yes 80 MQFP
DS5003
Secure Microprocessor Chip
ABSOLUTE MAXIMUM RATINGS
DC CHARACTERISTICS(VCC= 5V ±10%, TA= 0°C to +70°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on Any Pin
Relative to Ground..................................-0.3V to (VCC+ 0.5V)
Voltage Range on VCCRelative
to Ground..........................................................-0.3V to +6.0V
Operating Temperature Range.............................40°C to +85°C
Storage Temperature*.......................................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Operating Voltage VCC (Note 1) VCCMIN 5.5 V
Minimum Operating Voltage VCCMIN 0°C to +70°C (Note 1) 4.00 4.12 4.25 V
Power-Fail Warning Voltage VPFW 0°C to +70°C (Note 1) 4.25 4.37 4.50 V
Lithium Supply Voltage VLI (Note 1) 2.5 4.0 V
Operating Current at 16MHz ICC (Note 2) 36 mA
Idle-Mode Current at 12MHz IIDLE 0°C to +70°C (Note 3) 7.0 mA
Stop-Mode Current ISTOP (Note 4) 80 μA
Pin Capacitance CIN (Note 5) 10 pF
Output Supply Voltage (VCCO) VCCO1 (Notes 1, 2) VCC -
0.45 V
Output Supply Battery-Backed
Mode (VCCO,CE1–CE4,PE1,
PE2)
VCCO2 0°C to +70°C (Notes 1, 6) VLI -
0.65 V
Output Supply Current (Note 7) ICCO1 VCCO = VCC - 0.45V 75 mA
Lithium-Backed Quiescent
Current (Note 8) ILI 0°C to +70°C 5 75 nA
BAT = 3.0V (0°C to +70°C) (Note 1) 4.00 4.25 Reset Trip Point in Stop Mode
BAT = 3.3V (0°C to +70°C) (Note 1) 4.40 4.65
Input Low Voltage VIL (Note 1) -0.3 +0.8 V
Input High Voltage VIH1 (Note 1) 2.0 VCC +
0.3 V
Input High Voltage
(RST, XTAL1, PROG)VIH2 (Note 1) 3.5 VCC +
0.3 V
Output Low Voltage at
IOL = 1.6mA (Ports 1, 2, 3, PF)VOL1 (Notes 1, 9) 0.15 0.45 V
*Storage temperature is defined as the temperature of the device when VCC= 0V and VLI = 0V. In this state, the contents of SRAM
are not battery backed and are undefined.
Note:The DS5003 adheres to all AC and DC electrical specifications published for the DS5002FP.
DS5003
Secure Microprocessor Chip
AC CHARACTERISTICS—SDI PIN(VCC= 0V to 5V, TA= 0°C to +70°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS 4.5V < VCC < 5.5V 1.3 SDI Pulse Reject (Note 11) tSPRVCC = 0V, VBAT = 2.9V 4 μs
4.5V < VCC < 5.5V 10 SDI Pulse Accept (Note 11) tSPAVCC = 0V, VBAT = 2.9V 50 μs
DC CHARACTERISTICS (continued)(VCC= 5V ±10%, TA= 0°C to +70°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Output Low Voltage at
IOL = 3.2mA (P0.0–P0.7, ALE,
BA0–BA14, BD0–BD7, R/W,
CE1N,CE1–CE4,PE1–PE4,
VRST)
VOL2 (Note 1) 0.15 0.45 V
Output High Voltage at
IOH = -80μA (Ports 1, 2, 3) VOH1 (Note 1) 2.4 4.8 V
Output High Voltage at
IOH = -400μA (P0.0–P0.7, ALE,
BA0–BA14, BD0–BD7, R/W,
CE1N,CE1–CE4,PE1–PE4,
VRST)
VOH2 (Note 1) 2.4 4.8 V
Input Low Current,
VIN = 0.45V (Ports 1, 2, 3) IIL -50 μA
Transition Current 1 to 0,
VIN = 2.0V (Ports 1, 2, 3) ITL -500 μA
SDI Input Low Voltage VILS (Note 1) 0.4 V
SDI Input High Voltage VIHS (Notes 1, 10) 2.0 VCCO V
SDI Pulldown Resistor RSDI 25 60 k
Input Leakage
(P0.0–P0.7, MSEL) IIL 0.45 < VIN < VCC +10 μA
RST Pulldown Resistor RRE 0°C to +70°C 40 150 k
VRST Pullup Resistor RVR 4.7 k
PROG Pullup Resistor RPR 40 k
DS5003
Secure Microprocessor Chip
AC CHARACTERISTICS—EXPANDED BUS-MODE TIMING SPECIFICATIONS(VCC= 5V ±10%, TA= 0°C to +70°C.) (Figures 1, 2)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS Oscillator Frequency 1/tCLK 1.0 16.0 MHz
ALE Pulse Width tALPW 2tCLK - 40 ns
Address Valid to ALE Low tAVALL tCLK - 40 ns
Address Hold After ALE Low tAVAAV tCLK - 35 ns
RD Pulse Width tRDPW 6tCLK - 100 ns
WR Pulse Width tWRPW 6tCLK - 100 ns
12MHz 5tCLK - 165 RD Low to Valid Data In tRDLDV16MHz 5tCLK - 105 ns
Data Hold After RD High tRDHDV 0 ns
Data Float After RD High tRDHDZ 2tCLK - 70 ns
12MHz 8tCLK - 150 ALE Low to Valid Data In tALLVD
16MHz 8tCLK - 90
ns
12MHz 9tCLK - 165 Valid Address to Valid Data In tAVDV16MHz 9tCLK - 105 ns
ALE Low to RD or WR Low tALLRDL 3tCLK - 50 3tCLK + 50 ns
Address Valid to RD or WR Low tAVRDL 4tCLK - 130 ns
Data Valid to WR Going Low tDVWRL tCLK - 60 ns
12MHz 7tCLK - 150 Data Valid to WR High tDVWRH16MHz 7tCLK - 90 ns
Data Valid After WR High tWRHDV tCLK - 50 ns
RD Low to Address Float tRDLAZ 0 ns
RD or WR High to ALE High tRDHALH tCLK - 40 tCLK + 50 ns
AC CHARACTERISTICS—EXTERNAL CLOCK DRIVE(VCC= 5V ±10%, TA= 0°C to +70°C.) (Figure 3)
PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 12MHz 20 External Clock High Time tCLKHPW16MHz 15 ns
12MHz 20 External Clock Low Time tCLKLPW16MHz 15 ns
12MHz 20 External Clock Rise Time tCLKR16MHz 15 ns
12MHz 20 External Clock Fall Time tCLKF16MHz 15 ns
DS5003
Secure Microprocessor Chip
AC CHARACTERISTICS—POWER-CYCLE TIME(VCC= 5V ±10%, TA= 0°C to +70°C.) (Figure 4)
PARAMETER SYMBOL MIN MAX UNITS Slew Rate from VCCMIN to VLI tF 130 μs
Crystal Startup Time tCSU (Note 12)
Power-On Reset Delay tPOR 21,504 tCLK
AC CHARACTERISTICS—SERIAL PORT TIMING (MODE 0)(VCC= 5V ±10%, TA= 0°C to +70°C.) (Figure 5)
PARAMETER SYMBOL MIN MAX UNITS Serial Port Clock Cycle Time tSPCLK 12tCLK μs
Output Data Setup to Rising Clock Edge tDOCH 10tCLK - 133 ns
Output Data Hold After Rising Clock Edge tCHDO 2tCLK - 117 ns
Clock Rising Edge to Input Data Valid tCHDV 10tCLK - 133 ns
Input Data Hold After Rising Clock Edge tCHDIV 0 ns
AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING(VCC= 5V ±10%, TA= 0°C to +70°C.) (Figure 6)
PARAMETER SYMBOL MIN MAX UNITS Delay to Byte-Wide Address Valid from CE1,CE2,
or CE1N Low During Op Code Fetch tCE1LPA 30 ns
Pulse Width of CE1–CE4,PE1–PE4, or CE1N tCEPW 4tCLK - 35 ns
Byte-Wide Address Hold After CE1,CE2, or CE1N
High During Op Code Fetch tCE1HPA 2tCLK - 20 ns
Byte-Wide Data Setup to CE1,CE2, or CE1N High
During Op Code Fetch tOVCE1H 1tCLK + 40 ns
Byte-Wide Data Hold After CE1,CE2, or CE1N High
During Op Code Fetch tCE1HOV 0 ns
Byte-Wide Address Hold After CE1–CE4,PE1–PE4,
or CE1N High During MOVX tCEHDA 4tCLK - 30 ns
Delay from Byte-Wide Address Valid CE1–CE4,
PE1–PE4, or CE1N Low During MOVX tCELDA 4tCLK - 35 ns
Byte-Wide Data Setup to CE1–CE4,PE1–PE4, or
CE1N High During MOVX (Read) tDACEH 1tCLK + 40 ns
Byte-Wide Data Hold After CE1–CE4,PE1–PE4, or
CE1N High During MOVX (Read) tCEHDV 0 ns
Byte-Wide Address Valid to R/W Active During
MOVX (Write) tAVRWL 3tCLK - 35 ns
DS5003
Secure Microprocessor Chip
AC CHARACTERISTICS—BYTE-WIDE ADDRESS/DATA BUS TIMING (continued)(VCC= 5V ±10%, TA= 0°C to +70°C.) (Figure 6)
PARAMETER SYMBOL MIN MAX UNITS Delay from R/W Low to Valid Data Out During
MOVX (Write) tRWLDV 20 ns
Valid Data Out Hold Time from CE1–CE4,PE1–PE4,
or CE1N High tCEHDV 1tCLK - 15 ns
Valid Data Out Hold Time from R/W High tRWHDV 0 ns
Write Pulse Width (R/W Low Time) tRWLPW 6tCLK - 20 ns
RPC AC CHARACTERISTICS—DBB READ(VCC= 5V ±10%, TA= 0°C to +70°C.) (Figure 7)
PARAMETER SYMBOL MIN MAX UNITS CS, A0 Setup to RD tAR 0 ns
CS, A0 Hold After RD tRA 0 ns
RD Pulse Width tRR 160 ns
CS, A0 to Data Out Delay tAD 130 ns
RD to Data Out Delay tRD 0 130 ns
RD to Data Float Delay tRDZ 85 ns
RPC AC CHARACTERISTICS—DBB WRITE(VCC= 5V ±10%, TA= 0°C to +70°C.) (Figure 7)
PARAMETER SYMBOL MIN MAX UNITS CS, A0 Setup to WR tAW 0 ns
CS Hold After WR tWA 0 ns
A0 Hold After WR tWA 20 ns
WR Pulse Width tWW 160 ns
Data Setup to WR tDW 130 ns
Data Hold After WR tWD 20 ns
AC CHARACTERISTICS—DMA(VCC= 5V ±10%, TA= 0°C to +70°C.)
PARAMETER SYMBOL MIN MAX UNITS DACK to WR or RD tACC 0 ns
RD or WR to DACK tCAC 0 ns
DACK to Data Valid tACD 0 130 ns
RD or WR to DRQ Cleared tCRQ 110 ns
DS5003
Secure Microprocessor Chip
AC CHARACTERISTICS—PROG(VCC= 5V ±10%, TA= 0°C to +70°C.)
PARAMETER SYMBOL MIN MAX UNITS PROG Low to Active tPRA 48 Clocks
PROG High to Inactive tPRI 48 Clocks
Note 1:All voltages are referenced to ground.
Note 2:Maximum operating ICCis measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF= 10ns, VIL= 0.5V;
XTAL2 disconnected; RST = Port 0 = VCC, MSEL = VSS.
Note 3:Idle mode, IIDLE, is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF= 10ns, VIL= 0.5V; XTAL2
disconnected; Port 0 = VCC, RST = MSEL = VSS.
Note 4:Stop mode, ISTOP, is measured with all output pins disconnected; Port 0 = VCC; XTAL2 not connected; RST = MSEL =
XTAL1 = VSS.
Note 5:Pin capacitance is measured with a test frequency: 1MHz, TA= +25°C. This specification is characterized but not produc-
tion tested.
Note 6:VCCO2is measured with VCC< VLIand a maximum load of 10µA on VCCO.
Note 7:ICCO1is the maximum average operating current that can be drawn from VCCOin normal operation.
Note 8:ILIis the current drawn from the VLIinput when VCC= 0V and VCCOis disconnected. Battery-backed mode is 2.5V ≤VBAT4.0; VCC≤VBAT; VSDIshould be ≤VILSfor IBATmax.
Note 9:PFpin operation is specified with VBAT≥3.0V.
Note 10:VIHSminimum is 2.0V or VCCO, whichever is lower.
Note 11:SDI is deglitched to prevent accidental destruction. The pulse must be longer than tSPRto pass the deglitcher, but SDI is
not guaranteed unless it is longer than tSPA.
Note 12:Crystal startup time is the time required to get the mass of the crystal into vibrational motion from the time that power is
first applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the
crystal vendor for a worst-case specification on this time.
ALE
tALPW
tAVDV
tRDPWtALLRDL
tRDHALH
tALLVD
tRDLDV
tAVALL
tAVRDL
tAVAAVtRDLAZ
tRDHDV
tRDHDZ
PORT 0A7–A0
(Rn OR DPL)
P2.7–P2.0 OR A15–A8 FROM DPHA15–A8 FROM PCH
DATA INA7–A0
(PCL)
INSTR
PORT 2
Figure 1. Expanded Data Memory Read Cycle
DS5003
Secure Microprocessor ChipALE
tWRPWtALLRDL
tRDHALH
tAVALL
tAVRDL
tDVWRH
tAVAAV
tWRHDVtDVWRL
PORT 0A7–A0
(Rn OR DPL)
P2.7–P2.0 OR A15–A8 FROM PDHA15–A8 FROM PCH
DATA OUTA7–A0
(PCL)
INSTR
PORT 2
Figure 2. Expanded Data Memory Write Cycle
tCLKHPWtCLKLPW
1/tCLK
tCLKFtCLKR
Figure 3. External Clock Timing
DS5003
Secure Microprocessor ChipINTERRUPT
SERVICE
ROUTINE
CLOCK
OSC
INTERNAL
RESET
LITHIUM
CURRENT
VCC
VPFW
VCCMIN
VLI
tCSV
tPOR
Figure 4. Power-Cycle Timing
DS5003
Secure Microprocessor ChipALE
CLOCK
DATA OUT
WRITE TO SBUF REGISTER
INPUT DATA2345678
CLEAR RI
VALID234567
tSPCLK
tCHDIV
tDOCH
tCHDO
tCHDV
VALIDVALIDVALIDVALIDVALIDVALID
SET RI
SET TI
Figure 5. Serial Port Timing (Mode 0)
XTAL2
ALE
BA0–BA14PC OUT
DATA INDATA INDATA INDATADATA OUT
PC OUTPC OUTPC OUTDPL AND (DPH OR P2 SFR OUT)DPL AND (DPH OR P2 SFR OUT)
BD0–BD7
CE1, CE2,
OR CE1N
CE1, CE2, CE3,
CE4, PE1, PE2,
PE3, PE4, OR CE1N
R/W34561234566123456
MACHINE CYCLEMACHINE CYCLEMACHINE CYCLE
tCEL1LPA
tOVCE1HtDACEH
tCE1HOVtCEHDVtRWLDV
tRWHDV
tCEHDV
tCEL1HPA
tCELDAtCEHDA
tAVRWL
tRWLPW
tCEHDA
tCELDA
tCEPWtCEPW
Figure 6. Byte-Wide Bus Timing
DS5003
Secure Microprocessor Chip
READ OPERATIONDATA VALID
tAR
tRR
tRDtAD
tRA
tRDZ
CS OR A0
DATA
WRITE OPERATIONDATA VALID
tAWtWW
tWDtDW
tWA
CS OR A0
DATA
DMAtACD
tACC
tACC
tCRQtCRQ
tCAC
tCAC
DATAVALIDVALID
DRQ
DACK
Figure 7. RPC Timing Mode
DS5003
Secure Microprocessor Chip
Pin Description
PINNAMEFUNCTION
POWER PINS 13 VCC
Power Supply, +5V 12 VCCO
VCC Output. This is switched between VCC and VLI by internal circuits based on the level of VCC.When power is above the lithium input, power is drawn from VCC. The lithium cell remains
isolated from a load. When VCC is below VLI, VCCO switches to the VLI source. VCCO should be
connected to the VCC pin of an SRAM.
54 VLI
Lithium Voltage Input. Connect to a lithium cell greater than VLIMIN and no greater than VLIMAXas shown in the electrical specifications. Nominal value is +3V.
52 GND
Logic Ground
GENERAL-PURPOSE I/O PINS 11 P0.0/AD0
9 P0.1/AD1
7 P0.2/AD2
5 P0.3/AD3
1 P0.4/AD4
79 P0.5/AD5
77 P0.6/AD6
75 P0.7/AD7
General-Purpose I/O Port 0. This port is open drain and cannot drive a logic 1. It requires external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in this
mode, it does not require pullups.
15 P1.0
17 P1.1
19 P1.2
21 P1.3
25 P1.4
27 P1.5
29 P1.6
31 P1.7
General-Purpose I/O Port 1 49 P2.0/A8
50 P2.1/A9
51 P2.2/A10
56 P2.3/A11
58 P2.4/A12
60 P2.5/A13
64 P2.6/A14
66 P2.7/A15
General-Purpose I/O Port 2. Also serves as the MSB of the expanded address bus. 36 P3.0/RXD
General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on-board UART. This pin should not be connected directly to a PC COM port.
38 P3.1/TXD
General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on-board UART. This pin should not be connected directly to a PC COM port.
39 P3.2/INT0
General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0. 40 P3.3/INT1
General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1. 41 P3.4/T0
General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input. 44 P3.5/T1
General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input. 45 P3.6/WR
General-Purpose I/O Port Pin 3.6. Also serves as the write strobe for expanded bus operation. 46 P3.7/RD
General-Purpose I/O Port Pin 3.7. Also serves as the read strobe for expanded bus operation.
