DS5002FMN-16+ ,Secure Microprocessor ChipFEATURES The DS5002FP secure microprocessor chip is a 8051-Compatible Microprocessor for secure ve ..
DS5002FP ,Secure Microprocessor ChipFeatures analysis, and physical attack. As a result, a massive Memory Stored in Encrypted Form effo ..
DS5002FP-16 ,Secure microprocessor chip, 8051-compatible, in-system programming, 16 MHzFEATURES The DS5002FP secure microprocessor chip is a 8051-Compatible Microprocessor for secure ..
DS5002FP-16-N ,Secure microprocessor chip, 8051-compatible, in-system programming, 16 MHzfeatures available in any Port processor. The security
DS5002FPM/16 ,Secure microprocessor chip, 8051-compatible, in-system programming, 16 MHzApplications microprocessor chip. In addition to the memory and Access 32kB, 64kB, or 128kB of NV S ..
DS5002FPM-16 ,Secure microprocessor chip, 8051-compatible, in-system programming, 16 MHzFeatures analysis, and physical attack. As a result, a massive Memory Stored in Encrypted Form effo ..
EC3H06B ,NPN Epitaxial Planar Silicon Transistor UHF to S Band Low-Noise Amplifier and OSC ApplicationsFeatures Package Dimensions · Low noise : NF=0.9dB typ (f=1GHz).unit:mm: NF=1.4dB typ (f=1.5GHz).21 ..
EC4H07C ,Ultrahigh-Frequency TransistorsFeatures Package Dimensions•Low noise : NF=1.5dB typ (f=2GHz). unit : mm•High cut-off frequency : f ..
ECH8401 ,Medium Output MOSFETsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8402 ,Medium Output MOSFETsAbsolute Maximum Ratings at Ta=25°CParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage ..
ECH8402 ,Medium Output MOSFETsOrdering number : ENN8148 ECH8402N-Channel Silicon MOSFETGeneral-Purpose Switching DeviceECH8402App ..
ECH8410 ,N-Channel Power MOSFET, 30V, 12A, 10mOhm, Single ECH8Maximum RatingsParameter Symbol Conditions Ratings UnitDrain-to-Source Voltage V 30 VDSSGate-to-Sou ..
DS5002FM-C03-DS5002FMN-16+-DS5002FPM-16+
Secure Microprocessor Chip
GENERAL DESCRIPTION The DS5002FP secure microprocessor chip is a
secure version of the DS5001FP 128k soft
microprocessor chip. In addition to the memory and
I/O enhancements of the DS5001FP, the secure
microprocessor chip incorporates the most
sophisticated security features available in any
processor. The security features of the DS5002FP
include an array of mechanisms that are designed to
resist all levels of threat, including observation,
analysis, and physical attack. As a result, a massive
effort is required to obtain any information about
memory contents. Furthermore, the “soft” nature of
the DS5002FP allows frequent modification of the
secure information, thereby minimizing the value of
any secure information obtained by such a massive
effort.
PIN CONFIGURATION
FEATURES �
8051-Compatible Microprocessor for
Secure/Sensitive Applications Access 32kB, 64kB, or 128kB of NV SRAM for
Program and/or Data Storage
In-System Programming Through On-Chip Serial
Port
Can Modify Its Own Program or Data Memory in
the End System �
Firmware Security Features Memory Stored in Encrypted Form
Encryption Using On-Chip 64-Bit Key
Automatic True Random Key Generator
Self Destruct Input (SDI)
Optional Top Coating Prevents Microprobe
(DS5002FPM)
Improved Security Over Previous Generations
Protects Memory Contents from Piracy �
Crash-Proof Operation Maintains All Nonvolatile Resources for Over 10
Years in the Absence of Power
Power-Fail Reset
Early Warning Power-Fail Interrupt
Watchdog Timer
ORDERING INFORMATION
PART TEMP RANGE
INTERNAL
MICRO
PROBE
SHIELD
PIN-
PACKAGE DS5002FPM-16 0°C to +70°C Yes 80 QFP
DS5002FPM-16+ 0°C to +70°C Yes 80 QFP
DS5002FMN-16 -40°C to +85°C Yes 80 QFP
DS5002FMN-16+ -40°C to +85°C Yes 80 QFP
+ Denotes a Pb-free/RoHS-compliant device.
Selector Guide appears at end of data sheet.
DS5002FP
Secure Microprocessor Chip
P0.4AD4
CE2
PE2
BA9
P0.3/AD3
BA8
P0.2/AD2
BA13
P0.1/AD1
R/W
P0.0/AD0
VCC0
VCC
MSEL
P1.0
BA14
P1.1
BA12
P1.2
BA7
P1.3
PE3
PE4
BA6
P2.6/A14
CE3
CE4
BD3
P2.5/A13
BD2
P2.4/A12
BD1
P2.3/A11
BD0
VLI
SDI
GND
P2.2/A10
P2.1/A9
P2.0/A8
XTAL1
XTAL2
P3.7/RD
P3.6/WR
P3.5/TI
PF
VRST
P3.4/T0
Dallas
Semiconductor DS5002FP
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
P1.4
BA5
P1.5
BA4
P1.6
BA3
P1.7
PRO
BA2
RST
BA1
P3.0/RX
BA0
P3.1/TX
P3.2/INT
P3.3/INT
BA11 P0.5/AD
P0.6/AD
BA10 P0.7/AD
N.C. C
E1N
BD7 ALE BD6 N.C. BD5 P2.7/A1
BD4
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
QFP TOP VIEW
DS5002FP Secure Microprocessor Chip
ELECTRICAL SPECIFICATIONS The DS5002FP adheres to all AC and DC electrical specifications published for the DS5001FP.
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground
.-0.3V to (VCC + 0.5V)
Voltage Range on VCC Relative to Ground
-0.3V to +6.0V
Operating Temperature Range
..-40°C to +85°C
Storage Temperature* ...
..-55C to +125°C
Soldering Temperature
.....See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the operation
sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time can affect reliability.
*Storage temperature is defined as the temperature of the device when VCC = 0V and VLI = 0V. In this state the contents of SRAM are not
battery-backed and are undefined.
DC CHARACTERISTICS (VCC = 5V ±10%, TA = 0°C to +70°C.)**
PARAMETER SYMBOLCONDITIONS MIN TYP MAX UNITS Input Low Voltage VIL (Note 1) -0.3 +0.8 V
Input High Voltage VIH1 (Note 1) 2.0 VCC + 0.3 V
Input High Voltage
(RST, XTAL1, PROG) VIH2 (Note 1) 3.5 VCC + 0.3 V
Output Low Voltage at IOL = 1.6mA
(Ports 1, 2, 3, PF) VOL1 (Notes 1, 13) 0.15 0.45 V
Output Low Voltage at IOL = 3.2mA
(Ports 0, ALE, BA150, BD70,
R/W, CE1N, CE 14, PE 14, VRST)
VOL2 (Note 1) 0.15 0.45 V
Output High Voltage at IOH = -80µA
(Ports 1, 2, 3) VOH1 (Note 1) 2.4 4.8 V
Output High Voltage at IOH = -400µA
(Ports 0, ALE, BA150, BD70,
R/W, CE1N, CE 14, PE 14, VRST)
VOH2 (Note 1) 2.4 4.8 V
Input Low Current
VIN = 0.45V (Ports 1, 2, 3) IIL -50 µA
0°C to +70°C -500 Transition Current; 1 to 0
VIN = 2.0V (Ports 1, 2, 3) ITL -40°C to +85°C
(Note 12) -600 µA
SDI Input Low Voltage VILS (Note 1) 0.4 V
SDI Input High Voltage VIHS (Notes 1, 11) 2.0 VCCO V
SDI Pulldown Resistor RSDI 25 60 kΩ
Input Leakage (Port 0, MSEL) IIL 0.45 < VIN < VCC +10 µA
0°C to +70°C 40 150
RST Pulldown Resistor RRE -40°C to +85°C
(Note 12) 30 180 kΩ
VRST Pullup Resistor RVR 4.7 kΩ
PROG Pullup Resistor RPR 40 kΩ
0°C to +70°C
(Note 1) 4.25 4.37 4.5
Power-Fail Warning Voltage VPFW -40°C to +85°C
(Notes 1, 12) 4.1 4.37 4.6
0°C to +70°C
(Note 1) 4.00 4.12 4.25
Minimum Operating Voltage VCCMIN -40°C to +85°C 3.85 4.09 4.25
DS5002FP Secure Microprocessor Chip
DC CHARACTERISTICS (continued) (VCC = 5V ±10%, TA = 0°C to +70°C.)**
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Lithium Supply Voltage VLI (Note 1) 2.5 4.0 V
Operating Current at 16MHz ICC (Note 2) 36 mA
0°C to +70°C (Note 3) 7.0 Idle Mode Current at 12MHz IIDLE -40°C to +85°C (Notes 3, 12) 8.0 mA
Stop Mode Current ISTOP (Note 4) 80 µA
Pin Capacitance CIN (Note 5) 10 pF
Output Supply Voltage (VCCO) VCCO1 (Notes 1, 2) VCC
-0.45 V
0°C to +70°C (Notes 1, 8) VLI
-0.65 Output Supply Battery-Backed
Mode (VCCO, CE1–4, PE 1–2) VCCO2 -40°C to +85°C (Notes 1, 8,
12)
VLI
-0.9
Output Supply Current (Note 6) ICCO1 VCCO = VCC - 0.45V 75 mA
0°C to +70°C 5 75 Lithium-Backed Quiescent
Current (Note 7) ILI -40°C to +85°C 75 500 nA
BAT = 3.0V (0°C to +70°C)
(Note 1) 4.0 4.25
BAT = 3.0V (-40°C to +85°C)
(Notes 1, 12) 3.85 4.25 Reset Trip Point in Stop Mode
BAT = 3.3V (0°C to +70°C)
(Note 1) 4.4 4.65
**All parameters apply to both commercial and industrial temperature operation unless otherwise noted.
Note 1: All voltages are referenced to ground.
Note 2: Maximum operating ICC is measured with all output pins disconnected; XTAL1 driven with tCLKR, tCLKF = 10 ns, VIL = 0.5V; XTAL2
disconnected; RST = PORT0 = VCC, MSEL = VSS.
Note 3: Idle mode IIDLE is measured with all output pins disconnected; XTAL1 driven with tCLKR,tCLKF = 10ns, VIL = 0.5V; XTAL2
disconnected; PORT0 = VCC, RST = MSEL = VSS.
Note4: Stop mode ISTOP is measured with all output pins disconnected; PORT0 = VCC; XTAL2 not connected; RST = MSEL = XTAL1 =
VSS.
Note 5: Pin capacitance is measured with a test frequency: 1MHz, TA = +25°C.
Note 6: ICCO1 is the maximum average operating current that can be drawn from VCCO in normal operation.
Note 7: ILI is the current drawn from VLI input when VCC = 0V and VCCO is disconnected. Battery-backed mode is 2.5V ≤ VBAT ≤ 4.0; VCC ≤
VBAT; VSDI should be ≤ VILS for IBAT max.
Note 8: VCCO2 is measured with VCC < VLI, and a maximum load of 10µA on VCCO.
Note 9: Crystal startup time is the time required to get the mass of the crystal into vibrational motion from the time that power is first
applied to the circuit until the first clock pulse is produced by the on-chip oscillator. The user should check with the crystal
vendor for a worst-case specification on this time.
Note 10: SDI is deglitched to prevent accidental destruction. The pulse must be longer than tSPR to pass the deglitcher, but SDI is not
guaranteed unless it is longer than tSPA.
Note 11: VIHS minimum is 2.0V or VCCO, whichever is lower.
Note 12: This parameter applies to industrial temperature operation.
Note 13: PF pin operation is specified with VBAT ≥ 3.0V.
AC CHARACTERISTICS—SDI PIN (VCC = 0V to 5V, TA = 0°C to +70°C.)
PARAMETER SYMBOL CONDITIONS MINTYP MAX UNITS 4.5V < VCC < 5.5V 1.3 SDI Pulse Reject (Note 10) tSPR VCC = 0V, VBAT = 2.9V 4 µs
4.5V < VCC < 5.5V 10
DS5002FP Secure Microprocessor Chip
AC CHARACTERISTICSEXPANDED BUS MODE TIMING SPECIFICATIONS (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 1 and Figure 2)
# PARAMETER SYMBOL CONDITIONS MIN MAX UNITSOscillator Frequency 1 / tCLK 1.0 16 MHz
2 ALE Pulse Width tALPW 2tCLK - 40 ns Address Valid to ALE Low tAVALL tCLK - 40 ns Address Hold After ALE Low tAVAAV tCLK - 35 ns
14 RD Pulse Width tRDPW 6tCLK - 100 ns
15 WR Pulse Width tWRPW 6tCLK - 100 ns
12MHz 5tCLK - 165 16 RD Low to Valid Data In tRDLDV 16MHz 5tCLK - 105 ns
17 Data Hold after RD High tRDHDV 0 ns
18 Data Float after RD High tRDHDZ 2tCLK - 70 ns
12MHz 8tCLK - 150 19 ALE Low to Valid Data In tALLVD 16MHz 8tCLK - 90 ns
12MHz 9tCLK - 165 20 Valid Address to Valid Data In tAVDV 16MHz 9tCLK - 105 ns
21 ALE Low to RD or WR Low tALLRDL 3tCLK - 50 3tCLK + 50 ns
22 Address Valid to RD or WR
Low tAVRDL 4tCLK - 130 ns
23 Data Valid to WR Going Low tDVWRL tCLK - 60 ns
12MHz 7tCLK - 150 24 Data Valid to WR High tDVWRH 16MHz 7tCLK - 90 ns
25 Data Valid after WR High tWRHDV tCLK-50 ns
26 RD Low to Address Float tRDLAZ 0 ns
27 RD or WR High to ALE High tRDHALH tCLK - 40 tCLK + 50 ns
Figure 1. Expanded Data Memory Read Cycle DS5002FP Secure Microprocessor Chip
Figure 2. Expanded Data Memory Write Cycle
AC CHARACTERISTICSEXTERNAL CLOCK DRIVE (VCC = 5V ± 10%, TA = 0°C to +70°C.) (Figure 3)
# PARAMETER SYMBOL CONDITIONS MIN MAX UNITS 12MHz 20 28 External Clock High Time tCLKHPW 16MHz 15 ns
12MHz 20 29 External Clock Low Time tCLKLPW 16MHz 15 ns
12MHz 20 30 External Clock Rise Time tCLKR 16MHz 15 ns
12MHz 20 31 External Clock Fall Time tCLKF 16MHz 15 ns
Figure 3. External Clock Timing DS5002FP Secure Microprocessor Chip
AC CHARACTERISTICSPOWER CYCLE TIME (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 4)
# PARAMETER SYMBOL MIN MAX UNITS 32 Slew Rate from VCCMIN to VLI tF 130 µs
33 Crystal Startup Time tCSU (Note 9)
34 Power-on Reset Delay tPOR 21504 tCLK
Figure 4. Power Cycle Timing DS5002FP Secure Microprocessor Chip
AC CHARACTERISTICSSERIAL PORT TIMING, MODE 0 (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 5)
# PARAMETER SYMBOL MIN MAX UNITS 35 Serial Port Clock Cycle Time tSPCLK 12tCLK µs
36 Output Data Setup to Rising Clock Edge tDOCH 10tCLK - 133 ns
37 Output Data Hold after Rising Clock Edge tCHDO 2tCLK - 117 ns
38 Clock Rising Edge to Input Data Valid tCHDV 10tCLK - 133 ns
39 Input Data Hold after Rising Clock Edge tCHDIV 0 ns
Figure 5. Serial Port Timing, Mode 0 DS5002FP Secure Microprocessor Chip
AC CHARACTERISTICSBYTE-WIDE ADDRESS/DATA BUS TIMING (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 6)
# PARAMETER SYMBOL MIN MAX UNITS 40 Delay to Byte-Wide Address Valid from CE1,
CE2, or CE1N Low During Op Code Fetch tCE1LPA 30 ns
41 Pulse Width of CE14, PE14, or CE1N tCEPW 4tCLK - 35 ns
42 Byte-Wide Address Hold After CE1, CE2, or
CE1N High During Op Code Fetch tCE1HPA 2tCLK - 20 ns
43 Byte-Wide Data Setup to CE1, CE2, or CE1N
High During Op Code Fetch tOVCE1H 1tCLK + 40 ns
44 Byte-Wide Data Hold After CE1, CE2, or CE1N
High During Op Code Fetch tCE1HOV 0 ns
45 Byte-Wide Address Hold After CE14, PE14, or
CE1N High During MOVX tCEHDA 4tCLK - 30 ns
46 Delay from Byte-Wide Address Valid CE14,
PE14, or CE1N Low During MOVX tCELDA 4tCLK - 35 ns
47 Byte-Wide Data Setup to CE14, PE14, or
CE1N High During MOVX (Read) tDACEH 1tCLK + 40 ns
48 Byte-Wide Data Hold After CE14, PE14, or
CE1N High During MOVX (Read) tCEHDV 0 ns
49 Byte-Wide Address Valid to R/W Active During
MOVX (Write) tAVRWL 3tCLK - 35 ns
50 Delay from R/W Low to Valid Data Out During
MOVX (Write) tRWLDV 20 ns
51 Valid Data Out Hold Time from CE14, PE14, or
CE1N High tCEHDV 1tCLK - 15 ns
52 Valid Data Out Hold Time from R/W High tRWHDV 0 ns
53 Write Pulse Width (R/W Low Time) tRWLPW 6tCLK - 20 ns
Figure 6. Byte-Wide Bus Timing DS5002FP Secure Microprocessor Chip
RPC AC CHARACTERISTICS, DBB READ (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 7)
# PARAMETER SYMBOL MIN MAX UNITS 54 CS, A0 Setup to RD tAR 0 ns
55 CS, A0 Hold After RD tRA 0 ns
56 RD Pulse Width tRR 160 ns
57 CS, A0 to Data Out Delay tAD 130 ns
58 RD to Data Out Delay tRD 0 130 ns
59 RD to Data Float Delay tRDZ 85 ns
RPC AC CHARACTERISTICS, DBB WRITE (VCC = 5V ±10%, TA = 0°C to +70°C.) (Figure 7)
# PARAMETER SYMBOL MIN MAX UNITS 60 CS, A0 Setup to WR tAW 0 ns
61A CS, Hold After WR tWA 0 ns
61B A0, Hold After WR tWA 20 ns
62 WR Pulse Width tWW 160 ns
63 Data Setup to WR tDW 130 ns
64 Data Hold After WR tWD 20 ns
AC CHARACTERISTICS, DMA (VCC = 5V ±10%, TA = 0°C to +70°C.)
# PARAMETER SYMBOL MIN MAX UNITS 65 DACK to WR or RD tACC 0 ns
66 RD or WR to DACK tCAC 0 ns
67 DACK to Data Valid tACD 0 130 ns
68 RD or WR to DRQ Cleared tCRQ 110 ns
AC CHARACTERISTICS, PROG (VCC = 5V ±10%, TA = 0°C to +70°C.)
# PARAMETER SYMBOL MIN MAX UNITS 69 PROG Low to Active tPRA 48 CLKS
70 PROG High to Inactive tPRI 48 CLKS
DS5002FP Secure Microprocessor Chip
Figure 7. RPC Timing Mode DS5002FP Secure Microprocessor Chip
PIN DESCRIPTION
PIN NAME FUNCTION 11, 9, 7, 5,
1, 79, 77,
75
P0.0P0.7
General-Purpose I/O Port 0. This port is open-drain and cannot drive a logic 1. It requires external pullups. Port 0 is also the multiplexed expanded address/data bus. When used in
this mode, it does not require pullups.
15, 17, 19,
21, 25, 27,
29, 31
P1.0P1.7
General-Purpose I/O Port 1 49, 50, 51,
56, 58, 60,
64, 66
P2.0P2.7
General-Purpose I/O Port 2. Also serves as the MSB of the expanded address bus. 36 P3.0/RXD
General-Purpose I/O Port Pin 3.0. Also serves as the receive signal for the on-board UART. This pin should not be connected directly to a PC COM port.
38 P3.1/TXD
General-Purpose I/O Port Pin 3.1. Also serves as the transmit signal for the on-board UART. This pin should not be connected directly to a PC COM port.
39 P3.2/INT0
General-Purpose I/O Port Pin 3.2. Also serves as the active-low external interrupt 0. 40 P3.3/INT1
General-Purpose I/O Port Pin 3.3. Also serves as the active-low external interrupt 1. 41 P3.4/T0
General-Purpose I/O Port Pin 3.4. Also serves as the timer 0 input. 44 P3.5/T1
General-Purpose I/O Port Pin 3.5. Also serves as the timer 1 input. 45 P3.6/WR
General-Purpose I/O Port Pin. Also serves as the write strobe for Expanded bus operation. 46 P3.7/RD
General-Purpose I/O Port Pin. Also serves as the read strobe for Expanded bus operation. 34 RST
Active-High Reset Input. A logic 1 applied to this pin activates a reset state. This pin is pulled down internally so this pin can be left unconnected if not used. An RC power-on reset
circuit is not needed and is not recommended.
70 ALE
Address Latch Enable. Used to demultiplex the multiplexed expanded address/data bus on port 0. This pin is normally connected to the clock input on a 373 type transparent latch.
47, 48 XTAL2, XTAL1
Crystal Connections. Used to connect an external crystal to the internal oscillator. XTAL1 is the input to an inverting amplifier and XTAL2 is the output.
52 GND
Logic Ground 13 VCC
Power Supply, +5V 12 VCCO
VCC Output. This is switched between VCC and VLI by internal circuits based on the level of VCC. When power is above the lithium input, power is drawn from VCC. The lithium cell
remains isolated from a load. When VCC is below VLI, the VCCO switches to the VLI source.
VCCO should be connected to the VCC pin of an SRAM.
54 VLI
Lithium Voltage Input. Connect to a lithium cell greater than VLIMIN and no greater than VLIMAX as shown in the electrical specifications. Nominal value is +3V.
16, 8, 18,
80, 76, 4, 6,
20, 24, 26,
28, 30, 33,
35, 37
BA14BA0
Byte-Wide Address Bus Bits 140. This bus is combined with the nonmultiplexed data bus (BD7BD0) to access NV SRAM. Decoding is performed using CE1 to CE4. Therefore, BA15
is not actually needed. Read/write access is controlled by R/W. BA140 connect directly to an
8k, 32k, or 128k SRAM. If an 8k RAM is used, BA13 and BA14 are unconnected. If a 128k
SRAM is used, the micro converts CE2 and CE3 to serve as A16 and A15, respectively.
71, 69, 67,
65, 61, 59,
57, 55
BD7BD0
Byte-Wide Data Bus Bits 70. This 8-bit bidirectional bus is combined with the nonmultiplexed address bus (BA14BA0) to access NV SRAM. Decoding is performed on
CE1 and CE2. Read/write access is controlled by R/W. D7D0 connect directly to an SRAM,
and optionally to a real-time clock or other peripheral.
10 R/W
Read/Write (Active Low). This signal provides the write enable to the SRAMs on the byte-wide bus. It is controlled by the memory map and partition. The blocks selected as program
(ROM) are write-protected.
74 CE1
Active-Low Chip Enable 1. This is the primary decoded chip enable for memory access on the byte-wide bus. It connects to the chip-enable input of one SRAM. CE1 is lithium-backed.
It remains in a logic-high inactive state when VCC falls below VLI. CE2
Active-Low Chip Enable 2. This chip enable is provided to access a second 32k block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, the micro
converts CE2 into A16 for a 128k x 8 SRAM. CE2 is lithium-backed and remains at a logic
high when VCC falls below VLI.
63 CE3
Active-Low Chip Enable 3. This chip enable is provided to access a third 32k block of memory. It connects to the chip enable input of one SRAM. When MSEL = 0, the micro
DS5002FP Secure Microprocessor Chip
PIN NAME FUNCTION 62 CE4
Active-Low Chip Enable 4. This chip enable is provided to access a fourth 32k block of memory. It connects to the chip-enable input of one SRAM. When MSEL = 0, this signal is
unused. CE4 is lithium-backed and remains at a logic high when VCC falls below VLI.
78 PE1
Active-Low Peripheral Enable 1. Accesses data memory between addresses 0000h and 3FFFh when the PES bit is set to a logic 1. Commonly used to chip enable a byte-wide real-
time clock such as the DS1283. PE1 is lithium-backed and will remain at a logic high when
VCC falls below VLI. Connect PE1 to battery-backed functions only. PE2
Active-Low Peripheral Enable 2. Accesses data memory between addresses 4000h and 7FFFh when the PES bit is set to a logic 1. PE2 is lithium-backed and will remain at a logic
high when VCC falls below VLI. Connect PE2 to battery-backed functions only.
22 PE3
Active-Low Peripheral Enable 3. Accesses data memory between addresses 8000h and BFFFh when the PES bit is set to a logic 1. PE3 is not lithium-backed and can be connected
to any type of peripheral function. If connected to a battery-backed chip, it will need additional
circuitry to maintain the chip enable in an inactive state when VCC < VLI.
23 PE4
Active-Low Peripheral Enable 4. Accesses data memory between addresses C000h and FFFFh when the PES bit is set to a logic 1. PE4 is not lithium-backed and can be connected
to any type of peripheral function. If connected to a battery-backed chip, it will need additional
circuitry to maintain the chip enable in an inactive state when VCC < VLI.
32 PROG
Invokes the Bootstrap Loader on Falling Edge. This signal should be debounced so that only one edge is detected. If connected to ground, the micro enters bootstrap loading on
power-up. This signal is pulled up internally.
42 VRST
This I/O pin (open drain with internal pullup) indicates that the power supply (VCC) has
fallen below the VCCMIN level and the micro is in a reset state. When this occurs, the DS5002FP drives this pin to a logic 0. Because the micro is lithium-backed, this signal is
guaranteed even when VCC = 0V. Because it is an I/O pin, it also forces a reset if pulled low
externally. This allows multiple parts to synchronize their power-down resets.
43 PF
This output goes to a logic 0 to indicate that the micro has switched to lithium backup. This corresponds to VCC < VLI. Because the micro is lithium-backed, this signal is guaranteed
even when VCC = 0V. The normal application of this signal is to control lithium-powered
current to isolate battery-backed functions from non-battery-backed functions.
14 MSEL
Memory Select. This signal controls the memory size selection. When MSEL = +5V, the DS5002FP expects to use 32k x 8 SRAMs. When MSEL = 0V, the DS5002FP expects to use
a 128k x 8 SRAM. MSEL must be connected regardless of partition, mode, etc.
53 SDI
Self-Destruct Input. An active high on this pin causes an unlock procedure. This results in the destruction of Vector RAM, Encryption Keys, and the loss of power from VCCO. This pin
should be grounded if not used.
72 CE1N
Non-Battery-Backed Version of CE1. It is not generally useful since the DS5002FP cannot be used with EPROM due to its encryption.
73 N.C.
No Connection DS5002FP Secure Microprocessor Chip
DETAILED DESCRIPTION The DS5002FP implements a security system that is an improved version of its predecessor, the DS5000FP. Like
the DS5000FP, the DS5002FP loads and executes application software in encrypted form. Up to 128kB of
standard SRAM can be accessed by its byte-wide bus. This RAM is converted by the DS5002FP into lithium-
backed nonvolatile storage for program and data. Data is maintained for over 10 years at room temperature with a
very small lithium cell. As a result, the contents of the RAM and the execution of the software appear unintelligible
to the outside observer. The encryption algorithm uses an internally stored and protected key. Any attempt to
discover the key value results in its erasure, rendering the encrypted contents of the RAM useless.
The secure microprocessor chip offers a number of major enhancements to the software security implemented in
the previous generation DS5000FP. First, the DS5002FP provides a stronger software encryption algorithm that
incorporates elements of DES encryption. Second, the encryption is based on a 64-bit key word, as compared to
the DS5000FPs 40-bit key. Third, the key can only be loaded from an on-chip true random-number generator. As a
result, the true key value is never known by the user. Fourth, a self-destruct input (SDI) pin is provided to interface
to external tamper-detection circuitry. With or without the presence of VCC, activation of the SDI pin has the same
effect as resetting the security lock: immediate erasure of the key word and the 48-byte Vector RAM area. Fifth, an
optional top-coating of the die prevents access of information using microprobing techniques. Finally, customer-
specific versions of the DS5002FP are available that incorporate a one-of-a-kind encryption algorithm.
When implemented as a part of a secure system design, a system based on the DS5002FP can typically provide a
level of security that requires more time and resources to defeat than it is worth to unauthorized individuals who
have reason to try. For a user who wants a preconstructed module using the DS5002FP, RAM, lithium cell, and a
real-time clock, the DS2252T is available and described in a separate data sheet.
BLOCK DIAGRAM Figure 8 is a block diagram illustrating the internal architecture of the DS5002FP. The DS5002FP is a secure
implementation of the DS5001FP 128k soft microprocessor chip. As a result, it operates in an identical fashion to
the DS5001FP, except where indicated. See the DS5001FP data sheet for operating details.
