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DS5001FP-16
128k Soft Microprocessor Chip
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple
FEATURES8051-compatible microprocessor adapts to its
taskAccesses up to 128kB of nonvolatileSRAMIn-system programming through on-chip
serial portCan modify its own program or data
memory– Accesses memory on a separate byte-wide
busPerforms CRC-16 check of NV RAM
memoryDecodes memory and peripheral chipenablesHigh-reliability operationMaintains all nonvolatile resources for
over 10 yearsPower-fail reset– Early warning power-fail interruptWatchdog timerLithium backs user SRAM for
program/data storagePrecision bandgap reference for powermonitorFully 8051-compatible128kB scratchpad RAMTwo timer/countersOn-chip serial port– 32 parallel I/O port pinsSoftware security available with DS5002FP
secure microprocessor
PIN ASSIGNMENT (Top View)
DS5001FP62605856545250484745434135791113151719212224
P1.4
BA5
P1.5
BA4
P1.6
BA3
P1.7
PROG
BA2
RST
BA1
P3.0/RXD
BA0
P3.1/TXD
P3.2/INT0P3.3/INT1
BA11P0.5/AD5PE1P0.6/AD6BA10P0.7/AD7CE1NCCE1NBD7
BD6PSENBD5P2.7/A15BD4
25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
DS5001FP
128k Soft Microprocessor Chip80-Pin MQFP
44-Pin MQFP
DS5001FP
DESCRIPTIONThe DS5001FP 128k soft microprocessor chip is an 8051-compatible microprocessor based on NV RAM
technology and designed for systems that need large quantities of nonvolatile memory. It provides full
compatibility with the 8051 instruction set, timers, serial port, and parallel I/O ports. By using NV RAM
instead of ROM, the user can program and then reprogram the microprocessor while in-system. The
application software can even change its own operation, which allows frequent software upgrades,adaptive programs, customized systems, etc. In addition, by using NV SRAM, the DS5001FP is ideal for
data logging applications. It also connects easily to a Dallas real-time clock.
The DS5001FP provides the benefits of NV RAM without using I/O resources. It uses a nonmultiplexed
byte-wide address and data bus for memory access. This bus performs all memory access and providesdecoded chip enables for SRAM, which leaves the 32 I/O port pins free for application use. The
DS5001FP uses ordinary SRAM and battery-backs the memory contents for over 10 years at room
temperature with a small external battery. A DS5001FP also provides high-reliability operation in harsh
environments. These features include the ability to save the operating state, power-fail reset, power-fail
interrupt, and watchdog timer.
A user programs the DS5001FP through its on-chip serial bootstrap loader. The bootstrap loader
supervises the loading of software into NV RAM, validates it, and then becomes transparent to the user.
Software can be stored in multiple 32kB or one 128kB CMOS SRAM(s). Using its internal partitioning,
the DS5001FP can divide a common RAM into user-selectable program and data segments. This partitioncan be selected at program loading time, but can then be modified later at any time. The microprocessor
decodes memory access to the SRAM and addresses memory through its byte-wide bus. Memory portions
designated code or ROM are automatically write-protected by the microprocessor. Combining program
and data storage in one device saves board space and cost.
The DS5001FP offers several bank switches for access to even more memory. In addition to the primary
data area of 64kB, a peripheral selector creates a second 64kB data space with four accompanying chip
enables. This area can be used for memory-mapped peripherals or more data storage. The DS5001FP can
also use its expanded bus on ports 0 and 2 (like an 8051) to access an additional 64kB of data space.
Lastly, the DS5001FP provides one additional bank switch that changes up to 60kB of the NV RAMprogram space into data memory. Thus, with a small amount of logic, the DS5001 accesses up to 252kB
of data memory.
The DS2251T is available (Refer to the data sheet at /microcontrollers.) for users
who want a preconstructed module using the DS5001FP, RAM, lithium cell, and a real-time clock. Formore details, refer to the Secure Microcontroller User’s Guide. For users desiring software security, the
DS5002FP is functionally identical to the DS5001FP but provides superior firmware security. The 44-pin
version of the device is functionally identical to the 80-pin version but sports a reduced pin count and
footprint.
Refer to the Secure Microcontroller User’s Guide for operating details. This data sheet provides ordering
information, pinout, and electrical specifications.
ORDERING INFORMATION
DS5001FP
Figure 1. BLOCK DIAGRAM
DS5001FP
PIN DESCRIPTION
DS5001FP
DS5001FP
INSTRUCTION SETThe DS5001FP executes an instruction set that is object code-compatible with the industry standard 8051
microcontroller. As a result, software development packages such as assemblers and compilers that have
been written for the 8051 are compatible with the DS5001FP. A complete description of the instruction
set and operation are provided in the Secure Microcontroller User’s Guide. Also note that the DS5001FP
is embodied in the DS2251T module. The DS2251T combines the DS5001FP with between 32k and 128kof SRAM, a lithium cell, and a real-time clock. This is packaged in a 72-pin SIMM module.
MEMORY ORGANIZATIONFigure 2 illustrates the memory map accessed by the DS5001FP. The entire 64k of program and 64k of
data are potentially available to the byte-wide bus. This preserves the I/O ports for application use. The
user controls the portion of memory that is actually mapped to the byte-wide bus by selecting the program
range and data range. Any area not mapped into the NV RAM is reached by the expanded bus on ports 0and 2. An alternate configuration allows dynamic partitioning of a 64k space as shown in Figure 3.
Selecting PES=1 provides another 64k of potential data storage or memory-mapped peripheral space as
shown in Figure 4. These selections are made using special function registers. The memory map and its
controls are covered in detail in the Secure Microcontroller User’s Guide.
Figure 2. MEMORY MAP IN NONPARTITIONABLE MODE (PM = 1)
DS5001FP
Figure 3. MEMORY MAP IN PARTITIONABLE MODE (PM = 0)
Note: Partitionable mode is not supported when MSEL pin = 0 (128kB mode).
DS5001FP
Figure 4. MEMORY MAP WITH PES = 1
DS5001FP
Figure 5 illustrates a typical memory connection for a system using a 128kB SRAM. Note that in this
configuration, both program and data are stored in a common RAM chip Figure 6 shows a similar system
with using two 32kB SRAMs. The byte-wide address bus connects to the SRAM address lines. The
bidirectional byte-wide data bus connects the data I/O lines of the SRAM.
Figure 5. CONNECTION TO 128k x 8 SRAM
DS5001FP
Figure 6. DS5001FP CONNECTION TO 64k x 8 SRAM
POWER MANAGEMENTThe DS5001FP monitors VCC to provide power-fail reset, early warning power-fail interrupt, and switch
over to lithium backup. It uses an internal bandgap reference in determining the switch points. These are
called VPFW, VCCMIN, and VLI, respectively. When VCC drops below VPFW, the DS5001FP performs an
interrupt vector to location 2Bh if the power-fail warning was enabled. Full processor operation continues
regardless. When power falls further to VCCMIN, the DS5001FP invokes a reset state. No further code
execution is performed unless power rises back above VCCMIN. All decoded chip enables and the R/W
signal go to an inactive (logic 1) state. VCC is still the power source at this time. When VCC drops further
to below VLI, internal circuitry switches to the lithium cell for power. The majority of internal circuits are
disabled and the remaining nonvolatile states are retained. Any devices connected VCCO are powered by
the lithium cell at this time. VCCO is at the lithium battery voltage minus approximately 0.45V. This drop
varies depending on the load. Low power SRAMs should be used for this reason. When using the
DS5001FP, the user must select the appropriate battery to match the RAM data retention current and the
desired backup lifetime. Note that the lithium cell is only loaded when VCC < VLI. The User’s Guide has
more information on this topic. The trip points VCCMIN and VPFW are listed in Electrical Specifications.
DS5001FP
ABSOLUTE MAXIMUM RATINGS*Voltage Range on Any Pin Relative to Ground-0.3V to (VCC + 0.5V)
Voltage Range on VCC Related to Ground-0.3��C to 6.0�C
Operating Temperature Range-40�C to +85�C
Storage Temperature Range1-55�C to +125�C
Soldering TemperatureSee IPC/JEDEC J-STD-020AThis is a stress rating only and functional operation of the device at these or any other conditions above
those indicated in the operation sections of this specification is not implied. Exposure to absolutemaximum rating conditions for extended periods of time may affect reliability.Storage temperature is defined as the temperature of the device when VCC = 0V and VLI = 0V. In this
state, the contents of SRAM are not battery-backed and are undefined.
DC CHARACTERISTICS (TA = 0°C to +70°C; VCC = 5V ±10%)
DS5001FP
DC CHARACTERISTICS (continued) (TA = 0°C to +70°C; VCC = 5V ±10%)
DS5001FP
AC CHARACTERISTICS
EXPANDED BUS MODE TIMING SPECIFICATIONS
(TA = 0°C to +70°C; VCC = 5V ±10%)
