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DS5000-32-16+-DS5000T-32-16+
Soft Microcontroller Module
FEATURES � 8-Bit 8051-Compatible Microcontroller
Adapts to Task at Hand 8 or 32 kbytes of Nonvolatile RAM for
Program and/or Data Memory Storage
Initial Downloading of Software in End
System via On-Chip Serial Port
Capable of Modifying Its Own Program
and/or Data Memory in End Use � Crashproof Operation
Maintains All Nonvolatile Resources for 10
Years in the Absence of VCC at Room
Temperature
Power-Fail Reset
Early Warning Power-Fail Interrupt
Watchdog Timer � Software Security Feature
Executes Encrypted Software to Prevent
Unauthorized Disclosure � On-Chip, Full-Duplex Serial I/O Ports � Two On-Chip Timer/Event Counters � 32 Parallel I/O Lines � Compatible with Industry Standard 8051
Instruction Set and Pinout � Optional Permanently Powered Real-Time
Clock (DS5000T)
PIN ASSIGNMENT
DESCRIPTION The DS5000(T) Soft Microcontroller Module is a fully 8051-compatible 8-bit CMOS microcontroller that
offers “softness” in all aspects of its application. This is accomplished through the comprehensive use of
nonvolatile technology to preserve all information in the absence of system VCC. The internal
program/data memory space is implemented using either 8 or 32 kbytes of nonvolatile CMOS SRAM.
Furthermore, internal data registers and key configuration registers are also nonvolatile. An optional real-
time clock (RTC) gives permanently powered timekeeping. The clock keeps time to a hundredth of a
second using an on-board crystal.
Note: This data sheet provides ordering information, pinout, and electrical specifications. Refer to the Secure Microcontroller User’s Guide for operating information.
DS5000(T)
Soft Microcontroller Module
P1.0P1.1P1.2P1.3P1.4P1.5P1.6P1.7RSTRXD P3.0TXD P3.1INT0 P3.2INT1 P3.3T0 P3.4T1 P3.5WR P3.6RD P3.7XTAL2XTAL1GND
VCC40
P0.0 AD039
P0.1 AD138
P0.2 AD237
P0.3 AD336
P0.4 AD435
P0.5 AD534
P0.6 AD633
P0.7 AD73231
ALE30
PSEN29
P2.7 A1528
P2.6 A1427
P2.5 A1326
P2.4 A1225
P2.3 A1124
P2.2 A1023
P2.1 A922
P2.0 A821
40-Pin Encapsulated Package
DS5000(T)
DS5000(T)
ORDERING INFORMATION
PART RAM SIZE (kB) MAX CRYSTAL
SPEED (MHz) TIMEKEEPING
DS5000-32-16 32 16 No
DS5000-32-16+ 32 16 No
DS5000T-32-16 32 16 Yes
DS5000T-32-16+ 32 16 Yes
+ Denotes a lead-free package.
DS5000(T) BLOCK DIAGRAM Figure 1 DS5000(T)
PIN DESCRIPTION
PIN NAME FUNCTION 1–8 P1.0–P1.7 General-Purpose I/O Port 1
9 RST Active-High Reset Input. A logic 1 applied to this pin will activate a reset state.
This pin is pulled down internally so this pin can be left unconnected if not used.
10 P3.0/RXD General-Purpose I/O Port Pin 3.0/Receive Signal for On-Board UART. This pin
should not be connected directly to a PC COM port.
11 P3.1/TXD General-Purpose I/O Port Pin 3.1/Transmit Signal for On-Board UART. This pin
should not be connected directly to a PC COM port.
12 P3.2/INT0 General-Purpose I/O Port Pin 3.2/Active-Low External Interrupt 0
13 P3.3/INT1 General-Purpose I/O Port Pin 3.3/Active-Low External Interrupt 1
14 P3.4/T0 General-Purpose I/O Port Pin 3.4/Timer 0 Input
15 P3.5/T1 General-Purpose I/O Port Pin 3.5/Timer 1 Input
16 P3.6/WR General-Purpose I/O Port Pin 3.6/Active-Low Write Strobe for Expanded Bus
Operation
17 P3.7/RD General-Purpose I/O Port Pin 3.7/Active-Low Read Strobe for Expanded Bus
Operation
18, 19 XTAL2,
XTAL1
Crystal Connection. Used to connect an external crystal to the internal oscillator.
XTAL1 is the input to an inverting amplifier and XTAL2 is the output.
20 GND Logic Ground
21–28 P2.0–P2.7/
A8–A15 General-Purpose I/O Port 2/MSB of the Expanded Address Bus
29 PSEN
Active-Low Program Store Enable. Used to enable an external program memory
when using the expanded bus. It is normally an output and should be unconnected
if not used. PSEN also is used to invoke the bootstrap loader. At this time, PSEN is
pulled down externally. This should only be done once the DS5000(T) is already in
a reset state. The device that pulls down should be open drain since it must not
interfere with PSEN under normal operation.
30 ALE
Address Latch Enable. Used to demultiplex the multiplexed expanded address/data
bus on Port 0. This pin is normally connected to the clock input on a ’373 type
transparent latch. When using a parallel programmer, this pin also assumes the
PROG function for programming pulses.
31 EA
Active-Low External Access. This pin forces the DS5000(T) to behave like an
8031. No internal memory (or clock) is available when this pin is at a logic low.
Since this pin is pulled down internally, it should be connected to +5V to use NV
RAM. In a parallel programmer, this pin also serves as VPP for super voltage
pulses.
32-39 P0.7–P0.0/
AD7–AD0
General-Purpose I/O Port 0/Multiplexed Expanded Address/Data Bus. This port is
open drain and cannot drive a logic 1. It requires external pullups. When used in
the multiplexed expanded address data/bus mode, this pin does not require pullups.
40 VCC +5V Power Supply
DS5000(T)
INSTRUCTION SET The DS5000(T) executes an instruction set which is object code-compatible with the industry standard
8051 microcontroller. As a result, software development packages that have been written for the 8051,
including cross-assemblers, high-level language compilers, and debugging tools, are compatible with the
DS5000(T).
A complete description for the DS5000(T) instruction set is available in Secure Microcontroller User’s
Guide.
MEMORY ORGANIZATION Figure 2 illustrates the address spaces, which are accessed by the DS5000(T). As illustrated in the figure,
separate address spaces exist for program and data memory. Since the basic addressing capability of the
machine is 16 bits, a maximum of 64 kbytes of program memory and 64 kbytes of data memory can be
accessed by the DS5000(T) CPU. The 8- or 32-kbyte RAM area inside of the DS5000(T) can be used to
contain both program and data memory.
The real-time clock (RTC) in the DS5000T is reached in the memory map by setting a SFR bit. The
MCON.2 bit (ECE2) is used to select an alternate data memory map. While ECE2 = 1, all MOVXs will
be routed to this alternate memory map. The RTC is a serial device that resides in this area. A full
description of the RTC access and example software is given in the Secure Microcontroller User’s Guide.
If the ECE2 bit is set on a DS5000 without a timekeeper, the MOVXs will simply go to a nonexistent
memory. Software execution would not be affected otherwise.
DS5000(T)
DS5000(T) LOGICAL ADDRESS SPACES Figure 2
PROGRAM LOADING The Program Load Modes allow initialization of the NV RAM Program/Data Memory. This initialization
may be performed in one of two ways:
1. Serial Program Loading that can perform Bootstrap Loading of the DS5000(T). This feature allows
the loading of the application program to be delayed until the DS5000(T) is installed in the end
system. Dallas Semiconductor strongly recommends the use of serial program loading because of its
versatility and ease of use.
2. Parallel Program Load cycles that perform the initial loading from parallel address/data information
presented on the I/O port pins. This mode is timing-set compatible with the 8751H microcontroller
programming mode.
The DS5000(T) is placed in its Program Load configuration by simultaneously applying a logic 1 to the
RST pin and forcing the PSEN line to a logic 0 level. Immediately following this action, the DS5000(T)
will look for a parallel Program Load pulse, or a serial ASCII carriage return (0DH) character received at
9600, 2400, 1200, or 300 bps over the serial port.
The hardware configurations used to select these modes of operation are illustrated in Figure 3.
DS5000(T)
PROGRAM LOADING CONFIGURATIONS Figure 3 Table 1 summarizes the selection of the available Parallel Program Load cycles. The timing associated
with these cycles is illustrated in the electrical specs.
SERIAL BOOTSTRAP LOADER The Serial Program Load Mode is the easiest, fastest, most reliable, and most complete method of
initially loading application software into the DS5000(T) nonvolatile RAM. Communication can be
performed over a standard asynchronous serial communications port. A typical application would use a
simple RS232C serial interface to program the DS5000(T) as a final production procedure. The hardware
configuration required for the Serial Program Load mode is illustrated in Figure 3. Port pins 2.7 and 2.6
must be either open or pulled high to avoid placing the DS5000(T) in a parallel load cycle. Although an
11.0592 MHz crystal is shown in Figure 3, a variety of crystal frequencies and loader baud rates are
supported, shown in Table 2. The serial loader is designed to operate across a 3-wire interface from a
standard UART. The receive, transmit, and ground wires are all that are necessary to establish
communication with the DS5000(T).
The Serial Bootstrap Loader implements an easy-to-use command line interface that allows an application
program in an Intel hex representation to be loaded into and read back from the device. Intel hex is the
typical format which existing 8051 cross-assemblers output. The serial loader responds to single
character commands, which are summarized below:
DS5000(T)
COMMAND FUNCTION C Return CRC-16 checksum of embedded RAM
D Dump Intel hex file
F Fill embedded RAM block with constant
K Load 40-bit encryption key
L Load Intel hex file
R Read MCON register
T Trace (echo) incoming Intel hex data
U Clear security lock
V Verify embedded RAM with incoming Intel hex
W Write MCON register
Z Set security lock
P Put a value to a port
G Get a value from a port
PARALLEL PROGRAM LOAD CYCLES Table 1
MODE RST PSEN PROG EA P2.7 P2.6 P2.5 Program 1 0 0 VPP 1 0 X
Security Set 1 0 0 VPP 1 1 X
Verify 1 X X 1 0 0 X
Prog Expanded 1 0 0 VPP 0 1 0
Verify Expanded 1 0 1 1 0 1 0
Prog MCON or Key registers 1 0 0 VPP 0 1 1
Verify MCON registers 1 0 1 1 0 1 1
The Parallel Program Cycle is used to load a byte of data into a register or memory location within the
DS5000(T). The Verify Cycle is used to read this byte back for comparison with the originally loaded
value to verify proper loading. The Security Set Cycle may be used to enable and the Software Security
feature of the DS5000(T). One may also enter bytes for the MCON register or for the five encryption
registers using the Program MCON cycle. When using this cycle, the absolute register address must be
presented at Ports 1 and 2 as in the normal program cycle (Port 2 should be 00H). The MCON contents
can likewise be verified using the Verify MCON cycle.
When the DS5000(T) first detects a Parallel Program Strobe pulse or a Security Set Strobe pulse while in
the Program Load Mode following a Power-On Reset, the internal hardware of the DS5000(T) is
initialized so that an existing 4-kbyte program can be programmed into a DS5000(T) with little or no
modification. This initialization automatically sets the Range Address for 8 kbytes and maps the lowest 4-
kbyte bank of Embedded RAM as program memory. The next 4 kbytes of Embedded RAM are mapped
as Data Memory.
In order to program more than 4 kbytes of program code, the Program/Verify Expanded cycles can be
used. Up to 32 kbytes of program code can be entered and verified. Note that the expanded 32-kbyte
Program/ Verify cycles take much longer than the normal 4-kbyte Program/Verify cycles.
DS5000(T)
A typical parallel loading session would follow this procedure. First, set the contents of the MCON
register with the correct range and partition only if using expanded programming cycles. Next, the
encryption registers can be loaded to enable encryption of the program/data memory (not required). Then,
program the DS5000(T) using either normal or expanded program cycles and check the memory contents
using Verify cycles. The last operation would be to turn on the security lock feature by either a Security
Set cycle or by explicitly writing to the MCON register and setting MCON.0 to a 1.
SERIAL LOADER BAUD RATES FOR
DIFFERENT CRYSTAL FREQUENCIES Table 2
BAUD RATE CRYSTAL FREQ
(MHz) 300 1200 2400 9600 19200 57600 14.7456 Y Y Y Y
11.0592 Y Y Y Y Y Y
9.21600 Y Y Y Y
7.37280 Y Y Y Y
5.52960 Y Y Y Y
1.84320 Y Y Y Y
ADDITIONAL INFORMATION Refer to the Secure Microcontroller User’s Guide for a complete description for all operational aspects of
the DS5000(T).
DEVELOPMENT SUPPORT The DS89C450-K00 evaluation kit (/DS89C450evkit) can be used to develop and
test user code. It allows the user to download Intel hex-formatted code to the DS5000(T) from a PC.
Refer to the Secure Microcontroller User’s Guide for more information.
DS5000(T)
ABSOLUTE MAXIMUM RATINGS Voltage on Any Pin Relative to Ground…………………………………………………….-0.3V to +7.0V
Operating Temperature…………………………………………………………………….….0°C to +70°C
Storage Temperature………………………………………………………………………...-40°C to +70°C
Soldering Temperature.…………………………………………See IPC/JEDEC J-STD-020 Specification
This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this
specification is not implied. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability.
DC CHARACTERISTICS (tA=0°C to 70°C; VCC=5V ± 5%)
PARAMETER SYMBOLMIN TYP MAX UNITS NOTES Input Low Voltage VIL -0.3 0.8 V 1
Input High Voltage VIH1 2.0 VCC+0.3 V 1
Input High Voltage RST, XTAL1 VIH2 3.5 VCC+0.3 V 1
Output Low Voltage
@ IOL=1.6 mA (Ports 1, 2, 3)
VOL1 0.15 0.45 V
Output Low Voltage
@ IOL=3.2 mA (Ports 0, ALE, PSEN)
VOL2 0.15 0.45 V 1
Output High Voltage
@ IOH=-80 µA (Ports 1, 2, 3)
VOH1 2.4 4.8 V 1
Output High Voltage
@ IOH=-400 µA (Ports 0, ALE, PSEN)
VOH2 2.4 4.8 V 1
Input Low Current VIN = 0.45V
(Ports 1, 2, 3)
IIL -50 µA
Transition Current; 1 to 0
VIN=2.0V (Ports 1, 2, 3)
ITL -500 µA
Input Leakage Current
0.45 < VIN < VCC (Port 0)
IL ±10 µA
RST, EA Pulldown Resistor RRE 40 125 kΩ
Stop Mode Current ISM 80 µA 4
Power-Fail Warning Voltage VPFW 4.15 4.6 4.75 V 1
Minimum Operating Voltage VCCmin 4.05 4.5 4.65 V 1
Programming Supply Voltage
(Parallel Program Mode)
VPP 12.5 13 V 1
Program Supply Current IPP 15 20 mA
Operating Current DS5000-8k @ 8MHz
DS5000-32k @ 12 MHz
DS5000(T)-32-16 @ 16 MHz
ICC 25.2
35.7
45.6
43
48
54
mA 2
Idle Mode Current @ 12 MHz ICC 4.5 6.2 mA 3
AC CHARACTERISTICS: EXPANDED
BUS MODE TIMING SPECIFICATIONS (tA=0°C to 70°C; VCC=5V ± 5%)
# PARAMETER SYMBOLMIN 1 Oscillator Frequency 1/tCLK 1.0 16 MHz ALE Pulse Width tALPW 2tCLK -40 ns Address Valid to ALE Low tAVALL tCLK -40 ns Address Hold After ALE Low tAVAAV tCLK -35 ns ALE Low to Valid Instr. In @ 12 MHz @ 16 MHz
tALLVI 4tCLK -150
4tCLK -90
ns
ns ALE Low to PSEN Low tALLPSL tCLK -25 ns PSEN Pulse Width tPSPW 3tCLK -35 ns PSEN Low to Valid Instr. In @ 12 MHz @ 16 MHz
tPSLVI 3tCLK -150
3tCLK -90
ns
ns Input Instr. Hold after PSEN Going High tPSIV 0 ns
10 Input Instr. Float after PSEN Going High tPSIX tCLK -20 ns
11 Address Hold after PSEN Going High tPSAV tCLK -8 ns
12 Address Valid to Valid Instr. In @ 12 MHz @ 16 MHz
tAVVI 5tCLK -150
5tCLK -90
ns
ns
13 PSEN Low to Address Float tPSLAZ 0 ns
14 RD Pulse Width tRDPW 6tCLK -100 ns
15 WR Pulse Width tWRPW 6tCLK -100 ns
16 RD Low to Valid Data In @ 12 MHz @ 16 MHz
tRDLDV 5tCLK -165
5tCLK -105
ns
ns
17 Data Hold after RD High tRDHDV 0 ns
18 Data Float after RD High tRDHDZ 2tCLK -70 ns
19 ALE Low to Valid Data In @ 12 MHz @ 16 MHz
tALLVD 8CLK -150
8tCLK -90
ns
ns
20 Valid Addr. to Valid Data In @ 12 MHz @ 16 MHz
tAVDV 9tCLK -165
9tCLK -105
ns
ns
21 ALE Low to RD or WR Low tALLRDL 3tCLK -50 3tCLK +50 ns
22 Address Valid to RD or WR Low tAVRDL 4tCLK -130 ns
23 Data Valid to WR Going Low tDVWRL tCLK -60 ns
24 Data Valid to WR High @ 12 MHz @ 16 MHz
tDVWRH 7tCLK -150
7tCLK -90 ns
ns
25 Data Valid after WR High tWRHDV tCLK -50 ns
26 RD Low to Address Float tRDLAZ 0 ns
