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DS4M200D+33
3.3V Margining Clock Oscillator with LVPECL/LVDS Output
General DescriptionThe DS4M125/DS4M133/DS4M200 are margining clock
oscillators with LVPECL or LVDS outputs. They are
designed to fit in a 5mm x 3.2mm ceramic package with
an AT-cut fundamental-mode crystal to form a complete
clock oscillator. The circuit can generate the following
frequencies and their ±5% frequency deviations:
125MHz, 133.33MHz, and 200MHz. The DS4M125/
DS4M133/DS4M200 employ a low-jitter PLL to generate
the frequencies. The typical phase jitter is less than
0.9ps RMS from 12kHz to 20MHz.
Frequency margining is a circuit operation to change
the output frequency to 5% higher or 5% lower than the
nominal frequency. Frequency margining is accom-
plished through the margining select pin, MS. This
three-state input pin accepts a three-level voltage signal
to control the output frequency. In a low-level state, the
output frequency is set to the nominal frequency. When
set to a high-level state, the frequency output is set to
the nominal frequency plus 5%. When set to the mid-
level state, the frequency output is equal to the nominal
frequency minus 5%. If left open, the MS pin is pulled
low by an internal 100kΩ(nominal) pulldown resistor.
The DS4M125/DS4M133/DS4M200 are available with
either an LVPECL or LVDS output. The output can be
disabled by pulling the OE pin low. When disabled,
both OUTP and OUTN levels of the LVPECL driver go to
the LVPECL bias voltage, while the output of the LVDS
driver is a logical one. The OE input is an active-high
logic signal and has an internal 100kΩpullup resistor.
When OE is in a logic-high state, the OUTP and OUTN
outputs are enabled.
The devices operate from a single 3.3V supply voltage.
ApplicationsMemory Clocks
RAID Systems
FeaturesFrequency Margining: ±5%Nominal Clock Output Frequencies: 125MHz,
133.33MHz, and 200MHzJitter < 0.9ps RMS from 12kHz to 20MHzLVPECL or LVDS Output3.3V Operating VoltageOperating Temperature Range: -40°C to +85°CSupply Current: < 100mA at 3.3VExcellent Power-Supply Noise Rejection5mm x 3.2mm Ceramic LCCC PackageOutput Enable/Disable
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator withVPECL/LVDS Output
Ordering InformationDS4M125/
DS4M133/
DS4M200
DS4M125/
DS4M133/
DS4M200
VCCOUTP
OUTN
LVDS OPTION
GND
0.01μF0.1μF
100Ω
GND
VCCOUTP
OUTN
LVPECL OPTION
0.01μF0.1μF
50Ω
50Ω
PECL_BIAS AT
VCC - 2.0V
Typical Operating CircuitRev 0; 12/07
PARTTEMP RANGEPIN-PACKAGE
DS4M125P+33 -40°C to +85°C 10 LCCC DS4M125D+33 -40°C to +85°C 10 LCCC
DS4M133P+33 -40°C to +85°C 10 LCCC DS4M133D+33 -40°C to +85°C 10 LCCC
DS4M200P+33 -40°C to +85°C 10 LCCC DS4M200D+33 -40°C to +85°C 10 LCCC
+Denotes a lead(Pb)-free package. The lead finish is JESD97
category e4 (Au over Ni) and is compatible with both lead-based
and lead-free soldering processes.
Pin Configuration and Selector Guide appear at end of
data sheet.
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VCC= 3.135V to 3.465V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Power-Supply Voltage Range (VCC).....................-0.3V to +4.0V
Continuous Power Dissipation (TA= +70°C)...................330mW
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+125°C
Storage Temperature Range...............................-55°C to +85°C
Soldering Temperature
(3 passes max of reflow)..........................................Refer to the
IPC/JEDEC J-STD-020 Specification.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOperating Voltage Range VCC (Note 1) 3.135 3.3 3.465 V
ICC_D LVDS, output loaded or unloaded 52 75
ICC_PU LVPECL, output unloaded 49 70 Operating Current
ICC_PI LVPECL, output loaded 74 100
mA
Inactive Current ICC_OEZ VOE = VIL 52 85 mA
OUTPUT FREQUENCY SPECIFICATIONS DS4M125 MS = 0, OE = 1 125
DS4M133 MS = 0, OE = 1 133.33 Frequency
DS4M200
MS = 0, OE = 1 200
MHz
Frequency Stability fTOTAL/fOOver temperature range, aging, load,
supply, and initial tolerance (Note 3) -50 +50 ppm
Frequency Stability Over
Temperature fTEMP/f VCC = 3.3V -35 +35 ppm
Initial Tolerance fINITIAL/fV VCC = 3.3V, TA = +25°C ±20 ppm
Frequency Change Due to VCCfVCC/f VCC = 3.3V ±5% -3 +3 ppm/V
Frequency Change Due to Load
Variation fLOAD/fO±10% variation in termination
resistance ±1 ppm
Aging (15 Years) fAGING -7 +7 ppm
Phase Jitter JRMSIntegrated phase RMS; 12kHz to 80MHz,
VCC = 3.3V, TA = +25°C < 0.9 ps
Accumulated Deterministic Jitter
Due to Reference Spurs No margin 155.52MHz output 0.6 ps
10kHz 12.9
100kHz (Note 4) 26.3
200kHz (Note 4) 20.1
Accumulated Deterministic Jitter
Due to Power-Supply Noise
1MHz (Note 4) 6.4
ps
Startup Time tSTRT 1.0 ms
Frequency Switch Time tSWITCH 0.5 ms
Input-Voltage High (OE) VIH (Note 5) 0.7 x
VCC VCC V
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator withVPECL/LVDS Output
ELECTRICAL CHARACTERISTICS (continued)(VCC= 3.135V to 3.465V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSInput-Voltage Low (OE) VIL (Note 5) 0 0.3 x
VCCV
Input-Leakage High (OE) ILEAKH OE voltage = VCC -5 +5 μA
Input-Leakage Low (OE) ILEAKL OE voltage = GND -20 -50 μA
Input-Leakage High (MS) ILEAKH MS voltage = VCC 20 50 μA
Input-Leakage Low (MS) ILEAKL MS voltage = GND -5 +5 μA
Input Voltage: High Level (MS) VIH (Note 5)
0.75 x
VCC +
0.15V
VCC V
Input Voltage: Mid Level (MS) VIM (Note 5)
0.25 x
VCC +
0.15V
0.75 x
VCC -
0.15V
Input Voltage: Low Level (MS) VIL (Note 5) 0
0.25 x
VCC -
0.15V
LVDS Output High Voltage VOH 100 differential load (Notes 2, 5) 1.475 V
Output Low Voltage VOL 100 differential load (Notes 2, 5) 0.925 V
Differential Output Voltage |VOD|100 differential load 250 425 mV
Change in VOD for
Complementary States |VOD| 100 differential load 25 mV
Offset Output Voltage VOS 100 differential load (Note 2) 1.125 1.275 V
Change in VOS for
Complementary States |VOS| 100 differential load 150 mV
Differential Output Impedance ROLVDS 80 140
LVSSLVDSOOUTN or OUTP shorted to ground and
measure the current in the shorting path 40
Output Current
LLVDSOOUTN and OUTP shorted together and
measure the change in ICC 6.5
mA
Output Rise Time (Differential) tRLVDSO 20% to 80% 175 ps
Output Fall Time (Differential) tFLVDSO 80% to 20% 175 ps
Duty Cycle DCYCLE_LVDS 45 55 %
Propagation Delay from OE Going
LOW to Logical 1 at OUTP tPA1 (Figure 2) 200 ns
Propagation Delay from OE Going
HIGH to Output Active tP1A (Figure 2) 200 ns
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator with
LVPECL/LVDS Output
ELECTRICAL CHARACTERISTICS (continued)(VCC= 3.135V to 3.465V, TA= -40°C to +85°C, unless otherwise noted.) (Notes 1, 2)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVPECL Output High Voltage (Note 2) VOHOutput connected to 50 at PECL_BIAS
at VCC - 2.0V
VCC -
1.085
VCC -
0.88 V
Output Low Voltage (Note 2) VOLOutput connected to 50 at PECL_BIAS
at VCC - 2.0V
VCC -
1.825
VCC -
1.62 V
Differential Voltage VDIFF_PECLOutput connected to 50 at PECL_BIAS
at VCC - 2.0V 0.595 0.710 V
Rise Time tR-PECL 20% to 80% 200 ps
Fall Time tF-PECL 80% to 20% 200 ps
Duty Cycle DCYCLE_PECL 45 55 %
Propagation Delay from OE Going
LOW to Output Three-Stated tPAZ (Figure 3) 200 ns
Propagation Delay from OE Going
HIGH to Output Active tPZA (Figure 3) 200 ns
Note 1:Limits at -40°C are guaranteed by design and are not production tested. Typical values are at +25°C and 3.3V, unless
otherwise noted.
Note 2:AC parameters are guaranteed by design and characterization and are not production tested.
Note 3:Frequency stability is calculated as: ΔfTOTAL= ΔfINITIAL+ ΔfTEMP+ (ΔfVCCx 0.165) + ΔfLOAD+ ΔfAGING.
Note 4:Supply induced jitter is measured with a 50mVP-Psine wave forced on VCC. Deterministic jitter is calculated by measuring
the power of the resulting tone seen on a spectrum analyzer.
Note 5:Voltage referenced to ground.
SINGLE-SIDEBAND PHASE NOISE AT fO = fNOM (dBc/Hz)fM = 125MHz133.33MHz200MHz10Hz -70 -75 -70
100Hz -100 -105 -100
1kHz -118 -121 -115
10kHz -118 -122 -117
100kHz -124 -126 -122
1MHz -142 -141 -138
10MHz -150 -150 -150
20MHz -150 -150 -150
SINGLE-SIDEBAND PHASE NOISE AT fO= fNOM
DS4M125/DS4M133/DS4M200
3.3V Margining Clock Oscillator withVPECL/LVDS Output
Pin Description
PINNAMEFUNCTIONOE Active-High Output Enable. Has an internal pullup 100k resistor.MS Margin Select. Three-level input with a 100k pulldown resistor.
3 GND Ground OUTP Positive Output for LVPECL or LVDS OUTN Negative Output for LVPECL or LVDS
6 VCC Supply Voltage
7–10 N.C. No Connection. Must be floated.
— EP Exposed Paddle. The exposed pad must be used for thermal relief. This pad must be connected to
ground.
FREQUENCY vs. TEMPERATUREDS4M125/DS4M133/DS4M200 toc01
TEMPERATURE (°C)
fOUT
DEVIATION (ppm)60-2002040
fO + 5%
fO - 5%
CURRENT vs. TEMPERATUREDS4M125/DS4M133/DS4M200 toc02
TEMPERATURE (°C)
ICC
(mA)60-2002040
Typical Operating Characteristics
(VCC= +3.3V, TA = +25°C, unless otherwise noted.)
DS4M125/DS4M133/DS4M200
Detailed DescriptionThe DS4M125/DS4M133/DS4M200 consist of an oscil-
lator designed to oscillate with a fundamental-mode
crystal and a PLL to synthesize the base frequency with
its ±5% deviations. The output interface is either
LVPECL or LVDS.
The ±5% frequency deviation is controlled through a
three-level margining select (MS) pin. This three-state
input pin accepts a three-level voltage signal to control
the output frequency. In a low-level state, the output
frequency is set to the nominal frequency. When set to
a high-level state, the frequency output is set to the
nominal frequency plus 5%. When set to the mid-level
state, the frequency output is equal to the nominal fre-
quency minus 5%. The MS pin has an internal 100kΩ
pulldown resistor. When the pin is left floating, the
devices output a nominal frequency.
The devices are available with either LVDS or LVPECL
output drivers. When the OE signal is low, the LVPECL
output driver is turned off and the output voltage goes
to the PECL_BIAS level of VCC- 2.0V, while the LVDS
outputs are a logical one. The OE pin has an internal
100kΩpullup resistor. When the pin is left floating, the
device output is active.
3.3V Margining Clock Oscillator with
LVPECL/LVDS OutputDIVP
DIVFB
THREE-
STATE
PHASE
DET
FILTER
LC-VCO
THREE-
LEVEL
DECODER
DIVOUT
OUTSELN
FREQUENCY SELECTION
OUTDRV
VCC
OUTP
OUTN
GND
DS4M125/
DS4M133/
DS4M200
Figure 1. Functional Diagram
OUTP
tP1A
tPA1
0.7 x VCC
0.3 x VCC
OUTN
Figure 2. LVDS Output Timing Diagram When OE Is Enabled
OUTPPECL_BIASPECL_BIAS
PECL_BIASPECL_BIASOUTN
0.7 x VCC
0.3 x VCC
tPAZ
tPZA
Figure 3. LVPECL Output Timing Diagram When OE Is Enabled
