DS4550E ,2.7 to 5.5 V, I2C and JTAG nonvolatile 9-bit I/O expander plus memoryApplications♦ Low Power ConsumptionRAM-Based FPGA Bank Switching for MultipleProfiles♦ Wide Operati ..
DS481TM ,Low Power RS-485/RS-422 Multipoint Transceiver with Sleep Mode
DS485TMX ,Low-Power RS-485/RS-422 Multipoint Transceiver
DS485TN ,Low-Power RS-485/RS-422 Multipoint Transceiver
DS4E-M-DC12V , HIGHLY SENSITIVE 1500 V FCC SURGE WITHSTANDING MINIATURE RELAY
DS4E-M-DC12V , HIGHLY SENSITIVE 1500 V FCC SURGE WITHSTANDING MINIATURE RELAY
EC2-24 ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-24NU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-4.5NJ ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-4.5NU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-4.5TNU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-5ND ,High Insulation, High breakdown voltage, compact and lightweight, Surface mounting type
DS4550E
2.7 to 5.5 V, I2C and JTAG nonvolatile 9-bit I/O expander plus memory
General DescriptionThe DS4550 is a 9-bit, nonvolatile (NV) I/O expander
with 64 bytes of NV user memory controlled by either
an I2CTM-compatible serial interface or an IEEE 1149.1
JTAG port. The DS4550 offers a digitally programmable
alternative to hardware jumpers and mechanical
switches that are being used to control digital logic
nodes. Each I/O pin is independently configurable. The
outputs are open drain with selectable pullups. Each
output has the ability to sink up to 16mA, and since the
device is NV, it powers up in the desired state allowing
it to control digital logic inputs immediately on power-
up without having to wait for the host CPU to initiate
control.
ApplicationsRAM-Based FPGA Bank Switching for Multiple
Profiles
Selecting Between Boot Flash
Setting ASIC Configurations/Profiles
Servers
Network Storage
Routers
Telecom Equipment
PC Peripherals
FeaturesProgrammable Replacement for Mechanical
Jumpers and SwitchesNine NV Inputs/Outputs64-Byte NV User Memory (EEPROM)I2C-Compatible Serial Interface and JTAGUp to 8 Devices can be Multidropped on the Same2C BusIEEE 1149.1 Boundary Scan CompliantOpen-Drain Outputs with Configurable PullupsOutputs Capable of Sinking 16mALow Power ConsumptionWide Operating Voltage Range: 2.7V to 5.5VOperating Temperature Range: -40°C to +85°C
DS45502C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
Pin ConfigurationTypical Operating CircuitRev 0; 9/04
Ordering InformationAdd “/T&R” for tape and reel orders.2C is a trademark of Philips Corp. Purchase of I2C componentsfrom Maxim Integrated Products, Inc., or one of its sublicensed
Associated Companies, conveys a license under the Philips I2C Patent Rights to use these components in an I2C system, provided
that the system conforms to the I2C Standard Specification as defined by Philips.
DS45502C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONSStresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on VCC, SDA, and SCL Pins
Relative to Ground.............................................-0.5V to +6.0V
Voltage on A0, A1, A2, TCK, TMS, TDI, and I/O_n [n = 0 to 8]
Relative to Ground...................................-0.5V to VCC+ 0.5V,
not to exceed +6.0V.
Operating Temperature Range...........................-40°C to +85°C
EEPROM Programming Temperature Range.........0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature.....................See IPC/JEDEC J-STD-020
Specification
DC ELECTRICAL CHARACTERISTICS
DS45502C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
AC ELECTRICAL CHARACTERISTICS-–I2C Interface (See Figure5)(VCC= +2.7V to +5.5V, TA= -40°C to +85°C, unless otherwise noted. Timing referenced to VIL(MAX)and VIH(MIN).)
AC ELECTRICAL CHARACTERISTICSJTAG Interface (See Figure1)
DS45502C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
NONVOLATILE MEMORY CHARACTERISTICS
Note 2:ISTBYis specified with SDA = SCL = TMS = TDI = VCC, outputs floating, and inputs connected to VCCor GND.
Note 3:Guaranteed by design.
Note 4:Timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard mode timing.
Note 5:After this period, the first clock pulse is generated.
Note 6:CBtotal capacitance of one bus line in picofarads.
Note 7:EEPROM write time applies to all the EEPROM memory and SRAM-shadowed EEPROM memory when SEE = 0. The
EEPROM write time begins after a stop condition occurs.
Note 8:TCK can be stopped either high or low.
Note 9:EEPROM write begins immediately after the UPDATE-DR state that latches the data to be written. The EEPROM cannot be
accessed until the EEPROM write has completed. However, the remainder of the JTAG functionality is active and accessi-
ble during the EEPROM write.
Figure1. JTAG Timing Diagram
DS45502C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
Typical Operating Characteristics(VCC= +5.0V, TA= +25°C; TDI, TDO, TMS pins are no connects, unless otherwise noted.)
DS45502C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
Pin Description
DS45502C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
Block Diagram
Detailed DescriptionThe DS4550 contains nine bidirectional, NV, input/out-
put (I/O) pins, and a 64-byte EEPROM user memory.
The I/O pins and user memory are accessible through
either the I2C compatible serial bus or the IEEE 1149.1
JTAG interface.
Programmable NV I/O PinsEach programmable I/O pin consists of an input and an
open-collector output with a selectable internal pullup
resistor. To enable the pullups for each I/O pin, write to
the Pullup Enable Registers (F0h and F1h). To pull the
output low or place the pulldown transistor into a high-
impedance state, write to the I/O Control Registers (F2h
and F3h). To read the voltage levels present on the I/O
pins, read the I/O Status Registers (F8h and F9h). To
determine the status of the output register, read the I/O
Control Registers and the Pullup Resistor Registers.
The I/O Control Registers and the Pullup Enable
Registers are all SRAM-shadowed EEPROM registers.
It is possible to disable the EEPROM writes of the regis-
ters using the SEE bit in the Configuration Register.
This reduces the time required to write to the register
and increases the amount of times the I/O pins can be
adjusted before the EEPROM is worn out.
Memory Map and Memory TypesThe DS4550 memory map is shown in Table1. Three
different types of memory are present in the DS4550:
EEPROM, SRAM-shadowed EEPROM, and SRAM.
Memory locations specified as EEPROM are NV.
Writing to these locations results in an EEPROM write
cycle for a time specified by tWRin the AC Electrical
Characteristicstable. Locations specified as SRAM-
shadowed EEPROM can be configured to operate in
one of two modes specified by the SEE bit (the LSB of
the Configuration Register, F4h). When the SEE bit = 0
(default), the memory location acts like EEPROM.
However, when SEE = 1, shadow SRAM is written to
instead of the EEPROM. This eliminates both the EEP-
ROM write time, tWR, as well as the concern of wearing
out the EEPROM. This is ideal for applications that wish
to constantly write to the I/Os. Power-up default states
can be programmed for the I/Os in EEPROM (with SEE
= 0) and then once powered up, SEE can be written to
a 1 so that the I/Os can be updated periodically in
SRAM. The final type of memory present in the DS4550
is standard SRAM.
DS45502C and JTAG Nonvolatile 9-Bit I/O
Expander Plus Memory
Table1. DS4550 Memory Map
Slave Address and Address PinsThe DS4550’s I2C slave address is determined by the
state of the A0, A1, and A2 address pins as shown in
Figure2. Address pins connected to GND result in a ‘0’
in the corresponding bit position in the slave address.
Conversely, address pins connected to VCCresult in a
‘1’ in the corresponding bit positions. I2C communica-
tion is described in detail in a later section.
IEEE 1149.1 JTAG OperationThe DS4550 contains an IEEE 1149.1 compliant JTAG
port in addition to the I2C serial bus. Either can be used
to access the internal memory. However, the device
contains no bus arbitration and hence both busses
cannot be used at the same time. All of the I/O pins on
the DS4550 are IEEE 1149.1 boundary-scan compliant.
I/O_0 to I/O_8 as well as the I2C port pins, contain the
typical JTAG boundary scan cells, which allow the pins
to be polled or forced high/low using standard JTAG
instructions. The DS4550 also contains some exten-
sions to normal JTAG functionality, which allows access
to the internal memory. In particular, the DS4550 has
three device-specific test data registers (Memory
Address, Memory Read, and Memory Write) and three
device-specific instructions (ADDRESS, READ, and
WRITE), which provide memory access.
DS45502C and JTAG Nonvolatile 9-Bit I/O
Expander Plus MemoryFigure3. DS4550 JTAG Block Diagram
Figure2. DS4550 I2C Slave Address Byte
