DS4520E+-DS4520E+TRL Fast Delivery |IC PHOENIX CO.,LIMITED

DS4520E+ ,9-Bit I²C Nonvolatile I/O Expander Plus MemoryApplications♦ Wide Operating Voltage (2.7V to 5.5V)RAM-Based FPGA Bank Switching for ♦ Operating Te ..
DS4520E+TRL ,9-Bit I²C Nonvolatile I/O Expander Plus MemoryFeaturesThe DS4520 is a 9-bit nonvolatile (NV) I/O expander with♦ Programmable Replacement for Mech ..
DS4550E ,2.7 to 5.5 V, I2C and JTAG nonvolatile 9-bit I/O expander plus memoryApplications♦ Low Power ConsumptionRAM-Based FPGA Bank Switching for MultipleProfiles♦ Wide Operati ..
DS481TM ,Low Power RS-485/RS-422 Multipoint Transceiver with Sleep Mode
DS485TMX ,Low-Power RS-485/RS-422 Multipoint Transceiver
DS485TN ,Low-Power RS-485/RS-422 Multipoint Transceiver
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DS4520E+-DS4520E+TRL
9-Bit I²C Nonvolatile I/O Expander Plus Memory
General Description
The DS4520 is a 9-bit nonvolatile (NV) I/O expander with
64 bytes of NV user memory controlled by an I2C-
compatible serial interface. The DS4520 offers users a
digitally programmable alternative to hardware jumpers
and mechanical switches that are being used to control
digital logic nodes. Furthermore, the digital state of each
pin can be read through the serial interface. Each I/O
pin is independently configurable. The outputs are open
drain with selectable pullups. Each output has the ability
to sink up to 12mA. Since the device is NV, it powers up
in the desired state allowing it to control digital logic
inputs immediately on power-up without having to wait
for the host CPU to initiate control.
Applications
RAM-Based FPGA Bank Switching for
Multiple Profiles
Selecting Between Boot Flash
Setting ASIC Configurations/Profiles
Servers
Network Storage
Routers
Telecom Equipment
PC Peripherals
FeaturesProgrammable Replacement for Mechanical
Jumpers and SwitchesNine NV Input/Output Pins64-Byte NV User Memory (EEPROM)I2C-Compatible Serial InterfaceUp to 8 Devices Can be Multidropped on the
Same I2C BusOpen-Drain Outputs with Configurable PullupsOutputs Capable of Sinking 12mALow Power ConsumptionWide Operating Voltage (2.7V to 5.5V)Operating Temperature Range: -40°C to +85°C
DS4520
9-Bit I2C Nonvolatile
I/O Expander Plus Memory
I/O_0GND
I/O_8
I/O_7
I/O_6
I/O_5
SCL
SDA
TOP VIEW
I/O_1
I/O_2
I/O_3
I/O_4
VCC
DS4520
Pin Configuration
SCL
I/O_0
I/O_1
I/O_2
I/O_3
I/O_4
I/O_5
I/O_6
I/O_7
I/O_8
SDA
GND
FROM
SYSTEM
CONTROLLER
FPGA
CLOCK
GENERATOR
CPU
SPEED
SELECT
4.7kΩ4.7kΩ
0.1μF
VCC
VCCDS4520
Typical Operating Circuit
Rev 0; 6/04
Add “/T&R” for tape and reel orders.
Ordering Information
PARTTEMP RANGEPIN-PACKAGE
DS4520E-40°C to +85°C16 TSSOP
DS4520
9-Bit I2C Nonvolatile
I/O Expander Plus Memory
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
(TA= -40°C to +85°C)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage on VCC, SDA, and SCL Pins
Relative to Ground.............................................-0.5V to +6.0V
Voltage on A0, A1, A2, and I/O_n [n = 0 to 8]
Relative to Ground....-0.5V to (VCC+ 0.5V) not to exceed +6.0V
Operating Temperature Range...........................-40°C to +85°C
EEPROM Programming Temperature Range.........0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...See IPC/JEDEC J-STD-020A Specification
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Supply VoltageVCC(Note 1)+2.7+5.5V
Input Logic 1VIH0.7 x VCCVCC + 0.3V
Input Logic 0VIL-0.30.3 x VCCV
DC ELECTRICAL CHARACTERISTICS
(VCC= +2.7V to +5.5V; TA= -40°C to +85°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
Standby CurrentISTBY(Note 2)210µA
Input LeakageIL-1.0+1.0µA
Input Current each I/O PinII/O0.4V < VI/O < 0.9VCC (Note 3)-1.0+1.0µA
3mA sink current00.4Low-Level Output Voltage (SDA)VOL SDA6mA sink current00.6V
I/O Pin Low-Level Output VoltageVOL I/O12mA sink current0.4V
I/O Pin Pullup ResistorsRPU4.05.57.5kΩ
I/O CapacitanceCI/O(Note 4)10pF
Power-On Reset VoltageVPOR1.6V
DS4520
9-Bit I2C Nonvolatile
I/O Expander Plus Memory
Note 1:All voltages referenced to ground.
Note 2:ISTBYis specified with SDA = SCL = VCC, outputs floating, and inputs connected to VCCor GND.
Note 3:The DS4520 does not obstruct the SDA and SCL lines if VCCis switched off as long as the voltages applied to these inputs
do not violate their minimum and maximum input voltage levels.
Note 4:Guaranteed by design.
Note 5:Timing shown is for fast-mode (400kHz) operation. This device is also backward compatible with I2C standard-mode timing.
Note 6:CB—total capacitance of one bus line in picofarads.
Note 7:EEPROM write time applies to all the EEPROM memory and SRAM shadowed EEPROM memory when SEE = 0. The EEPROM
write time begins after a stop condition occurs.
AC ELECTRICAL CHARACTERISTICS (See Figure 2)
(VCC= +2.7V to +5.5V; TA= -40°C to +85°C, unless otherwise noted. Timing referenced to VIL(MAX)and VIH(MIN).)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
SCL Clock FrequencyfSCL(Note 5)0400kHz
Bus Free Time Between Stop and
Start ConditionstBUF1.3µs
Hold Time (Repeated) Start
ConditiontHD:STA0.6µs
Low Period of SCLtLOW1.3µs
High Period of SCLtHIGH0.6µs
Data Hold TimetHD:DAT00.9µs
Data Setup TimetSU:DAT100ns
Start Setup timetSU:STA0.6µs
SDA and SCL Rise TimetR(Note 6)20 + 0.1CB300ns
SDA and SCL Fall TimetF(Note 6)20 + 0.1CB300ns
Stop Setup TimetSU:STO0.6µs
SDA and SCL Capacitive LoadingCB(Note 6)400pF
EEPROM Write TimetWR(Note 7)1020ms
NONVOLATILE MEMORY CHARACTERISTICS
(VCC= +2.7V to +5.5V, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
EEPROM Writes+70°C (Note 4)50,000
DS4520
9-Bit I2C Nonvolatile
I/O Expander Plus Memory
Typical Operating Characteristics
(VCC= +5.0V, TA = +25°C, unless otherwise noted.)
SUPPLY CURRENT vs. SUPPLY VOLTAGE
DS4520 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
I/O0–I/O7 CONTROL BITS = 0
I/O0–I/O7 PULLUPS DISABLED
VCC = SDA = SCL
SUPPLY CURRENT vs. TEMPERATURE
DS4520 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (6040200-20
I/O0–I/O7 CONTROL BITS = 0
I/O0–I/O7 PULLUPS DISABLED
VCC = SDA = SCL = 5V
SUPPLY CURRENT vs. SCL FREQUENCY
DS4520 toc03
SCL FREQUENCY (kHz)
SUPPLY CURRENT (
VCC = SDA = 5V
I/O OUTPUT VOLTAGE
vs. SUPPLY VOLTAGE
DS4520 toc04
SUPPLY VOLTAGE (V)
I/O VOLTAGE (V)4321
PULLUPS ENABLED
PULLDOWNS DISABLED
HIGH IMPEDANCE
EEPROM RECALL AT VPOR
DS4520
9-Bit I2C Nonvolatile
I/O Expander Plus Memory
Pin Description
PINNAMEFUNCTIONI/O_0Input/Output 0. Bidirectional I/O pin.I/O_1Input/Output 1. Bidirectional I/O pin.I/O_2Input/Output 2. Bidirectional I/O pin.I/O_3Input/Output 3. Bidirectional I/O pin.I/O_4Input/Output 4. Bidirectional I/O pin.
6A0I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device.
7A1I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device.
8VCCPower-Supply VoltageSDAI2C Serial Data Open-Drain Input/OutputSCLI2C Serial Clock InputA2I2C Address Input. Inputs A0, A1, and A2 determine the I2C slave address of the device.I/O_5Input/Output 5. Bidirectional I/O pin.I/O_6Input/Output 6. Bidirectional I/O pin.I/O_7Input/Output 7. Bidirectional I/O pin.I/O_8Input/Output 8. Bidirectional I/O pin.GNDGround
DS4520
I/O CONTROL
REGISTERS
I/O CELL (x9)
I/O_n
[n = 0 TO 8]
RPU
PULLUP ENABLE (F0h-F1h)
I/O CONTROL (F2h-F3h)
I/O STATUS (F8h-F9h)
I2C
INTERFACE
SDA
SCL
GND
EEPROM
64 BYTES
USER MEMORY
[00h TO 3Fh]
VCC
VCC
VCC
Block Diagram
DS4520
9-Bit I2C Nonvolatile
I/O Expander Plus Memory
Detailed Description
The DS4520 contains nine bidirectional, NV, input/out-
put (I/O) pins, and a 64-byte EEPROM user memory.
The I/O pins and user memory are accessible through
an I2C-compatible serial bus.
Programmable NV I/O Pins
Each programmable I/O pin consists of an input and an
open-collector output with a selectable internal pullup
resistor. To enable the pullups for each I/O pin, write to
the Pullup Enable Registers (F0h and F1h). To pull the
output low or place the pulldown transistor into a high-
impedance state, write to the I/O Control Registers (F2h
and F3h). To read the voltage levels present on the I/O
pins, read the I/O Status Registers (F8h and F9h). To
determine the status of the output register, read the I/O
Control Registers and the Pullup Resistor Registers.
The I/O Control Registers and the Pullup Enable
Registers are all SRAM shadowed EEPROM registers. It
is possible to disable the EEPROM writes of the regis-
ters using the SEE bit in the Configuration Register.
This reduces the time required to write to the register
and increases the amount of times the I/O pins can be
adjusted before the EEPROM is worn out.
Memory Map and Memory Types
The DS4520 memory map is shown in Table 1. Three
different types of memory are present in the DS4520:
EEPROM, SRAM shadowed EEPROM, and SRAM.
Memory locations specified as EEPROM are NV.
Writing to these locations results in an EEPROM write
cycle for a time specified by tWRin the AC Electrical
Characteristicstable. Locations specified as SRAM
shadowed EEPROM can be configured to operate in
one of two modes specified by the SEE bit (the LSB of
the Configuration Register, F4h). When the SEE bit = 0
(default), the memory location acts like EEPROM.
However, when SEE = 1, shadow SRAM is written to
instead of the EEPROM. This eliminates both the
EEPROM write time, tRW, as well as the concern of
wearing out the EEPROM. This is ideal for applications
that wish to constantly write to the I/Os. Power-up
default states can be programmed for the I/Os in
EEPROM (with SEE = 0) and then once powered-up,
SEE can be written to a 1 so the I/Os can be updated
periodically in SRAM. The final type of memory present
in the DS4520 is standard SRAM.
Slave Address and Address Pins
The DS4520’s slave address is determined by the state
of the A0, A1, and A2 address pins as shown in Figure 1.
Address pins connected to GND result in a ‘0’ in the cor-
responding bit position in the slave address. Conversely,
address pins connected to VCCresult in a ‘1’ in the cor-
responding bit positions. I2C communication is
described in detail in a later section.2C Serial Interface Description2C Definitions
The following terminology is commonly used to
describe I2C data transfers.
Master Device:The master device controls the slave
devices on the bus. The master device generates SCL
clock pulses, start, and stop conditions.
Slave Devices:Slave devices send and receive data
at the master’s request.
Bus Idle or Not Busy:Time between stop and start
conditions when both SDA and SCL are inactive and in
their logic-high states. When the bus is idle it often initi-
ates a low-power mode for slave devices.
Start Condition:A start condition is generated by the
master to initiate a new data transfer with a slave.
Transitioning SDA from high to low while SCL remains
high generates a start condition. See the timing dia-
gram for applicable timing.
Stop Condition:A stop condition is generated by the
master to end a data transfer with a slave. Transitioning
SDA from low to high while SCL remains high gener-
ates a stop condition. See the timing diagram for
applicable timing.
Repeated Start Condition:The master can use a
repeated start condition at the end of one data transfer
to indicate that it immediately initiates a new data trans-
fer following the current one. Repeated starts are com-
monly used during read operations to identify a specific
memory address to begin a data transfer. A repeated
start condition is issued identically to a normal start
condition. See the timing diagram for applicable timing.
Bit Write:Transitions of SDA must occur during the low
state of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
setup and hold time requirements (see Figure 2). Data is
shifted into the device during the rising edge of the SCL.

Partno	Mfg	Dc	Qty	Available	Descript
DS4520E+	MAXIM	N/a	1500	avai	9-Bit I²C Nonvolatile I/O Expander Plus Memory
DS4520E+TRL	MAXIM	N/a	1500	avai	9-Bit I²C Nonvolatile I/O Expander Plus Memory