DS4077L-0CN ,50MHz to 122.88MHz VCXOELECTRICAL CHARACTERISTICS (continued)(V = 3.135V to 3.465V, T = -40°C to +85°C, unless otherwise n ..
DS4077L-0DN ,50MHz to 122.88MHz VCXOapplications requir- LVCMOS Output Buffering low phase noise and jitter. Jitter performance of bet- ..
DS4077L-ACN ,50MHz to 122.88MHz VCXOFeaturesThe DS4077 is an integrated voltage-controlled crystal♦ 50MHz to 122.88MHz Frequencyoscilla ..
DS4077L-BCN ,50MHz to 122.88MHz VCXOBlock DiagramVDDTOP VIEWN.C. N.C. N.C.8 79X1 LVCMOSOUTPUTVC 1 6VDDCRYSTALOSCN.C. 2 5 N.C. (LVDSO-)D ..
DS4077L-BDN ,50MHz to 122.88MHz VCXOApplicationsData RetimingReference Clock Generation in Base Stationsand Wireless
DS4077L-GCN ,50MHz to 122.88MHz VCXOApplicationsOrdering InformationFREQUENCYPART TEMP RANGE OUTPUT TYPE PIN-PACKAGE TOP MARK(f ) (MHz) ..
EC2-12NU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-24 ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-24NU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-4.5NJ ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-4.5NU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
EC2-4.5TNU ,COMPACT AND LIGHTWEIGHT, SMALL MOUNTING SIZE, HIGH BREAKDOWN VOLTAGE
DS4077-DS4077L-0CN-DS4077L-0DN-DS4077L-ACN-DS4077L-BCN-DS4077L-BDN-DS4077L-GCN-DS4077L-GDN
50MHz to 122.88MHz VCXO
General DescriptionThe DS4077 is an integrated voltage-controlled crystal
oscillator (VCXO) module designed to provide reference
clock generation in base stations, telecom/datacom, and
wireless applications. The DS4077 is developed using a
fundamental quartz crystal plus a unique integrated cir-
cuit design. The internal fundamental quartz crystal
determines the frequency of operation. Custom frequen-
cies are available. Contact the factory for availability.
The DS4077 is designed for use with applications requir-
ing low phase noise and jitter. Jitter performance of bet-
ter than 0.8ps RMS is achieved over the 12kHz to 20MHz
range. Phase noise performance of better than
-125dBc/Hz at 1kHz is achieved with this design.
Features50MHz to 122.88MHz Frequency3.135V to 3.465V OperationLow Jitter: < 0.8ps RMS±69ppm Absolute Pull Range (APR)Output Options:
LVCMOS Output Buffer
LVDS Complementary Output BufferMinimum ±110ppm Tuning Range (+25°C)14mm x 9mm x 3.06mm Plastic LGA Package
DS4077
50MHz to 122.88MHz VCXON.C.
N.C.N.C.N.C.
LVCMOS (LVDSO+)VSS87
6VDDN.C. (LVDSO-)
( ) LVDS OPTION
TRANSFER-MOLDED PLASTIC PACKAGE
LGATOP VIEW
DS4077
Pin Configuration
ApplicationsRev 3; 9/06
Ordering Information
PARTTEMP RANGEOUTPUT TYPEFREQUENCY
(fNOM) (MHz)PIN-PACKAGETOP MARKDS4077L-DCN-40°C to +85°CLVCMOS549 LGADS4077L-DCN
DS4077L-DDN-40°C to +85°CLVDS549 LGADS4077L-DDN
DS4077L-CCN-40°C to +85°CLVCMOS61.449 LGADS4077L-CCN
DS4077L-CDN-40°C to +85°CLVDS61.449 LGADS4077L-CDN
Ordering Information continued at end of data sheet.Clock-Data Recovery in Telecom/Datacom
Applications
Data Retiming
Reference Clock Generation in Base Stations
and Wireless Applications
Block DiagramVDD
LVCMOS
OUTPUT
VARACTOR
OSC
CONTROL
LVCMOS OPTION SHOWN HERE.
CRYSTAL
DS4077
DS4077
50MHz to 122.88MHz VCXO
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(VDD= 3.135V to 3.465V, TA= -40°C to +85°C, unless otherwise noted.) (Typical values at +25°C, VDD= 3.3V, unless otherwise
noted.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VC, VDD, LVCMOS, LVDSO+, LVDSO- Output........-0.3V, +3.6V
Operating Temperature Range
(noncondensing)..............................................-40°C to +85°C
Junction Temperature......................................................+150°C
Thermal Resistance
Junction to Ambient.................................................91.06°C/W
Junction to Case......................................................44.51°C/W
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature
(reflow, 2 passes max)....See IPC/JEDEC STD-020 Specification
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVDD Operating Supply RangeVDD3.1353.33.465V
fOUT ≤ 106.25MHz2030
VDD Supply CurrentIDDOutput open
fOUT > 106.25MHz2535
FrequencyfOUTVC = 1.6V, VDD = 3.3V, TA = +25°C
(Note 2)
fNOM
–8ppmfNOMfNOM
+8ppmMHz
Frequency vs. VDD SensitivityVDDppmVDD = 3.3V ±5%-3.5+11.5ppm
Frequency vs. Load SensitivityLOADpmm10pF to 20pF (Note 3)-1ppm/pF
Frequency vs. TemperatureTEMPppmFrom +25°C-20+20ppm
VC Voltage RangeVCRANGE0.31.602.8V
Frequency Tuning SensitivityVCSEN41164ppm/V
Tuning Voltage BandwidthVCBW(Note 3)10kHz
Absolute Pull RangefTUNEVC = 0.3V to 2.8V (Note 2)-69+69ppm
VC Input LeakageILCVVC = 0V to VDD-500+500nA
Aging, First YearAGEppm-5+5ppm
Aging, Years 0–10tAGETotal aging-10+10ppm
LVDS OUTPUTOutput High VoltageVOHLVDSO(Note 4)1.475V
Output Low VoltageVOLLVDSO(Note 4)0.925V
Differential Output VoltageVODLVDSO(Note 4)250400mV
Output Common-Mode VariationVLVDSOCOM(Note 4)150mV
Offset Output VoltageVOFFLVDSO(Note 4)1.1251.275V
Differential Output ImpedeanceROLVDSO(Note 3)80140Ω
Output CurrentIVSSLVDSOShort ground40mA
Output CurrentILVDSOShort together (Note 3)12mA
Output Rise Time (Differential)tRLVDSO20% to 80% (Note 3)150ps
Output Fall Time (Differential)tFLVDSO80% to 20% (Note 3)150ps
DS4077
50MHz to 122.88MHz VCXO
ELECTRICAL CHARACTERISTICS (continued)(VDD= 3.135V to 3.465V, TA= -40°C to +85°C, unless otherwise noted.) (Typical values at +25°C, VDD= 3.3V, unless otherwise
noted.) (Note 1)
Note 1:Limits at -40°C are guaranteed by design and not production tested.
Note 2:10pF, LVCMOS.
Note 3:Guaranteed by design and not production tested.
Note 4:100Ωdifferential load.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
LVCMOS OUTPUTOutput Logic 0VOLOutput Current -450µA00.4V
Output Logic 1VOHOutput Current +450µAVDD -
0.8VVDDV
Output Rise TimetRLoad condition: 10pF to ground; 10% to
90% VDD (Note 3)2ns
Output Fall TimetFLoad condition: 10pF to ground; 90% to
10% VDD (Note 3)2ns
Duty CycleDCYCLoad condition: 10pF, VDD / 2 (Note 3)4060%
HarmonicsHVDD = 3.3V, TA = +25°C (Note 3)-18-8dBc/Hz
SSB PHASE NOISE AND JITTER, VDD = 3.3, TA = +25°C (Note 3)10Hz Offset-70
100Hz Offset-100
1kHz Offset-125
10kHz Offset-145
100kHz Offset
LVCMOS
dBc/Hz
Jitter (12kHz to 20MHz)0.8psRMS
Pin Description
PIN
LVCMOSLVDSNAMEFUNCTION1VCVCXO Control Voltage
2, 5, 7, 8, 92, 7, 8, 9N.C.No Connection3VSSGround—LVCMOSLVCMOS Output6VDDDC Power4, 5LVDSO+/LVDSO-LVDS Positive and Negative Outputs
DS4077
50MHz to 122.88MHz VCXO
Typical Operating Characteristics(VCC= +3.3V, TA= +25°C, unless otherwise noted.)
FREQUENCY vs. TEMPERATUREDS4077 toc01
TEMPERATURE (°C)
fOUT
DEVIATION (ppm)40200-20
fOUT = 77.76MHz
VC = 1.55V
LVCMOS OUTPUT FREQUENCY
vs. LOAD CAPACITANCE vs. VCDS4077 toc02
VC (V)
fOUT
DEVIATION (ppm)
CL = 0pF
CL = 20pF
fOUT = 77.76MHz
OUTPUT FREQUENCY
vs. SUPPLY VOLTAGE vs. VCDS4077 toc03
VDD (V)
fOUT
DEVIATION FROM V
= 3.3V (ppm)
fOUT = 77.76MHz
TA = +25°C
VC = 0.3V
VC = 2.8V
VC = 1.6V
DS4077
50MHz to 122.88MHz VCXOMaxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are
Ordering Information (continued)
PARTTEMP RANGEOUTPUT TYPEFREQUENCY
(fNOM) (MHz)PIN-PACKAGETOP MARKDS4077L-ECN-40°C to +85°CLVCMOS74.175829 LGADS4077L-ECN
DS4077L-EDN-40°C to +85°CLVDS74.175829 LGADS4077L-EDN
DS4077L-FCN-40°C to +85°CLVCMOS74.259 LGADS4077L-FCN
DS4077L-FDN-40°C to +85°CLVDS74.259 LGADS4077L-FDN
DS4077L-ACN-40°C to +85°CLVCMOS76.89 LGADS4077L-ACN
DS4077L-ADN-40°C to +85°CLVDS76.89 LGADS4077L-ADN
DS4077L-0CN-40°C to +85°CLVCMOS77.769 LGADS4077L-0CN
DS4077L-0DN-40°C to +85°CLVDS77.769 LGADS4077L-0DN
DS4077L-GCN-40°C to +85°CLVCMOS106.259 LGADS4077L-GCN
DS4077L-GDN-40°C to +85°CLVDS106.259 LGADS4077L-GDN
DS4077L-BDN-40°C to +85°CLVDS122.889 LGADS4077L-BDN
Revision HistoryRev 0;8/05:Initial release.
Rev 1;12/05:Added LVDS option.
Rev 2;6/06:Changed device description/frequency range; changed jitter typical value from 1 to 0.8psRMS;
added new parts numbers to Ordering Information table; changed jitter range upper limits from
80MHz to 20MHz.
Rev 3;9/06:Changed VDDppm units from ppm/PF to ppm; added separate IDDparameter for parts with fOUT
greater than 106.25MHz.
PACKAGE TYPEPACKAGE CODEDOCUMENT NO.9 LGAL949A-1
21-0265
Package InformationFor the latest package outline information and land patterns, go to /packages.
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