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DS3502U+-DS3502U+T&R/C
High-Voltage NV I²C Potentiometer
DS3502
High-Voltage, NV, I2C POTRev 1; 3/09
General DescriptionThe DS3502 is a 7-bit, nonvolatile (NV) digital poten-
tiometer (POT) featuring an output voltage range of up to
15.5V. Programming is accomplished by an I2C-compat-
ible interface, which can operate at speeds of up to
400kHz. External voltages are applied at the RL and RH
inputs to define the lowest and highest potentiometer
outputs.
ApplicationsTFT-LCD VCOMCalibration
Instrumentation and Industrial Controls
Mechanical POT Replacement
Features128 Wiper Tap Points Full-Scale Resistance: 10kΩI2C-Compatible Serial InterfaceAddress Pins Allow Up to Four DS3502s to Share
the Same I2C BusDigital Operating Voltage: 2.5V to 5.5VAnalog Operating Voltage: 4.5V to 15.5VOperating Temperature: -40°C to +100°C10-Pin µSOP Package+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
Ordering Information
PARTTEMP RANGEPIN-PACKAGE DS3502U+ -40°C to +100°C 10 μSOP
DS3502U+T&R -40°C to +100°C 10 μSOP
7-BIT
WIPER REGISTER
7-BIT
NONVOLATILE MEMORY
CONTROL CIRCUITRY
AND
ADDRESS DECODEA1
DECODER
LEVEL SHIFTER
SDA
SCL
DS3502
Functional Diagram
Pin Configuration and Typical Operating Circuit appear at
end of data sheet.
DS3502
High-Voltage, NV, I2C POT
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS(TA= -40°C to +100°C)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on VCCRelative to GND...............-0.5V to +6.0V
Voltage Range on V+ Relative to GND..................-0.5V to +17V
Voltage Range on SDA, SCL, A0, A1
Relative to GND.......-0.5V to (VCC+ 0.5V), not to exceed 6.0V
Voltage Range on RH, RL, RW...................................-0.5V to V+
Voltage Range Across RH and RL Pins.....................-0.5V to V+
Operating Temperature Range.........................-40°C to +100°C
Programming Temperature Range.........................0°C to +70°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
Maximum RW Current...........................................................1mA
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS Supply Voltage VCC (Note 1) +2.5 +5.5 V
V+ Voltage V+ V+ > VCC +4.5 +15.5 V
Input Logic 1
(SCL, SDA, A0, A1) VIH0.7 x
VCC
VCC
+ 0.3 V
Input Logic 0
(SCL, SDA, A0, A1) VIL -0.3 0.3 x
VCCV
Resistor Inputs (RL, RW, RH) VRES -0.3 +15.5 V
Wiper Current IWIPER 1 mA
ELECTRICAL CHARACTERISTICS(VCC= +2.5V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSVCC Supply Current ICC (Note 2) 0.2 3 mA
Standby Supply Current ISTBY (Note 3) 10 μA
V+ Bias Current IV+ +1 μA
Input Leakage (SDA, SCL, A0, A1) IL -1 +1 μA
Wiper Response Time tWRS 1 μs
Low-Level Output Voltage (SDA) VOL 3mA sink current 0.0 0.4 V
I/O Capacitance CI/O 5 10 pF
Power-Up Recall Voltage VPOR (Note 4) 1.2 2.4 V
Power-Up Memory Recall Delay tD (Note 5) 3 ms
Wiper Resistance RW V+ = 15.0V 5000
End-to-End Resistance (RH to RL) RTOTAL 10 k
RTOTAL Tolerance TA= +25°C -20 +20 %
CH, CL, CW Capacitance CPOT 10 pF
DS3502
High-Voltage, NV, I2C POT
VOLTAGE-DIVIDER CHARACTERISTICS(VCC= +2.5V to +5.5V, TA= -40°C to +100°C, unless otherwise noted.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSIntegral Nonlinearity INL (Note 6) -1 +1 LSB
Differential Nonlinearity DNL (Note 7) -0.5 +0.5 LSB
Zero-Scale Error ZSERROR V+ = 4.5V (Note 8) 0 0.5 2 LSB
Full-Scale Error FSERROR V+ = 4.5V (Note 9) -2 -1 0 LSB
Ratiometric Temp Coefficient TCV WR/IVR register set to 40h ±4 ppm/°C
I2C AC ELECTRICAL CHARACTERISTICS(VCC= +2.5V to +5.5V, TA= -40°C to +100°C, timing referenced to VIL(MAX)and VIH(MIN). See Figure 2.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS SCL Clock Frequency fSCL (Note 10) 0 400 kHz
Bus Free Time Between STOP
and START Conditions tBUF 1.3 μs
Hold Time (Repeated) START
Condition tHD:STA 0.6 μs
Low Period of SCL tLOW 1.3 μs
High Period of SCL tHIGH 0.6 μs
Data Hold Time tHD:DAT 0 0.9 μs
Data Setup Time tSU:DAT 100 ns
START Setup Time tSU:STA 0.6 μs
SDA and SCL Rise Time tR (Note 11) 20 +
0.1CB 300 ns
SDA and SCL Fall Time tF (Note 11) 20 +
0.1CB 300 ns
STOP Setup Time tSU:STO 0.6 μs
SDA and SCL Capacitive
Loading CB (Note 11) 400 pF
EEPROM Write Time tW (Note 12) 10 20 ms
Pulse-Width Suppression Time at
SDA and SCL Inputs tIN (Note 13) 50 ns
A0, A1 Setup Time tSU:A Before START 0.6 μs
A0, A1 Hold Time tHD:A After STOP 0.6 μs
SDA and SCL Input Buffer
Hysteresis 0.05 x
VCC V
DS3502
High-Voltage, NV, I2C POT
NONVOLATILE MEMORY CHARACTERISTICS(VCC= +2.5V to +5.5V)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSTA = +70°C50,000EEPROM Write CyclesTA = +25°C200,000Writes
Note 1:All voltages are referenced to ground. Currents entering the IC are specified positive and currents exiting the IC are negative.
Note 2:ICCis specified with the following conditions: SCL = 400kHz, SDA pulled up, and RL, RW, RH floating.
Note 3:ISTBYis specified with SDA = SCL = VCC= 5.5V and resistor pins floating.
Note 4:This is the minimum VCCvoltage that causes NV memory to be recalled.
Note 5:This is the time from VCC> VPORuntil initial memory recall is complete.
Note 6:Integral nonlinearity is the deviation of a measured resistor setting value from the expected values at each particular resis-
tor setting. Expected value is calculated by connecting a straight line from the measured minimum setting to the mea-
sured maximum setting. INL = [V(RW)i- (V(RW)0]/LSB(ideal) - i, for i = 0...127.
Note 7:Differential nonlinearity is the deviation of the step-size change between two LSB settings from the expected step size.
The expected LSB step size is the slope of the straight line from measured minimum position to measured maximum posi-
tion. DNL = [V(RW)i+1- (V(RW)i]/LSB(ideal) - 1, for i = 0...126.
Note 8:ZS error = code 0 wiper voltage divided by one LSB (ideal).
Note 9:FS error = (code 127 wiper voltage - V+) divided by one LSB (ideal).
Note 10:I2C interface timing shown is for fast-mode (400kHz) operation. This device is also backward-compatible with I2C standard
mode timing.
Note 11:CB—total capacitance of one bus line in picofarads.
Note 12:EEPROM write time begins after a STOPcondition occurs.
Note 13:Pulses narrower than max are suppressed.
DS3502
High-Voltage, NV, I2C POT
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
Pin Description
NAMEPINFUNCTION SDA 1 I2C Serial Data. Input/output for I2C data.
GND 2 Ground Terminal
VCC 3 Supply Voltage Terminal
A1, A0 4, 5 Address Select Inputs. Determines I2C slave address. Slave address is 01010A1A0X. (See the
Slave Address Byte and Address Pins section for details).
RH 6 High Terminal of Potentiometer
RW 7 Wiper Terminal of Potentiometer
RL 8 Low Terminal of Potentiometer
V+ 9 Wiper Bias Voltage
SCL 10 I2C Serial Clock. Input for I2C clock.
SUPPLY CURRENT
vs. SUPPLY VOLTAGEDS3502 toc01
SUPPLY VOLTAGE (V)
SUPPLY CURRENT (
SDA = SCL = VCC, V+ = 15.5V
RW, RH, AND RL ARE FLOATING
SUPPLY CURRENT
vs. TEMPERATUREDS3502 toc02
TEMPERATURE (°C)
SUPPLY CURRENT (6040200-20
SDA = SCL = VCC = 5V, V+ = 15.5V
RW, RH, AND RL ARE FLOATING
INTEGRAL NONLINEARITY
vs. POTENTIOMETER SETTINGDS3502 toc03
POTENTIOMETER SETTING (DEC)
INTEGRAL NONLINEARITY (LSB)
DIFFERENTIAL NONLINEARITY
vs. POTENTIOMETER SETTING
DS3502 toc04
POTENTIOMETER SETTING (DEC)
DIFFERENTIAL NONLINEARITY (LSB)
-0.5
DS3502
High-Voltage, NV, I2C POTI2C
INTERFACE
WIPER
REGISTER/
INITIAL VALUE
REGISTER
(WR/IVR)
00h
VCC
SDA
CONTROL
LOGIC/
REGISTER
(02h)
POS 7Fh
POS 00h
GND
SCL
MODE BIT
DS3502
Simplified Functional Diagram
Detailed DescriptionThe DS3502 contains a single potentiometer whose
wiper position is controlled by the value in the Wiper
Register (WR). The initial power-up value of the wiper
position is set by programming the Initial Value Register
(IVR). On power-up, the data stored in the IVR register
is loaded into the WR register, which sets the position
of the potentiometer’s wiper.
Control RegisterThe Control Register (CR) located in register 02h con-
tains the WR/IVR Address Mode bit (MODE bit). The
MODE bit determines how I2C data is written to the WR
and IVR data register as follows:
MODE = 0:I2C writes to memory address 00h write to
(CR = 00h)both WR and IVR.2C reads from address 00h read from WR.
MODE = 1:I2C writes to memory address 00h write to
(CR = 80h)WR.
I2C reads from address 00h read from WR.
Regardless of the setting of the MODE bit, all I2C reads
of address 00h return the contents of the WR register.
Setting MODE = 1 allows for quick writing of SRAM
without the added delay of writing to the associated
EEPROM register. The data that is stored in EEPROM
and SRAM remains unchanged if the MODE bit is tog-
gled.The volatile CR register powers up as 00h, set-
ting the device into MODE = 0.
Digital Potentiometer OutputThe potentiometer consists of 127 resistors in series
connected between the RH and RL pins. Between each
resistance and at the two endpoints, RH and RL, solid-
state switches enable RW to be connected within the
resistive network. The wiper position and the output on
RW are decoded based on the value in WR. If RH, RL,
and RW are externally connected in a voltage-divider
configuration, then the voltage on RW can be easily
calculated using the following equation:
where WR is the wiper position in decimal (0–127).WRVVRWRLRHRL=+−127()
Table 1. Memory Map
REGISTER NAME ADDRESS
(HEX)
FACTORY/POWER-UP DEFAULT
(HEX) WR/IVR Wiper Register/Initial Value Register 00 40
CR Control Register 02 00 (Mode 0)
