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DS34C86TM-DS34C86TMX-DS34C86TN
Quad CMOS Differential Line Receiver
DS34C86T
Quad CMOS Differential Line Receiver
General DescriptionThe DS34C86Tisa quad differential line receiver designed meetthe RS-422, RS-423, and Federal Standards 1020
and 1030for balanced and unbalanced digital data transmis-
sion, while retainingthelow power characteristicsof CMOS.
The DS34C86T hasan input sensitivityof 200 mV over the
common mode input voltage rangeof ±7V. Hysteresisis
providedto improve noise margin and discourage output
instabilityfor slowly changing input waveforms.
The DS34C86T features internal pull-up and pull-downre-
sistors which prevent output oscillationon unused channels.
Separate enable pins allow independent controlof receiver
pairs. The TRI-STATE® outputs have6 mA source and sink
capability. The DS34C86Tis pin compatible with the
DS3486.
Features CMOS designfor low power ±0.2V sensitivity overthe input common mode voltage
range Typical propagation delays:19ns Typical input hysteresis:60 mV Inputs won’t load line when VCC =0V Meetsthe requirementsof EIA standard RS-422 TRI-STATE outputsfor system bus compatibility Availablein surface mount Open input Failsafe feature, output highfor open input
Logic DiagramConnection Diagram
Dual-In-Line Package
Top View
Order Number DS34C86TM, and DS34C86TN
SeeNS Package Number M16A and N16E
Truth Table
Enable Input Output Z
HVID≥ VTH (Max) H
HVID≤ VTH (Min) L Open* H
*Open,not terminated= TRI-STATE
June 1998
DS34C86T
Quad
CMOS
Differential
Line
Receiver