DS33Z44 ,Quad Ethernet MapperFEATURES The DS33Z44 extends four 10/100 Ethernet LAN Four 10/100 IEEE 802.3 Ethernet MACs (MII ..
DS33Z44 ,Quad Ethernet MapperFeatures Continued on Page 10. DS33Z44 4 SERIAL TRANSCEIVERS/ ORDERING INFORMATION SERIAL DRI ..
DS33Z44+ ,Quad Ethernet MapperFEATURES The DS33Z44 extends four 10/100 Ethernet LAN Four 10/100 IEEE 802.3 Ethernet MACs (MII s ..
DS33Z44+ ,Quad Ethernet MapperTABLE OF CONTENTS 1 DESCRIPTION........8 2 FEATURE HIGHLIGHTS .9 2.1 GENERAL ........9 2.2 SERIAL I ..
DS33Z44DK ,Ethernet Transport Design KitGENERAL DESCRIPTION Demonstrates Key Functions of DS33Z44 The DS33Z44 design kit is an easy-to-use ..
DS3486M ,Quad RS-422/RS-423 Line ReceiverFeaturesn Four independent receiversNational’squadRS-422,RS-423receiver
EB2-12 ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEFEATURESª Compact and lightweight : 7.5 mm · 14.3 mm · 9.3 mm, 1.5 gª 2 form c contact arrangementª ..
EB2-12NU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
EB2-12TNU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
DS33Z44
Quad Ethernet Mapper
GENERAL DESCRIPTION The DS33Z44 extends four 10/100 Ethernet LAN
segments by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over four PDH/TDM data streams. The serial links support bidirectional
synchronous interconnect up to 52Mbps over xDSL, T1/E1/J1, T3/E3, V.35/Optical, OC-1/EC-1, or
SONET/SDH Tributary.
The device performs store-and-forward of packets with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) controllers provide fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33Z44 can operate with an inexpensive external processor, EEPROM or in a stand-alone hardware mode.
APPLICATIONS Transparent LAN Service
LAN Extension Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4
FUNCTIONAL DIAGRAM
FEATURES Four 10/100 IEEE 802.3 Ethernet MACs (MII and
RMII) Half/Full Duplex with Automatic Flow Control Four 52Mbps Synchronous TDM Serial Ports
with independent transmit and receive timing. HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill Committed Information Rate Controllers Provide Fractional Allocations in 512kbps Increments Programmable BERT for Serial (TDM) Interfaces External 16MB, 100MHz SDRAM Buffering Parallel Microprocessor Interface SPI Interface and Hardware Mode for Operation
Without a Host Processor 1.8V Operation with 3.3V Tolerant I/O IEEE 1149.1 JTAG Support
Features Continued on Page 10.
ORDERING INFORMATION Go to /telecom for a complete list of
Telecommunications data sheets, evaluation kits, application
notes, and software downloads.
DS33Z44
Quad Ethernet Mapper
DS33Z44 Quad Ethernet Mapper
DOCUMENT REVISION HISTORY DS33Z44 Quad Ethernet Mapper
TABLE OF CONTENTS DESCRIPTION....................................................................................................................9 FEATURE HIGHLIGHTS...................................................................................................10 2.1 GENERAL.................................................................................................................................10
2.2 SERIAL INTERFACES.................................................................................................................10
2.3 HDLC......................................................................................................................................10 2.4 COMMITTED INFORMATION RATE (CIR) CONTROLLERS...............................................................10
2.5 X.86 SUPPORT.........................................................................................................................10
2.6 SDRAM INTERFACE.................................................................................................................11
2.7 MAC INTERFACES....................................................................................................................11 2.8 MICROPROCESSOR INTERFACE.................................................................................................11
2.9 SERIAL SPI INTERFACEMASTER MODE ONLY.........................................................................11
2.10 DEFAULT CONFIGURATIONS......................................................................................................11
2.11 TEST AND DIAGNOSTICS...........................................................................................................11 2.12 SPECIFICATIONS COMPLIANCE...................................................................................................12
APPLICATIONS................................................................................................................13 ACRONYMS AND GLOSSARY........................................................................................16 MAJOR OPERATING MODES.........................................................................................17 BLOCK DIAGRAMS.........................................................................................................18 PIN DESCRIPTIONS.........................................................................................................19 7.1 PIN FUNCTIONAL DESCRIPTION.................................................................................................19
FUNCTIONAL DESCRIPTION..........................................................................................30 8.1 PROCESSOR INTERFACE....................................................................................................30
8.1.1 Read-Write/Data Strobe Modes..........................................................................................................31 8.1.2 Clear On Read....................................................................................................................................31
8.1.3 Interrupt and Pin Modes......................................................................................................................31 8.2 SPI SERIAL EEPROM INTERFACE.......................................................................................31
8.3 CLOCK STRUCTURE............................................................................................................32
8.3.1 Serial Interface Clock Modes..............................................................................................................34 8.3.2 Ethernet Interface Clock Modes..........................................................................................................34
8.4 RESETS AND LOW-POWER MODES...................................................................................35
8.5 INITIALIZATION AND CONFIGURATION..............................................................................36 8.6 GLOBAL RESOURCES..........................................................................................................36
8.7 PER-PORT RESOURCES......................................................................................................36
8.8 DEVICE INTERRUPTS...........................................................................................................37 8.9 SERIAL INTERFACES...........................................................................................................39
8.10 CONNECTIONS AND QUEUES.............................................................................................39
8.11 ARBITER................................................................................................................................42
8.12 FLOW CONTROL...................................................................................................................42 8.12.1 Full Duplex Flow control......................................................................................................................43
8.12.2 Half Duplex Flow control.....................................................................................................................44 8.12.3 Host-Managed Flow control................................................................................................................44
8.13 ETHERNET INTERFACES.....................................................................................................45
8.13.1 DTE and DCE Mode...........................................................................................................................47 8.14 ETHERNET MAC...................................................................................................................48
8.14.1 MII Mode Options................................................................................................................................50 8.14.2 RMII Mode...........................................................................................................................................50
DS33Z44 Quad Ethernet Mapper
8.15 BERT......................................................................................................................................53
8.15.1 Receive Data Interface........................................................................................................................53 8.15.2 Repetitive Pattern Synchronization.....................................................................................................54
8.15.3 Pattern Monitoring...............................................................................................................................55 8.15.4 Pattern Generation..............................................................................................................................55
8.16 SERIAL INTERFACES...........................................................................................................56
8.17 TRANSMIT PACKET PROCESSOR.......................................................................................56 8.18 RECEIVE PACKET PROCESSOR.........................................................................................57
8.19 X.86 ENCODING AND DECODING.......................................................................................59
8.20 COMMITTED INFORMATION RATE CONTROLLER.............................................................62 8.21 HARDWARE MODE...............................................................................................................64
DEVICE REGISTERS.......................................................................................................68 9.1 REGISTER BIT MAPS.................................................................................................................69
9.1.1 Global Register Bit Map......................................................................................................................69
9.1.2 Arbiter Register Bit Map......................................................................................................................70 9.1.3 BERT Register Bit Map.......................................................................................................................70
9.1.4 Serial Interface Register Bit Map........................................................................................................71 9.1.5 Ethernet Interface Register Bit Map....................................................................................................73
9.1.6 MAC Register Bit Map.........................................................................................................................74 9.2 GLOBAL REGISTER DEFINITIONS................................................................................................76
9.3 ARBITER REGISTERS................................................................................................................90
9.3.1 Arbiter Register Bit Descriptions.........................................................................................................90 9.4 BERT REGISTERS....................................................................................................................93
9.5 SERIAL INTERFACE REGISTERS...............................................................................................100
9.5.1 Serial Interface Transmit and Common Registers............................................................................100 9.5.2 Serial Interface Transmit Register Bit Descriptions..........................................................................100
9.5.3 Transmit HDLC Processor Registers................................................................................................101 9.5.4 X.86 Registers...................................................................................................................................107
9.5.5 Receive Serial Interface....................................................................................................................109 9.6 ETHERNET INTERFACE REGISTERS..........................................................................................122
9.6.1 Ethernet Interface Register Bit Descriptions.....................................................................................122 9.6.2 MAC Registers..................................................................................................................................134
10 FUNCTIONAL TIMING....................................................................................................151 10.1 FUNCTIONAL SERIAL I/O TIMING..............................................................................................151
10.2 MII AND RMII INTERFACES......................................................................................................152
10.3 SPI INTERFACE MODE AND EEPROM PROGRAM SEQUENCE....................................................154
11 OPERATING PARAMETERS.........................................................................................157 11.1 MII INTERFACE.......................................................................................................................160 11.2 RMII INTERFACE....................................................................................................................162
11.3 MDIO INTERFACE...................................................................................................................164
11.4 TRANSMIT WAN INTERFACE...................................................................................................165
11.5 RECEIVE WAN INTERFACE.....................................................................................................166 11.6 SDRAM TIMING.....................................................................................................................167
11.7 MICROPROCESSOR BUS AC CHARACTERISTICS.......................................................................169
11.8 EEPROM INTERFACE TIMING.................................................................................................172 11.9 JTAG INTERFACE TIMING.......................................................................................................173
12 JTAG INFORMATION.....................................................................................................174 12.1 JTAG/TAP CONTROLLER STATE MACHINE DESCRIPTION.........................................................175
12.2 INSTRUCTION REGISTER.........................................................................................................177
12.2.1 SAMPLE:PRELOAD.........................................................................................................................178 12.2.2 BYPASS............................................................................................................................................178
DS33Z44 Quad Ethernet Mapper
12.2.5 HIGHZ...............................................................................................................................................178 12.2.6 IDCODE............................................................................................................................................178
12.3 JTAG ID CODES....................................................................................................................179
12.4 TEST REGISTERS....................................................................................................................179
12.5 BOUNDARY SCAN REGISTER...................................................................................................179 12.6 BYPASS REGISTER.................................................................................................................179
12.7 IDENTIFICATION REGISTER......................................................................................................179
12.8 JTAG FUNCTIONAL TIMING.....................................................................................................180
13 PACKAGE INFORMATION.............................................................................................181 13.1 17MM X 17MM 256-CSBGA....................................................................................................181
