DS33Z11 ,Ethernet MapperFEATURES 10/100 IEEE 802.3 Ethernet MAC (MII and RMII) The DS33Z11 extends a 10/100 Ethernet LAN ..
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DS33Z44 ,Quad Ethernet MapperFeatures Continued on Page 10. DS33Z44 4 SERIAL TRANSCEIVERS/ ORDERING INFORMATION SERIAL DRI ..
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DS33Z44+ ,Quad Ethernet MapperTABLE OF CONTENTS 1 DESCRIPTION........8 2 FEATURE HIGHLIGHTS .9 2.1 GENERAL ........9 2.2 SERIAL I ..
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DS33Z11
Ethernet Mapper
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device may be simultaneously available through various sales channels. For information about device errata, click here: /errata.
GENERAL DESCRIPTION The DS33Z11 extends a 10/100 Ethernet LAN segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over a PDH/TDM data stream. The serial link supports bidirectional-synchronous interconnect up to 52Mbps over xDSL,
T1/E1/J1, T3/E3, V.35/Optical, OC-1/EC-1, or SONET/SDH Tributary. The device performs store-and-forward of packets with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) controller provides fractional bandwidth allocation up to the line
rate in increments of 512kbps. The DS33Z11 can operate with an inexpensive external processor, EEPROM or in a stand-alone hardware mode.
FUNCTIONAL DIAGRAM
FEATURES ��10/100 IEEE 802.3 Ethernet MAC (MII and RMII)
Half/Full Duplex with Automatic Flow Control
��52Mbps Synchronous TDM Serial Port with
Independent Transmit and Receive Timing
��HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill
��Committed Information Rate Controller Provides Fractional Allocations in 512kbps Increments
��Programmable BERT for Serial (TDM) Interface
��External 16MB, 100MHz SDRAM Buffering
��Parallel Microprocessor Interface
��SPI Interface and Hardware Mode for Operation Without a Host Processor
��Also Available in a 100-Ball, 10mm CSBGAthe Hardware/SPI Mode-Only DS33ZH11
��1.8V Operation with 3.3V Tolerant I/O
��IEEE 1149.1 JTAG Support
Feature Highlights continued on page 8.
APPLICATIONS Transparent LAN Service
LAN Extension Ethernet Delivery Over T1/E1/J1, T3/E3, OC-1/EC-1, G.SHDSL, or HDSL2/4
ORDERING INFORMATION
DS33Z11
Ethernet Mapper
DS33Z11 Ethernet Mapper
TABLE OF CONTENTS DESCRIPTION..............................................................................................................................7 FEATURE HIGHLIGHTS...............................................................................................................8 2.1 GENERAL.......................................................................................................................................................8 2.2 SERIAL INTERFACE.........................................................................................................................................8
2.3 HDLC...........................................................................................................................................................8 2.4 COMMITTED INFORMATION RATE (CIR) CONTROLLER......................................................................................8 2.5 X.86 SUPPORT..............................................................................................................................................8
2.6 SDRAM INTERFACE.......................................................................................................................................9 2.7 MAC INTERFACE............................................................................................................................................9
2.8 MICROPROCESSOR INTERFACE.......................................................................................................................9 2.9 SERIAL SPI INTERFACEMASTER MODE ONLY..............................................................................................9 2.10 DEFAULT CONFIGURATIONS............................................................................................................................9
2.11 TEST AND DIAGNOSTICS.................................................................................................................................9 2.12 SPECIFICATIONS COMPLIANCE......................................................................................................................10
APPLICATIONS...........................................................................................................................11 ACRONYMS AND GLOSSARY...................................................................................................14 MAJOR OPERATING MODES....................................................................................................15 BLOCK DIAGRAMS....................................................................................................................16 PIN DESCRIPTIONS...................................................................................................................17 7.1 PIN FUNCTIONAL DESCRIPTION.....................................................................................................................17
FUNCTIONAL DESCRIPTION.....................................................................................................29 8.1 PROCESSOR INTERFACE...............................................................................................................................29
8.1.1 Read-Write/Data Strobe Modes..........................................................................................................30 8.1.2 Clear on Read.....................................................................................................................................30
8.1.3 Interrupt and Pin Modes......................................................................................................................30 8.2 SPI SERIAL EEPROM INTERFACE................................................................................................................30 8.3 CLOCK STRUCTURE...............................................................................................................................31
8.3.1 Serial Interface Clock Modes..............................................................................................................33 8.3.2 Ethernet Interface Clock Modes..........................................................................................................33
8.4 RESETS AND LOW POWER MODES...............................................................................................................34 8.5 INITIALIZATION AND CONFIGURATION.............................................................................................................35
8.6 GLOBAL RESOURCES...................................................................................................................................35 8.7 PER-PORT RESOURCES...............................................................................................................................35
8.8 DEVICE INTERRUPTS....................................................................................................................................36 8.9 SERIAL INTERFACE.......................................................................................................................................38 8.10 CONNECTIONS AND QUEUES.........................................................................................................................38
8.11 ARBITER......................................................................................................................................................39 8.12 FLOW CONTROL...........................................................................................................................................40
8.12.1 Full-Duplex Flow Control.....................................................................................................................41 8.12.2 Half Duplex Flow control.....................................................................................................................42
8.12.3 Host-Managed Flow control................................................................................................................42 8.13 ETHERNET INTERFACE PORT.....................................................................................................................43 8.13.1 DTE and DCE Mode...........................................................................................................................45
8.14 ETHERNET MAC..........................................................................................................................................46 8.14.1 MII Mode Options................................................................................................................................48
8.14.2 RMII Mode...........................................................................................................................................48 8.14.3 PHY MII Management Block and MDIO Interface...............................................................................49
8.15 BERT..........................................................................................................................................................50 8.15.1 Receive Data Interface........................................................................................................................50
DS33Z11 Ethernet Mapper
8.15.3 Pattern Monitoring...............................................................................................................................52 8.15.4 Pattern Generation..............................................................................................................................52
8.16 TRANSMIT PACKET PROCESSOR...................................................................................................................53 8.17 RECEIVE PACKET PROCESSOR.....................................................................................................................54
8.18 X.86 ENCODING AND DECODING...................................................................................................................56 8.19 COMMITTED INFORMATION RATE CONTROLLER..............................................................................................59
8.20 HARDWARE MODE........................................................................................................................................61
DEVICE REGISTERS..................................................................................................................65 9.1 REGISTER BIT MAPS....................................................................................................................................66
9.1.1 Global Register Bit Map......................................................................................................................66 9.1.2 Arbiter Register Bit Map......................................................................................................................67
9.1.3 BERT Register Bit Map.......................................................................................................................67 9.1.4 Serial Interface Register Bit Map........................................................................................................68
9.1.5 Ethernet Interface Register Bit Map....................................................................................................70 9.1.6 MAC Register Bit Map.........................................................................................................................71
9.2 GLOBAL REGISTER DEFINITIONS...................................................................................................................73 9.3 ARBITER REGISTERS....................................................................................................................................80
9.3.1 Arbiter Register Bit Descriptions.........................................................................................................80 9.4 BERT REGISTERS.......................................................................................................................................81 9.5 SERIAL INTERFACE REGISTERS.....................................................................................................................88
9.5.1 Serial Interface Transmit and Common Registers..............................................................................88 9.5.2 Serial Interface Transmit Register Bit Descriptions............................................................................88
9.5.3 Transmit HDLC Processor Registers..................................................................................................89 9.5.4 X.86 Registers.....................................................................................................................................96
9.5.5 Receive Serial Interface......................................................................................................................98 9.6 ETHERNET INTERFACE REGISTERS.............................................................................................................111
9.6.1 Ethernet Interface Register Bit Descriptions.....................................................................................111 9.6.2 MAC Registers..................................................................................................................................123
10 FUNCTIONAL TIMING..............................................................................................................139 10.1 FUNCTIONAL SERIAL I/O TIMING.................................................................................................................139 10.2 MII AND RMII INTERFACES.........................................................................................................................140
10.3 SPI INTERFACE MODE AND EEPROM PROGRAM SEQUENCE......................................................................142
11 OPERATING PARAMETERS....................................................................................................144 11.1 THERMAL CHARACTERISTICS......................................................................................................................145
11.2 THETA-JA VS. AIRFLOW.............................................................................................................................145 11.3 TRANSMIT MII INTERFACE..........................................................................................................................146
11.4 RECEIVE MII INTERFACE............................................................................................................................147 11.5 TRANSMIT RMII INTERFACE........................................................................................................................148 11.6 RECEIVE RMII INTERFACE..........................................................................................................................149
11.7 MDIO INTERFACE......................................................................................................................................150 11.8 TRANSMIT WAN INTERFACE.......................................................................................................................151
11.9 RECEIVE WAN INTERFACE.........................................................................................................................152 11.10 SDRAM TIMING.........................................................................................................................................153 11.11 AC CHARACTERISTICSMICROPROCESSOR BUS TIMING............................................................................155
11.12 EEPROM INTERFACE TIMING....................................................................................................................158 11.13 JTAG INTERFACE TIMING...........................................................................................................................159
12 JTAG INFORMATION...............................................................................................................160 12.1 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION............................................................................160 12.2 INSTRUCTION REGISTER.............................................................................................................................163
12.2.1 SAMPLE:PRELOAD.........................................................................................................................164 12.2.2 BYPASS............................................................................................................................................164
12.2.3 EXTEST............................................................................................................................................164 12.2.4 CLAMP..............................................................................................................................................164
12.2.5 HIGHZ...............................................................................................................................................164
DS33Z11 Ethernet Mapper
12.3 JTAG ID CODES.......................................................................................................................................165 12.4 TEST REGISTERS.......................................................................................................................................165
12.5 BOUNDARY SCAN REGISTER.......................................................................................................................165 12.6 BYPASS REGISTER.....................................................................................................................................165
12.7 IDENTIFICATION REGISTER..........................................................................................................................165 12.8 JTAG FUNCTIONAL TIMING........................................................................................................................165
13 PACKAGE INFORMATION.......................................................................................................167 13.1 PACKAGE OUTLINE DRAWING OF 169-BALL CSBGA (VIEW FROM BOTTOM OF DEVICE).................................167 13.2 PACKAGE OUTLINE DRAWING OF 100-BALL CSBGA (DS33ZH11 ONLY).....................................................168
14 REVISION HISTORY.................................................................................................................169 DS33Z11 Ethernet Mapper
LIST OF FIGURES Figure 3-1 Ethernet to WAN Extension (No Framing)..............................................................................................11
Figure 3-2 Ethernet to WAN Extension (T1E1 Framing and LIU)............................................................................12 Figure 3-3 Ethernet to WAN Extension with T3/E3 Framing....................................................................................12
Figure 3-4 Ethernet over DSL...................................................................................................................................13 Figure 3-5 Copper to Fiber Connection....................................................................................................................13 Figure 6-1 Detailed Block Diagram...........................................................................................................................16
Figure 7-1 DS33Z11 169-Ball CSBGA Pinout..........................................................................................................27 Figure 7-2 DS33ZH11 100-Ball CSBGA Pinout (Hardware or SPI Mode Only).......................................................28
Figure 8-1 Clocking for the DS33Z11.......................................................................................................................32 Figure 8-2 Device Interrupt Information Flow Diagram.............................................................................................37 Figure 8-3 Flow Control Using Pause Control Frame...............................................................................................42
Figure 8-4 IEEE 802.3 Ethernet Frame....................................................................................................................43 Figure 8-5 Configured as DTE Connected to an Ethernet PHY in MII Mode............................................................45
Figure 8-6 DS33Z11 Configured as a DCE in MII Mode..........................................................................................46 Figure 8-7 RMII Interface..........................................................................................................................................48 Figure 8-8 MII Management Frame..........................................................................................................................49
Figure 8-9 PRBS Synchronization State Diagram....................................................................................................51 Figure 8-10 Repetitive Pattern Synchronization State Diagram...............................................................................52
Figure 8-11 LAPS Encoding of MAC Frames Concept.............................................................................................56 Figure 8-12 X.86 Encapsulation of the MAC field.....................................................................................................57 Figure 8-13 CIR in the WAN Transmit Path.............................................................................................................60
Figure 10-1 TX Serial Interface Functional Timing.................................................................................................139 Figure 10-2 RX Serial Interface Functional Timing.................................................................................................139
Figure 10-3 Transmit Byte Sync Functional timing.................................................................................................140 Figure 10-4 Receive Byte Sync Functional Timing.................................................................................................140 Figure 10-5 MII Transmit Functional Timing...........................................................................................................141
Figure 10-6 MII Transmit Half Duplex with a Collision Functional Timing..............................................................141 Figure 10-7 MII Receive Functional Timing............................................................................................................141
Figure 10-8 RMII Transmit Interface Functional Timing.........................................................................................141 Figure 10-9 RMII Receive Interface Functional Timing..........................................................................................142 Figure 10-10 SPI Master Functional Timing...........................................................................................................142
Figure 11-1 Transmit MII Interface.........................................................................................................................146 Figure 11-2 Receive MII Interface Timing...............................................................................................................147
Figure 11-3 Transmit RMII Interface.......................................................................................................................148 Figure 11-4 Receive RMII Interface Timing............................................................................................................149 Figure 11-5 MDIO Timing.......................................................................................................................................150
Figure 11-6 Transmit WAN Timing.........................................................................................................................151 Figure 11-7 Receive WAN timing...........................................................................................................................152
Figure 11-8 SDRAM Interface Timing.....................................................................................................................154 Figure 11-9 Intel Bus Read Timing (HWMODE = 0, MODEC = 00).......................................................................156 Figure 11-10 Intel Bus Write Timing (HWMODE = 0, MODEC = 00).....................................................................156
Figure 11-11 Motorola Bus Read Timing (HWMODE = 0, MODEC = 01)..............................................................157 Figure 11-12 Motorola Bus Write Timing (HWMODE = 0, MODEC = 01)..............................................................157
Figure 11-13 EEPROM Interface Timing................................................................................................................158 Figure 11-14 JTAG Interface Timing Diagram........................................................................................................159 Figure 12-1 JTAG Functional Block Diagram.........................................................................................................160
Figure 12-2 TAP Controller State Diagram.............................................................................................................163 Figure 12-3 JTAG Functional Timing......................................................................................................................166
