DS33W11+ ,Ethernet Over PDH Mapping DevicesFUNCTIONAL DESCRIPTION....34 8.1 PARALLEL PROCESSOR INTERFACE......35 8.1.1 Read-Write/Data Strobe ..
DS33W41+ ,Ethernet Over PDH Mapping DevicesFeatures continued in Section 2. Ethernet service. The voice ports of the DS33W41 and DS33W11 Orde ..
DS33X11 ,Ethernet Over PDH Mapping DevicesFeatures The DS33X162 family of semiconductor devices ♦ 10/100/1000 IEEE 802.3 MAC (MII/RMII/GMII) ..
DS33X11+ ,Ethernet Over PDH Mapping DevicesRev: 063008 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 Ethernet Ov ..
DS33X11DK ,Demo Kit for the DS33X11Features The DS33X11 demo kit (DK) is an easy-to-use ♦ Demonstrates Key Functions of DS33X11 evalua ..
DS33X161+ ,Ethernet Over PDH Mapping DevicesFEATURES ....67 8.16.1 VLAN Forwarding by VID (IEEE 802.1q) ... 67 8.16.2 Programming the VLAN ID T ..
EB2-12 ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEFEATURESª Compact and lightweight : 7.5 mm · 14.3 mm · 9.3 mm, 1.5 gª 2 form c contact arrangementª ..
EB2-12NU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
EB2-12TNU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
DS33W11+-DS33W41+-DS33X11-DS33X11+-DS33X161+-DS33X162-DS33X162+-DS33X41+
Ethernet Over PDH Mapping Devices
Maxim Integrated Products 1 DS33X162/DS33X161/DS33X82/DS33X81/ DS33X42/DS33X41/DS33X11/DS33W41/DS33W11 hernet Over PDH Mapping Devices
General Description The DS33X162 family of semiconductor devices
extend 10/100/1000Mbps Ethernet LAN segments by
encapsulating MAC frames in GFP-F, HDLC, cHDLC,
or X.86 (LAPS) for transmission over PDH/TDM data
streams. The devices support the Ethernet over PDH
(EoPDH) standards for the delivery of Ethernet
Access Services, including eLAN, eLINE, and VLAN.
The multiport devices support VCAT/LCAS for
dynamic link aggregation. The serial links support
bidirectional synchronous interconnect up to 52Mbps
over xDSL, T1/E1/J1, T3/E3, or V.35/Optical.
The devices perform store-and-forward of frames
with Ethernet traffic conditioning and bridging
functions at wire speed. The programmability of
classification, priority queuing, encapsulation, and
bundling allows great flexibility in providing various
Ethernet services. OAM flows can be extracted and
inserted by an external processor to manage the
Ethernet service.
The voice ports of the DS33W41 and DS33W11
easily connect to external codecs for integrated voice
and data service applications.
Applications Bonded Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1, T3/E3,
OC-1/EC-1, G.SHDSL, or HDSL2/4
Functional Diagram
Features ♦
10/100/1000 IEEE 802.3 MAC (MII/RMII/GMII)
with Autonegotiation and Flow Control ♦
GFP-F/LAPS/HDLC/cHDLC Encapsulation ♦
VCAT/LCAS Link Aggregation for Up to 16
Links ♦
Supports Up to 200ms Differential Delay ♦
Quality of Service (QoS) Support ♦
VLAN, Q-in-Q, 802.1p, and DSCP Support ♦
Ethernet Bridging and Filtering ♦
Add/Drop OAM Frames from μP Interface ♦
Traffic Shaping Through CIR/CBS Policing ♦
External 256Mb, 125MHz DDR SDRAM Buffer ♦
Parallel and SPI™ Microprocessor Interfaces ♦
1.8V, 2.5V, 3.3V Supplies ♦
IEEE 1149.1 JTAG Support
Features continued in Section 2.
Ordering Information
PORTS PART TDM ETHERNET VOICE
PIN-
PACKAGE
DS33X162+ 16 2 0 256 CSBGA
DS33X161+ 16 1 0 256 CSBGA
DS33X82+ 8 2 0 256 CSBGA
DS33X81+ 8 1 0 256 CSBGA
DS33X42+ 4 2 0 256 CSBGA
DS33X41+ 4 1 0 256 CSBGA
DS33X11+ 1 1 0 144 CSBGA
DS33W41+ 4 1 1 256 CSBGA
DS33W11+ 1 1 1 256 CSBGA
Note: All devices are specified over the -40°C to +85°C industrial operating temperature range.
+Denotes a lead-free/RoHS-compliant package.
SPI is a trademark of Motorola, Inc.
Rev: 063008
SDRAM CONTROLLER
MACs
ENET
PHYs
PROCESSOR
DDR SDRAM
TDM LIU/
FRAMER
FFIC
MGMT
BRIDGING
8-BIT & SPI μP INTERFACE
QoS
POLICY
BUFFER MANAGER
GFP/
LAPS/ HDLC
VOICE PORT
WAN
SERIAL
PORTS
CLAD
DS33X162
_________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11
Table of Contents
1. DETAILED DESCRIPTION..............................................................................................................9
2. FEATURE HIGHLIGHTS................................................................................................................10 2.1 GENERAL......................................................................................................................................10
2.2 VCAT/LCAS LINK AGGREGATION (INVERSE MULTIPLEXING)..........................................................10
2.3 HDLC...........................................................................................................................................10
2.3.1 cHDLC..................................................................................................................................................10
2.4 GFP-F..........................................................................................................................................11
2.5 X.86 SUPPORT.............................................................................................................................11
2.6 DDR SDRAM INTERFACE.............................................................................................................11
2.7 MAC INTERFACES.........................................................................................................................11
2.7.1 Ethernet Bridging for 10/100................................................................................................................12
2.7.2 Ethernet Traffic Classification..............................................................................................................12
2.7.3 Ethernet Bandwidth Policing................................................................................................................12
2.7.4 Ethernet Traffic Scheduling..................................................................................................................12
2.7.5 Connection Endpoints..........................................................................................................................12
2.7.6 Virtual Connection................................................................................................................................12
2.7.7 Connection and Aggregation...............................................................................................................12
2.7.8 Ethernet Control Frame Processing.....................................................................................................12
2.7.9 Q-in-Q..................................................................................................................................................12
2.8 SERIAL PORTS..............................................................................................................................13
2.8.1 Voice Ports...........................................................................................................................................13
2.9 MICROPROCESSOR INTERFACE......................................................................................................13
2.10 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES............................................................13
2.11 TEST AND DIAGNOSTICS.............................................................................................................13
2.12 SPECIFICATIONS COMPLIANCE....................................................................................................13
3. APPLICABLE EQUIPMENT TYPES..............................................................................................14
4. ACRONYMS & GLOSSARY..........................................................................................................17
5. DESIGNING WITH THE DS33X162 FAMILY OF DEVICES..........................................................18 5.1 IDENTIFICATION OF APPLICATION REQUIREMENTS..........................................................................18
5.2 DEVICE SELECTION.......................................................................................................................18
5.3 ANCILLARY DEVICE SELECTION......................................................................................................19
5.4 CIRCUIT DESIGN............................................................................................................................19
5.5 BOARD LAYOUT.............................................................................................................................19
5.6 SOFTWARE DEVELOPMENT............................................................................................................19
6. BLOCK DIAGRAMS......................................................................................................................20
7. PIN DESCRIPTIONS......................................................................................................................21 7.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................21
8. FUNCTIONAL DESCRIPTION.......................................................................................................34 8.1 PARALLEL PROCESSOR INTERFACE................................................................................................35
8.1.1 Read-Write/Data Strobe Modes...........................................................................................................35
8.1.2 Clear on Read......................................................................................................................................35
8.1.3 Interrupt and Pin Modes.......................................................................................................................35
8.1.4 Multiplexed Bus Operation...................................................................................................................35
8.2 SPI SERIAL PROCESSOR INTERFACE.............................................................................................36
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 8.4 RESETS AND LOW-POWER MODES................................................................................................39
8.5 INITIALIZATION AND CONFIGURATION..............................................................................................41
8.6 GLOBAL RESOURCES....................................................................................................................41
8.7 PER-PORT RESOURCES................................................................................................................41
8.8 DEVICE INTERRUPTS.....................................................................................................................41
8.9 FORWARDING MODES AND WAN CONNECTIONS............................................................................43
8.9.1 Forwarding Modes...............................................................................................................................43
8.9.2 WAN Connections................................................................................................................................49
8.9.3 Queue Configuration............................................................................................................................50
8.10 BANDWIDTH CAPABILITIES (THROUGHPUT)..................................................................................51
8.11 SERIAL (WAN)...........................................................................................................................52
8.11.1 Voice Support (DS33W11 and DW33W41 Only).................................................................................52
8.12 LINK AGGREGATION AND LINK CAPACITY ADJUSTMENT (VCAT/LCAS)........................................53
8.12.1 VCAT/LCAS Control Frame for T3/E3.................................................................................................54
8.12.2 VCAT/LCAS Configuration and Operation...........................................................................................55
8.12.3 Link Capacity Adjustment Scheme (LCAS).........................................................................................56
8.12.4 Alarms and Conditions related to VCAT/LCAS....................................................................................57
8.13 ARBITER/BUFFER MANAGER.......................................................................................................57
8.14 FLOW CONTROL.........................................................................................................................58
8.14.1 Full Duplex Flow control.......................................................................................................................59
8.14.2 Half Duplex Flow control......................................................................................................................59
8.15 ETHERNET INTERFACES.............................................................................................................60
8.15.1 GMII Mode...........................................................................................................................................62
8.15.2 MII Mode..............................................................................................................................................63
8.15.3 DTE and DCE Mode............................................................................................................................65
8.15.4 RMII Mode............................................................................................................................................66
8.16 QUALITY OF SERVICE (QOS) FEATURES.....................................................................................67
8.16.1 VLAN Forwarding by VID (IEEE 802.1q).............................................................................................67
8.16.2 Programming the VLAN ID Table........................................................................................................68
8.16.3 Priority Coding with VLAN Tags (IEEE 802.1p)...................................................................................69
8.16.4 Priority Coding with Multiple (Q-in-Q) VLAN Tags...............................................................................70
8.16.5 Priority Coding with DSCP...................................................................................................................71
8.16.6 Programming the Priority Table...........................................................................................................72
8.17 OAM SUPPORT WITH FRAME TRAPPING, EXTRACTION, AND INSERTION.......................................74
8.17.1 Frame Trapping....................................................................................................................................76
8.17.2 Frame Extraction and Frame Insertion................................................................................................77
8.17.3 OAM by Ethernet Destination Address (DA)........................................................................................78
8.17.4 OAM by IP Address..............................................................................................................................78
8.17.5 OAM by VLAN Tag...............................................................................................................................78
8.17.6 SNMP Support.....................................................................................................................................78
8.18 BRIDGING AND FILTERING...........................................................................................................79
8.18.1 Bridge Filter Table Reset.....................................................................................................................79
8.19 ETHERNET MAC........................................................................................................................80
8.19.1 PHY MII Management Block and MDIO Interface...............................................................................83
8.19.2 Ethernet MAC Management Counters for RFC2819 RMON...............................................................84
8.19.3 Programmable Ethernet Destination Address Filtering........................................................................85
8.20 ETHERNET FRAME ENCAPSULATION...........................................................................................86
8.20.1 Transmit Packet Processor (Encapsulator).........................................................................................86
8.20.2 Receive Packet Processor (Decapsulator)..........................................................................................87
8.20.3 GFP-F Encapsulation and Decapsulation............................................................................................89
8.20.4 X.86 Encoding and Decoding..............................................................................................................94
8.20.5 HDLC Encoding and Decoding............................................................................................................96
8.20.6 cHDLC Encoding And Decoding..........................................................................................................98
8.21 CIR/CBS CONTROLLER.............................................................................................................99
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 9.1 INTERFACING TO MAXIM T1/E1 TRANSCEIVERS............................................................................101
9.2 INTERFACING TO MAXIM T3/E3 TRANSCEIVERS............................................................................103
10. DEVICE REGISTERS...................................................................................................................105 10.1 REGISTER BIT MAPS................................................................................................................106
10.1.1 Global Register Bit Map.....................................................................................................................106
10.1.2 MAC Indirect Register Bit Map...........................................................................................................131
10.2 GLOBAL REGISTER DEFINITIONS...............................................................................................141
10.2.1 Microport Registers............................................................................................................................147
10.2.2 MAC 1 Interface Access Registers....................................................................................................152
10.2.3 MAC 2 Interface Access Registers....................................................................................................156
10.2.4 VLAN Control Registers.....................................................................................................................160
10.3 ETHERNET INTERFACE REGISTERS...........................................................................................164
10.3.1 WAN Extraction and Transmit LAN registers.....................................................................................164
10.3.2 Receive LAN Register Definitions......................................................................................................175
10.3.3 Bridge Filter Registers........................................................................................................................188
10.4 ARBITER REGISTERS................................................................................................................189
10.4.1 Arbiter Register Bit Descriptions........................................................................................................189
10.5 PACKET PROCESSOR (ENCAPSULATOR) REGISTERS.................................................................230
10.6 DECAPSULATOR REGISTERS....................................................................................................236
10.7 VCAT/LCAS REGISTERS.........................................................................................................245
10.7.1 Transmit VCAT Registers..................................................................................................................245
10.7.2 VCAT Receive Register Description..................................................................................................252
10.8 SERIAL INTERFACE REGISTERS................................................................................................265
10.8.1 Serial Interface Transmit and Common Registers.............................................................................265
10.8.2 Serial Interface Transmit Register Bit Descriptions...........................................................................265
10.8.3 Transmit Per Serial Port Register Description...................................................................................269
10.8.4 Transmit Voice Port Register Description..........................................................................................270
10.8.5 Receive Per Serial Port Register Description....................................................................................273
10.8.6 Receive Voice Port Register Description...........................................................................................274
10.8.7 MAC Registers...................................................................................................................................275
11. FUNCTIONAL TIMING.................................................................................................................330 11.1 FUNCTIONAL SPI INTERFACE TIMING........................................................................................330
11.1.1 SPI Transmission Format and CPHA Polarity...................................................................................330
11.2 FUNCTIONAL SERIAL INTERFACE TIMING...................................................................................333
11.3 VOICE PORT FUNCTIONAL TIMING DIAGRAMS............................................................................335
11.4 MII/RMII AND GMII INTERFACES..............................................................................................336
12. OPERATING PARAMETERS......................................................................................................339 12.1 THERMAL CHARACTERISTICS....................................................................................................341
12.2 TRANSMIT AND RECEIVE GMII INTERFACE................................................................................342
12.3 TRANSMIT AND RECEIVE MII INTERFACE...................................................................................344
12.4 TRANSMIT AND RECEIVE RMII INTERFACE................................................................................346
12.5 MDIO INTERFACE....................................................................................................................348
12.6 TRANSMIT AND RECEIVE WAN INTERFACE................................................................................349
12.7 TRANSMIT AND RECEIVE VOICE PORT INTERFACE.....................................................................351
12.8 DDR SDRAM INTERFACE........................................................................................................353
12.9 AC CHARACTERISTICS—MICROPROCESSOR BUS INTERFACE TIMING........................................355
12.10 JTAG INTERFACE....................................................................................................................362
13. JTAG INFORMATION..................................................................................................................363 13.1 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION.........................................................364
13.1.1 TAP Controller State Machine...........................................................................................................364
________________________________________________DS33X162/X161/X82/X81/X42/X41/X11/W41/W11 13.2.2 BYPASS.............................................................................................................................................367
13.2.3 EXTEST.............................................................................................................................................367
13.2.4 CLAMP...............................................................................................................................................367
13.2.5 HIGHZ................................................................................................................................................367
13.2.6 IDCODE.............................................................................................................................................367
13.3 JTAG ID CODES......................................................................................................................368
13.4 TEST REGISTERS.....................................................................................................................368
13.4.1 Boundary Scan Register....................................................................................................................368
13.4.2 Bypass Register.................................................................................................................................368
13.4.3 Identification Register.........................................................................................................................368
13.5 JTAG FUNCTIONAL TIMING......................................................................................................369
14. PIN CONFIGURATION................................................................................................................370 14.1 DS33X162/X161/X82/X81/X42/X41 PIN CONFIGURATION—256-BALL CSBGA.......................370
14.2 DS33W41/DS33W11 PIN CONFIGURATION—256-BALL CSBGA.............................................371
14.3 DS33X11 PIN CONFIGURATION—144-BALL CSBGA................................................................372
15. PACKAGE INFORMATION.........................................................................................................373 15.1 256-BALL CSBGA, 17MM X 17MM (56-G6017-001).................................................................373
15.2 144-BALL CSBGA, 10MM X 10MM (56-G6008-003).................................................................374
16. DOCUMENT REVISION HISTORY..............................................................................................375
