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DS33R41-DS33R41+
Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
GENERAL DESCRIPTION The DS33R41 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or
X.86 (LAPS) for transmission over four interleaved
T1/E1/J1 lines using a robust, balanced, and
programmable inverse multiplexing. Four integrated
T1/E1/J1 transceivers provide framing and line
interfacing functionality.
The device performs store-and-forward of packets
with full wire-speed transport capability. The built-in
committed information rate (CIR) controller provides
fractional bandwidth allocation up to the line rate in
increments of 512kbps.
FUNCTIONAL DIAGRAM
FEATURES �
10/100 IEEE 802.3 Ethernet MAC (MII and
RMII) Half/Full Duplex with Automatic Flow
Control �
Layer 1 Inverse Multiplexing Over Four
T1/E1/J1 Lines Through the Integrated
Framers and LIUs �
Supports Up to 7.75ms Differential Delay �
Aggregate Bandwidth from Up to Four
T1/E1/J1 Links �
T1/E1 Signaling Capability for OAM �
HDLC/LAPS Encapsulation with
Programmable FCS, Interframe Fill �
CIR Controller Provides Fractional
Allocations in 512kbps Increments �
Programmable BERTs �
External 16MB, 100MHz SDRAM Buffering �
Parallel Microprocessor Interface �
1.8V, 3.3V Power Supplies �
IEEE 1149.1 JTAG Support Features continued on page 11.
APPLICATIONS Bonded Transparent LAN Service
LAN Extension
Ethernet Delivery Over T1/E1/J1
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS33R41 -40°C to +85°C 400 BGA
DS33R41
Inverse-Multiplexing Ethernet Mapper with
Quad Integrated T1/E1/J1 Transceivers
10/100
MAC
SDRAM
MII/RMII
μC
DS33R41 10/100
ETHERNET
PHY
4 INTERLEAVED
SERIAL STREAMS
4 T1/E1/J1
TRANSCEIVERS
WITH BERTs
HDLC/X.86
ETHERNET
MAPPER
T1/E1
LINES
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
TABLE OF CONTENTS DESCRIPTION...................................................................................................................................9 FEATURE HIGHLIGHTS..................................................................................................................11 2.1 GENERAL......................................................................................................................................11
2.2 MICROPROCESSOR INTERFACE......................................................................................................11
2.3 LINK AGGREGATION (INVERSE MULTIPLEXING)...............................................................................11
2.4 HDLC ETHERNET MAPPING..........................................................................................................11
2.5 X.86 (LINK ACCESS PROTOCOL FOR SONET/SDH) ETHERNET MAPPING.......................................11
2.6 ADDITIONAL HDLC CONTROLLERS IN THE INTEGRATED T1/E1/J1 TRANSCEIVER............................12
2.7 COMMITTED INFORMATION RATE (CIR) CONTROLLERS..................................................................12
2.8 SDRAM INTERFACE......................................................................................................................12
2.9 T1/E1/J1 FRAMER........................................................................................................................12
2.10 LINE INTERFACE............................................................................................................................13
2.11 MAC INTERFACE...........................................................................................................................13
2.12 CLOCK SYNTHESIZER....................................................................................................................13
2.13 JITTER ATTENUATOR.....................................................................................................................13
2.14 SYSTEM INTERFACE......................................................................................................................14
2.15 TEST AND DIAGNOSTICS................................................................................................................14
2.16 SPECIFICATIONS COMPLIANCE.......................................................................................................14
APPLICATIONS...............................................................................................................................15 ACRONYMS AND GLOSSARY.......................................................................................................16 MAJOR OPERATING MODES........................................................................................................17 BLOCK DIAGRAMS.........................................................................................................................18 6.1 FRAMER/LIU INTERIM SIGNALS......................................................................................................20
PIN DESCRIPTIONS........................................................................................................................21 7.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................21
FUNCTIONAL DESCRIPTION.........................................................................................................33 8.1 PROCESSOR INTERFACE...............................................................................................................34
8.1.1 Read-Write/Data Strobe Modes............................................................................................................35
8.1.2 Clear on Read.......................................................................................................................................35
8.1.3 Interrupt and Pin Modes........................................................................................................................35
ETHERNET MAPPER......................................................................................................................36 9.1 ETHERNET MAPPER CLOCKS.........................................................................................................36
9.1.1 Serial Interface Clock Modes................................................................................................................38
9.1.2 Ethernet Interface Clock Modes............................................................................................................38
9.2 RESETS AND LOW-POWER MODES................................................................................................39
9.3 INITIALIZATION AND CONFIGURATION..............................................................................................40
9.4 GLOBAL RESOURCES....................................................................................................................41
9.5 PER-PORT RESOURCES................................................................................................................41
9.6 DEVICE INTERRUPTS.....................................................................................................................41
9.7 SERIAL INTERFACE........................................................................................................................43
9.8 LINK AGGREGATION (IMUX)..........................................................................................................43
9.8.1 Microprocessor Requirements..............................................................................................................45
9.8.2 IMUX Command Protocol.....................................................................................................................46
9.8.3 Out of Frame (OOF) Monitoring............................................................................................................48
9.8.4 Data Transfer........................................................................................................................................48
9.9 CONNECTIONS AND QUEUES.........................................................................................................49
9.10 ARBITER.......................................................................................................................................50
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
9.11.1 Full Duplex Flow Control.......................................................................................................................51
9.11.2 Half Duplex Flow Control......................................................................................................................53
9.11.3 Host-Managed Flow Control.................................................................................................................53
9.12 ETHERNET INTERFACE PORT.........................................................................................................54
9.12.1 DTE and DCE Mode.............................................................................................................................56
9.13 ETHERNET MAC...........................................................................................................................57
9.13.1 MII Mode...............................................................................................................................................59
9.13.2 RMII Mode.............................................................................................................................................59
9.13.3 PHY MII Management Block and MDIO Interface................................................................................60
9.14 TRANSMIT PACKET PROCESSOR....................................................................................................61
9.15 RECEIVE PACKET PROCESSOR......................................................................................................62
9.16 X.86 ENCODING AND DECODING....................................................................................................64
9.17 COMMITTED INFORMATION RATE CONTROLLER..............................................................................67
10 INTEGRATED T1/E1/J1 TRANSCEIVERS......................................................................................68 10.1 T1/E1/J1 TRANSCEIVER CLOCKS..................................................................................................68
10.2 PER-CHANNEL OPERATION............................................................................................................69
10.3 T1/E1/J1 TRANSCEIVER INTERRUPTS............................................................................................69
10.4 T1 FRAMER/FORMATTER CONTROL AND STATUS...........................................................................70
10.4.1 T1 Transmit Transparency....................................................................................................................70
10.4.2 AIS-CI and RAI-CI Generation and Detection......................................................................................70
10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation..............................................................................71
10.5 E1 FRAMER/FORMATTER CONTROL AND STATUS...........................................................................72
10.5.1 Automatic Alarm Generation.................................................................................................................73
10.6 LOOPBACK CONFIGURATIONS........................................................................................................74
10.6.1 Per-Channel Payload Loopback...........................................................................................................75
10.7 ERROR COUNTERS........................................................................................................................76
10.7.1 Line-Code Violation Counter (TR.LCVCR)...........................................................................................76
10.7.2 Path Code Violation Count Register (TR.PCVCR)...............................................................................77
10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR)..............................................................................78
10.7.4 E-Bit Counter (TR.EBCR).....................................................................................................................78
10.8 DS0 MONITORING FUNCTION........................................................................................................79
10.9 SIGNALING OPERATION.................................................................................................................80
10.9.1 Processor-Based Receive Signaling....................................................................................................80
10.9.2 Hardware-Based Receive Signaling.....................................................................................................81
10.9.3 Processor-Based Transmit Signaling...................................................................................................82
10.9.4 Hardware-Based Transmit Signaling....................................................................................................83
10.10 PER-CHANNEL IDLE CODE GENERATION........................................................................................84
10.10.1 Idle-Code Programming Examples.......................................................................................................85
10.11 CHANNEL BLOCKING REGISTERS...................................................................................................86
10.12 ELASTIC STORES OPERATION........................................................................................................86
10.12.1 Receive Side.........................................................................................................................................86
10.12.2 Transmit Side........................................................................................................................................87
10.12.3 Elastic Stores Initialization....................................................................................................................87
10.13 G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY)............................................................88
10.14 T1 BIT-ORIENTED CODE (BOC) CONTROLLER...............................................................................89
10.14.1 Transmit BOC.......................................................................................................................................89
10.15 RECEIVE BOC..............................................................................................................................89
10.16 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY)...........................................90
10.16.1 Method 1: Internal Register Scheme Based on Double-Frame............................................................90
10.16.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe.......................................................90
10.17 ADDITIONAL HDLC CONTROLLERS IN T1/E1/J1 TRANSCEIVER.......................................................91
10.17.1 HDLC Configuration..............................................................................................................................91
10.17.2 FIFO Control.........................................................................................................................................93
10.17.3 HDLC Mapping......................................................................................................................................94
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
10.17.5 Receive Packet-Bytes Available...........................................................................................................95
10.18 LEGACY FDL SUPPORT (T1 MODE)...............................................................................................96
10.18.1 Overview...............................................................................................................................................96
10.18.2 Receive Section....................................................................................................................................96
10.18.3 Transmit Section...................................................................................................................................97
10.19 D4/SLC-96 OPERATION................................................................................................................97
10.20 LINE INTERFACE UNIT (LIU)...........................................................................................................98
10.20.1 LIU Operation........................................................................................................................................98
10.20.2 Receiver................................................................................................................................................98
10.20.3 Transmitter..........................................................................................................................................100
10.21 MCLK PRESCALER.....................................................................................................................101
10.22 JITTER ATTENUATOR...................................................................................................................101
10.23 CMI (CODE MARK INVERSION) OPTION........................................................................................101
10.24 RECOMMENDED CIRCUITS...........................................................................................................102
10.25 T1/E1/J1 TRANSCEIVER BERT FUNCTION...................................................................................107
10.25.1 BERT Status.......................................................................................................................................107
10.25.2 BERT Mapping....................................................................................................................................107
10.25.3 BERT Repetitive Pattern Set..............................................................................................................109
10.25.4 BERT Bit Counter................................................................................................................................109
10.25.5 BERT Error Counter............................................................................................................................109
10.25.6 BERT Alternating Word-Count Rate...................................................................................................109
10.26 PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY)...........................................................110
10.26.1 Number-of-Errors Registers................................................................................................................110
10.26.2 Number of Errors Left Register...........................................................................................................110
11 INTERLEAVED PCM BUS OPERATION.......................................................................................111 11.1 CHANNEL INTERLEAVE MODE......................................................................................................111
11.2 PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER.....................................................................113
11.3 FRACTIONAL T1/E1 SUPPORT.....................................................................................................113
11.4 T1/E1/J1 TRANSMIT FLOW DIAGRAMS.........................................................................................114
12 DEVICE REGISTERS.....................................................................................................................118 12.1 REGISTER BIT MAPS...................................................................................................................119
12.1.1 Global Register Bit Map......................................................................................................................119
12.1.2 Arbiter Register Bit Map......................................................................................................................120
12.1.3 Serial Interface Register Bit Map........................................................................................................121
12.1.4 Ethernet Interface Register Bit Map....................................................................................................123
12.1.5 MAC Register Bit Map........................................................................................................................124
12.2 T1/E1/J1 TRANSCEIVER REGISTER BIT MAP................................................................................126
12.3 GLOBAL REGISTER DEFINITIONS FOR ETHERNET MAPPER............................................................131
12.4 ARBITER REGISTERS...................................................................................................................143
12.4.1 Arbiter Register Bit Descriptions.........................................................................................................143
12.5 SERIAL INTERFACE REGISTERS....................................................................................................144
12.5.1 Serial Interface Transmit and Common Registers..............................................................................144
12.5.2 Serial Interface Transmit Register Bit Descriptions............................................................................144
12.5.3 Transmit HDLC Processor Registers..................................................................................................145
12.5.4 X.86 Registers.....................................................................................................................................151
12.5.5 Receive Serial Interface......................................................................................................................153
12.6 ETHERNET INTERFACE REGISTERS..............................................................................................166
12.6.1 Ethernet Interface Register Bit Descriptions.......................................................................................166
12.6.2 MAC Registers....................................................................................................................................177
12.7 TRANSCEIVER REGISTERS...........................................................................................................193
12.7.1 Number-of-Errors Left Register...........................................................................................................293
13 FUNCTIONAL TIMING...................................................................................................................294
DS33R41 Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 Transceivers
13.3 E1 MODE....................................................................................................................................300
14 OPERATING PARAMETERS........................................................................................................305 14.1 THERMAL CHARACTERISTICS.......................................................................................................306
14.2 MII INTERFACE............................................................................................................................307
14.3 RMII INTERFACE.........................................................................................................................309
14.4 MDIO INTERFACE.......................................................................................................................311
14.5 TRANSMIT WAN INTERFACE........................................................................................................312
14.6 RECEIVE WAN INTERFACE..........................................................................................................313
14.7 SDRAM INTERFACE....................................................................................................................314
14.8 AC CHARACTERISTICS—MICROPROCESSOR BUS........................................................................316
14.9 JTAG INTERFACE TIMING............................................................................................................319
14.10 AC CHARACTERISTICS—RECEIVE SIDE.......................................................................................320
14.11 AC CHARACTERISTICS—TRANSMIT SIDE.....................................................................................324
15 JTAG INFORMATION....................................................................................................................327 15.1 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION.............................................................328
15.2 TAP CONTROLLER STATE MACHINE............................................................................................328
15.2.1 Test-Logic-Reset.................................................................................................................................328
15.2.2 Run-Test-Idle......................................................................................................................................328
15.2.3 Select-DR-Scan..................................................................................................................................328
15.2.4 Capture-DR.........................................................................................................................................328
15.2.5 Shift-DR...............................................................................................................................................328
15.2.6 Exit1-DR..............................................................................................................................................328
15.2.7 Pause-DR............................................................................................................................................328
15.2.8 Exit2-DR..............................................................................................................................................328
15.2.9 Update-DR..........................................................................................................................................329
15.2.10 Select-IR-Scan....................................................................................................................................329
15.2.11 Capture-IR...........................................................................................................................................329
15.2.12 Shift-IR................................................................................................................................................329
15.2.13 Exit1-IR...............................................................................................................................................329
15.2.14 Pause-IR.............................................................................................................................................329
15.2.15 Exit2-IR...............................................................................................................................................329
15.2.16 Update-IR............................................................................................................................................329
15.3 INSTRUCTION REGISTER..............................................................................................................331
15.3.1 SAMPLE:PRELOAD...........................................................................................................................331
15.3.2 BYPASS..............................................................................................................................................331
15.3.3 EXTEST..............................................................................................................................................331
15.3.4 CLAMP................................................................................................................................................331
15.3.5 HIGHZ.................................................................................................................................................331
15.3.6 IDCODE..............................................................................................................................................331
15.4 JTAG ID CODES.........................................................................................................................332
15.5 TEST REGISTERS........................................................................................................................332
15.5.1 Boundary Scan Register.....................................................................................................................332
15.5.2 Bypass Register..................................................................................................................................332
15.5.3 Identification Register.........................................................................................................................332
15.6 JTAG FUNCTIONAL TIMING.........................................................................................................333
16 PACKAGE INFORMATION............................................................................................................334 16.1 400-BALL BGA (27MM X 27MM) (56-G6003-002)........................................................................334
17 DOCUMENT REVISION HISTORY................................................................................................335
