DS33R11DK ,Ethernet Transport Design KitGENERAL DESCRIPTION The DS33R11/DS33ZH11 design kit is an easy-to- Demonstrates Key Functions of D ..
DS33R41 ,Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 TransceiversTABLE OF CONTENTS 1 DESCRIPTION ..... 9 2 FEATURE HIGHLIGHTS...... 11 2.1 GENERAL........ 11 2.2 MI ..
DS33R41+ ,Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 TransceiversAPPLICATIONS μC ETHERNET Bonded Transparent LAN Service MAPPER LAN Extension SDRAM Ethernet Deliv ..
DS33W11+ ,Ethernet Over PDH Mapping DevicesFUNCTIONAL DESCRIPTION....34 8.1 PARALLEL PROCESSOR INTERFACE......35 8.1.1 Read-Write/Data Strobe ..
DS33W41+ ,Ethernet Over PDH Mapping DevicesFeatures continued in Section 2. Ethernet service. The voice ports of the DS33W41 and DS33W11 Orde ..
DS33X11 ,Ethernet Over PDH Mapping DevicesFeatures The DS33X162 family of semiconductor devices ♦ 10/100/1000 IEEE 802.3 MAC (MII/RMII/GMII) ..
EB2-12 ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEFEATURESª Compact and lightweight : 7.5 mm · 14.3 mm · 9.3 mm, 1.5 gª 2 form c contact arrangementª ..
EB2-12NU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
EB2-12TNU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
DS33R11DK
Ethernet Transport Design Kit
GENERAL DESCRIPTION The DS33R11/DS33ZH11 design kit is an easy-to-
use evaluation board for the DS33R11 and the
DS33ZH11 Ethernet transport-over-serial link
devices. The DS33ZH11 section of the design kit
contains an option for either T3E3 or T1E1 serial
links. The DS33R11 chipset has an integrated T1E1
transceiver. All serial links are complete with line
interface, transformers, and network connections.
Dallas’ ChipView software is provided with the design
kit, giving point-and-click access to configuration and
status registers from a Windows-based PC.
On-board LEDs indicate receive loss-of-signal, queue
overflow, Ethernet link, Tx/Rx, and interrupt status.
Windows is a registered trademark of Microsoft Corp.
DESIGN KIT CONTENTS DS33R11DK/DS33ZH11DK Main Board (DS33R11 +
DS33ZH11)
CD ROM:
ChipView Software and Manual
DS33R11DK/DS33ZH11DK Data Sheet
Configuration Files
FEATURES � Demonstrates Key Functions of DS33R11 and
DS33ZH11 Ethernet Transport Chipsets � DS33ZH11 Section Includes DS21348 T1E1
LIU and DS3150 T3E3 LIU, Transformers, BNC
and RJ48 Network Connectors and
Termination � Provides Support for Hardware and Software
Modes � On-Board MMC2107 Processor and ChipView
Software Provide Point-and-Click Access to
DS33R11 Register Set � All DS33R11 and DS33ZH11 Interface Pins are
Easily Accessible for External Data
Source/Sink � LEDs for Loss-of-Signal, Queue Overflow,
Ethernet Link, Tx/Rx, and Interrupt Status � Easy-to-Read Silkscreen Labels Identify the
Signals Associated with All Connectors,
Jumpers, and LEDs
ORDERING INFORMATION
PART DESCRIPTION DS33R11DK Design Kit for DS33R11 and
DS33ZH11
DS33R11DK/DS33ZH11DK
Ethernet Transport Design Kit
DS33R11DK/DS33ZH11DK
TABLE OF CONTENTS
GENERAL DESCRIPTION..........................................................................................................1
DESIGN KIT CONTENTS............................................................................................................1
ORDERING INFORMATION.......................................................................................................1
COMPONENT LIST.....................................................................................................................3
SYSTEM FLOORPLAN...............................................................................................................8
PC BOARD ERRATA..................................................................................................................8
FILE LOCATIONS.......................................................................................................................9
BASIC OPERATION..................................................................................................................10 POWERING UP THE DESIGN KIT...............................................................................................................10
General...............................................................................................................................................................10
BASIC DS33R11 INITIALIZATION..............................................................................................................10
Additional Configuration for DS33R11...............................................................................................................10
BASIC DS33ZH11 INITIALIZATION............................................................................................................11
Additional Configuration for DS33ZH11.............................................................................................................11
MONITOR AND CAPTURE ETHERNET TRAFFIC...............................................................................11
LEDS, CONFIGURATION SWITCHES, JUMPERS, AND CONNECTORS..............................12
ADDRESS MAP (ALL CARDS)................................................................................................16
DS33R11 INFORMATION.........................................................................................................16
DS33R11DK/DS33ZH11DK INFORMATION............................................................................17
TECHNICAL SUPPORT............................................................................................................17
SCHEMATICS...........................................................................................................................17 DS33R11DK/DS33ZH11DK
COMPONENT LIST
DESIGNATION QTY DESCRIPTION SUPPLIER/PART NUMBER C01, C28, CB03, CB49,
CB136, CB146, CB192,
CP01, CP2, CP03
10 470µF ±20%, 6.3V tantalum capacitors
(D case)
KEM
T491D477M006AS
C02, C11, C30, CB36,
CB37, CB40–CB43,
CB45, CB153, CB195,
CB197
13 1µF ±10%, 16V ceramic capacitors
(1206)
Panasonic
ECJ-3YB1C105K
C03–C06, C13, C14,
C17, C20, C22, C26,
C29, . . .incomplete
listing (94 devices total)
94 0.1µF ±10%, 16V ceramic capacitors
(0603)
Phycomp
06032R104K7B20D
C07, C08, C09, C12,
C16, C18, C19, C21,
C23, C24, C31, . . .
incomplete listing (81
devices total)
81 10µF ±20%, 10V ceramic capacitors
(1206)
Panasonic
ECJ-3YB1A106M
C10, CB23, CB24, CB26,
CB33, CB91, CB95,
CB151, CB161, CB162,
CB175, CB177, CB181,
CB185, CB189, CB190
16 0.1µF ±20%, 16V X7R ceramic
capacitors (0603)
AVX
0603YC104MAT
C15, CB76, CB77,
CB169, CB179, CB188 6 10µF ±20%, 10V ceramic capacitors
(1206)
Panasonic
ECJ-3YB1A106M
C25, C27, CB154–
CB156, CB158–CB160,
CB166, CB173, CB174,
CB182, CB183
13 4.7µF, 6.3V ceramic multilayer
capacitors (0603)
UNK
ECJ-1VB0J475M
CB105 1 0.1µF ±10%, 16V ceramic capacitor
(0805)
Phycomp
08052R104K7B20D
CB180 1 1µF ±10%, 16V ceramic capacitor (1206) Panasonic
ECJ-3YB1C105K
DB01 1 1A, 40V Schottky diode International Rectifier
10BQ040
DS01, DS02, DS05,
DS13, DS14 5 Red LEDs (SMD) Panasonic
LN1251C
DS03, DS08, DS15,
DS19 4 Red LEDs (SMD) Panasonic
LN1251C
DS04, DS07, DS12,
DS21 4 Green LEDs (SMD) Panasonic
LN1351C
DS06, DS09, DS10,
DS11, DS16, D17, DS18,
DS20
8 Amber LEDs (SMD) Panasonic
LN1451C
GND_TP01, GND_TP02,
GND_TP03,
GND_TPB01,
GND_TPP01–
GND_TPP23
27 Standard ground clip Keystone
4954
H01–H06, HB01, HB02, 9 Kit, 4-40 hardware, 0.5" nylon standoff
Lab stock
DS33R11DK/DS33ZH11DK
DESIGNATION QTY DESCRIPTION SUPPLIER/PART NUMBER J01, J05, J06, J18, J36 5 Terminal strip (10-pin, dual row, vertical) Samtec
TSW-105-07-T-D
J02 1 DB9 right-angle connector (long case) AMP
747459-1
J03, J10, J11, J14–J17,
J25, J26, J27, J32, J34,
J35
13 100-mil, 2-position jumpers Lab stock
Not applicable
J04 1 100-mil, 2 x 7-position jumper Lab stock
Not applicable
J07, J08, J09 3 Not Populated
14-pin headers, dual row, vertical
Samtec
NOPOP-HDR-TSW-107-14-T-D
J12, J13, J22, J23, J30,
J33 6 L_TERMINAL STRIP, 10 PIN, DUAL
ROW, VERT DO NOT POPLUATE DNP
J19, J24 2
Not Populated
5-pin connectors, BNC
75Ω, right angle
Trompetor
NOPOP-UCBJR220
J20, JB03 2 8-pin single-port RJ48 connectors MOLEX
15-43-8588
J21, J37 2 8-pin connectors (fastjack single, for
national PHY)
Halo Electronics
HFJ11-2450E
J28, J29, J31 3 20-pin headers (dual row, vertical) Samtec
HDR-TSW-110-14-T-D
J38, J39 2 5-pin BNC connectors (75Ω, right angle) Trompetor
UCBJR220
J40, J41 2 5-pin BNC connectors (right angle) Trompetor
UCBJR220
JB01, JB05 2 Sockets, banana plug, horizontal, black Mouser Electronics
164-6218
JB02, JB04 2 Sockets, banana plug, horizontal, red Mouser Electronics
164-6219
JP01–JP11, JPB01 12 100-mil, 3-position jumpers Lab stock
Not applicable
R1, R2 2 1.0kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ103V
R01 1 1.0MΩ ±5%, 1/16W resistor (0603) Panasonic
ERJ-3GEYJ105V
R02 1 10kΩ ±1%, 1/10W resistor (0805) Panasonic
ERJ-6ENF1002V
R03, R04, R05, R09,
R14, R15, R21, RB35,
RB52, RB53, RB58,
RB69, RB70, RB73,
RB77–RB86, RB89,
RB90, RB93–RB96,
RB101, RB132, RB133,
RB137, RB138, RB144,
RB151–RB155, RB159,
RB162
43 30Ω, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ300V
DS33R11DK/DS33ZH11DK
DESIGNATION QTY DESCRIPTION SUPPLIER/PART NUMBER R07, R10, R12, R13,
RB15 5 0Ω ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEY0R00V
R11, RB167 2 10.0kΩ ±1%, 1/16W resistors (0603 ) Panasonic
ERJ-3EKF1002V
R16–R19 4 0Ω ±5%, 1/10W resistors (0805) Panasonic
ERJ-6GEY0R00V
R20, R22 2 330Ω ±5%, 1/8W resistors (1206) Panasonic
ERJ-8ENF3300V
RB01–RB03, RB06–
RB13, RB17, RB18,
RB22, RB25, RB27,
RB28, RB32, RB33
19 10kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ103V
RB04, RB05, RB30,
RB31, RB34, RB36–
RB43, RB59–RB61,
RB63, RB99, RB100,
RB150
20 10kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ103V
RB129 1 30Ω ±5%, 1/16W resistor (0603) Panasonic
ERJ-3GEYJ300V
RB14, RB19, RB44–
RB47, RB49–RB51,
RB54, RB97, RB98,
RB102, RB104, RB116,
RB178
16 2.0kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ202V
RB148, RB149 2 61.9Ω ±1%, 1/10W resistors (0805) Panasonic
ERJ-6ENF61R9V
RB156 1 330Ω ±5%, 1/10W resistor (0805) Panasonic
ERJ-6GEYJ331V
RB16, RB20, RB48,
RB66, RB67, RB68,
RB71, RB74, RB75,
RB135, RB142, RB146,
RB157, RB161, RB165,
RB169, RB174, RB176
18 330Ω ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ331V
RB177 1 51.1Ω ±1%, 1/10W resistor (0805) Panasonic
ERJ-6ENF51R1V
RB21, RB23 2 330Ω ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ331V
RB24 1 1.0kΩ ±5%, 1/16W resistor (0603) Panasonic
ERJ-3GEYJ102V
RB26, RB103, RB105–
RB115, RB117–RB128,
RB130, RB131, RB134,
RB136, RB139–RB141,
RB143, RB163, RB166,
RB170
36 1.0kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ102V
RB29 1 0Ω ±5%, 1/8W resistor (1206) Panasonic
ERJ-8GEYJ0R00V
DS33R11DK/DS33ZH11DK
DESIGNATION QTY DESCRIPTION SUPPLIER/PART NUMBER RB55, RB56, RB57,
RB62, RB64, RB65,
RB72, RB76, RB145,
RB147, RB158, RB160,
RB164, RB168, RB173,
RB175
16 5.1kΩ ±5%, 1/16W resistors (0603) Panasonic
ERJ-3GEYJ512V
RB87, RB91 2 60.4Ω ±1%, 1/10W resistors (0805) Panasonic
ERJ-6ENF60R4V
RB88, RB92, RB171,
RB172 4 54.9Ω ±1%, 1/16W resistors (0603) Panasonic
ERJ-3EKF54R9V
SHORT01 1
2-position SMD jumper
Do not populate. Intended to have
solder bridge during assembly. Not populated
SW01, SW02 2 4-pin single-pole switch Panasonic
EVQPAE04M
T01 1 16-pin dual SMT transformer Pulse Engineering
TX1099
T02, T03 2 6-pin SMT transformers (1:2CT,
transmitter/receiver)
Pulse Engineering
PE-65968
TB01 1 12-pin SMT transformer (1CT:1CT and
1CT:2CT)
Pulse Engineering
PE-68877
TP01–TP03, TPB01–
TPB11, TPP01,TPP02 16 Test points (one plated hole)
Do not stuff. —
U01, U15 2 Microprocessor voltage monitors
2.93V reset, 4-pin SOT143
Maxim
MAX811SEUS-T
U02 1 2Mb SPI serial EEPROM
8-pin SO, 2.7V to 3.6V
Atmel
AT25F2048N-10SU-2.7
U03 1 MMC2107 Processor Motorola
MMC2107
U04 1 FPGA IC
1.2V, 20mm x 20mm, 144-pin TQFP
Lattice Semiconductor
LFEC3E-3T144C
U05, UB03 2 Cypress SRAM, Lab Stock Lab stock
U06, U07 2 High-speed inverters Fairchild Semiconductor
NC7SZ86
U08, UB07 2 1.8V or Adj
8-Pin µMAX/SO
Maxim
MAX1792EUA18
U09 1 DS33R11, Z44/2156 MCM
27mm x 27mm, 256-pin BGA
Dallas Semiconductor
DS33R11
U10, U14 2 DsPHYTER II Single 10/100 Ethernet
transceiver (65-pin LLP)
National Semiconductor
DP83847ALQA56A
DS33R11DK/DS33ZH11DK
DESIGNATION QTY DESCRIPTION SUPPLIER/PART NUMBER U11 1
DS33ZH11 ELITE 10/100 Ethernet
transport over serial link
10mm x 10mm, 100-pin CSBGA
Dallas Semiconductor
DS33ZH11
U12 1 DS21348 LIU 44-pin TQFP Dallas Semiconductor
DS21348
U13 1 DS3150 T3/E3/STS-1 LIU I/F
48-pin TQFP
Dallas Semiconductor
DS3150T
UB01 1 Dual RS-232 transceiver with 3.3V/5V
internal capacitors
Maxim
MAX3233E
UB02 1 LDO regulator with reset,1.20V output
300mA, 6-pin SOT23
Maxim
MAX1963EZT120-T
UB04, UB05 2 Synchronous DRAM, 1Meg x 32 x 4
banks, 86-pin TSOP
Micron
MT48LC4M32B2TG-7
UB06 1 High-speed buffer Fairchild Semiconductor
NC7SZ86
XB01 1 Low-profile 8.0MHz crystal ECL
EC1-8.000M
Y01, YB05 2 Oscillator, crystal clock
3.3V, 2.048MHz (needs socket)
SaRonix
NTH039A3-2.0480
Y02 1
Not populated
Oscillator, crystal clock
3.3V, 25.000MHz (low jitter)
SaRonix
NTH089AA3-25.000
Y03, YB03 2 Oscillator, crystal clock
3.3V, 100.000MHz
SaRonix
NTH089A3-100.0000
Y04 1 SPI serial EEPROM
2.7V, 16k, 8-pin DIP (needs socket)
Atmel
AT25160A-10PI-2.7
Y05 1 Oscillator, crystal clock,
3.3V, 34.368MHz (needs socket)
SaRonix
NTH089AA3-34.368
YB01 1 Oscillator, crystal clock
3.3V, 44.736MHz (needs socket)
SaRonix
NTH089AA3-44.736
YB02 1 Oscillator, crystal clock
3.3V, 1.544MHz (needs socket)
SaRonix
NTH039A3-1.5440
YB04 1 Oscillator, crystal clock
3.3V, 25.000MHz (low jitter)
SaRonix
NTH089AA3-25.000
DS33R11DK/DS33ZH11DK
SYSTEM FLOORPLAN
PC BOARD ERRATA • Center tap of T02 was not pulled to V3_3 in DS33R11DK/DS33ZH11DK01A0 revision (page 23 in schematic).
Pin T02.2 is pulled to V3_3 with a wire in the DS33R11DK/DS33ZH11DK01A0 revision. • Reference designators were assigned for R1, R2 and R01, R02. R1 and R2 will be renamed in the next design. • Component R1, R2 and Y05 are on bottom of the PC board but do not have the same prefix as other
components on the bottom side. • Silkscreen for J36.6 is mislabeled. It reads “RT0” but should read “RT1.” • Oscillators Y03 and YB03 are not suitable for use as input clocks for the Ethernet PHY. Because of this, the
oscillators will only be used as the SDRAM oscillators. These oscillators generate too much jitter to function as
the input clock for the PHY. This requires that the PHY is driven by the default oscillator, YB04 and YB02.
Jumpers JP03 and JP11 have been modified to prevent accidental selection of the wrong oscillator.
MICROPROCESSOR
AND SERIAL PORT
(57600-8-N-1)
TRANSFORMER AND NETWORK
CONNECTIONS (T3E3)
TRANSFORMER AND NETWORK
CONNECTIONS (T1E1)
BACKPLANE JUMPERS—TO DS33ZH11
10/100 ETHERNET PHY AND
MAGNETICS
10/100 ETHERNET PHY AND
MAGNETICS
LEDs
LEDs
LEDs
DS33R11
DS3150
T3E3 LIU CONFIGURATION
JUMPERS
DS3150
T3E3 LIU CONFIGURATION
JUMPERS
EEPROM
(CONFIG)
SDRAM
DS33ZH11 TSER RSER
TCLK RCLK
TRANSFORMER AND NETWORK
CONNECTIONS (T1E1)
SDRAM
TEST POINTS
TEST POINTS
TEST POINTS
DS33R11/DS33ZH11 DESIGN KIT DS33R11 SECTION DS33ZH11 SECTION
DS33R11DK/DS33ZH11DK
FILE LOCATIONS This design kit relies upon several supporting files, which are provided on the CD and are available as a zip file
from the Maxim website at /DS33R11DK.
All locations are given relative to the top directory of the CD/zip file.
Table 1. DS33Z11 Register Definition and Configuration Files
FILE NAME. FILE USAGE .\DS33R11_cfg_demo_gui\DS33Z11.def
Top level definition file to select in
ChipView’s register mode. This file
autoloads the remaining definition files
shown below. (Note: The DS33R11 is
composed of an integrated DS33Z11 and
an integrated DS2155.)
.\DS33R11_cfg_demo_gui\SU_LI_PORT1.def
.\DS33R11_cfg_demo_gui\DS2155.def
Dependant files. These are called by the
DS33Z11.def file, which is listed above.
.\DS33R11_cfg_demo_gui\basic_Config.eset
GUI interface for loading settings when
running the Zchip plug-in (launched from
the Tools menu of the ChipView program).
.\DS33R11_cfg_demo_gui\basic_config.mfg
.\DS33R11_cfg_demo_gui\e1_gapclk_crc4_hdb3_nocas.ini
Files for manually configuring the
DS33Z11 and DS2155 to convert Ethernet
traffic to serial a T1E1 stream.
.\DS33R11_cfg_demo_gui\DS2155_T1_BERT_ESF.ini
.\DS33R11_cfg_demo_gui\gapclk_llb_DS2155_T1_ESF_LBO0_2.ini
Stand-alone configuration files for
evaluating the DS33R11’s integrated
DS2155 T1E1 transceiver. These files are
for evaluating DS2155 functionality, and
disrupt the Ethernet to serial traffic flow.
DS33R11DK/DS33ZH11DK
BASIC OPERATION
Powering Up the Design Kit • Connect PCB 3.3V and GND banana plugs to power supply. A 2A supply is recommended. At steady-state, the
system should draw approximately 700mA. • Verify that jumpers are configured as described in Table 2.
General • Upon power-up, the DS33R11 Queue overflow LED (DS02 red) will not be lit; also, the INT LED (DS01 red) will
not be lit. PHY LINK LED (DS07 green) should be lit if the Ethernet is connected. Transceiver RLOS LED
(DS05 red) will be lit. • DS33ZH11 does not have Queue overflow or INT pins. DS21348 and DS3150 RLOS LEDs (DS15 and DS13
red) will be lit.
Following are several basic system initializations.
Basic DS33R11 Initialization This section covers two basic methods for configuring the DS33R11.
1. Device-Driver Based Configuration. If the pins J09.4+J09.6 are jumpered, the device driver autoconfigures
the DS33R11 upon power-up. This enables traffic to pass from the Ethernet port to the serial port. Consult
the device driver documentation for further details.
2. Register-Based Configuration. Launch ChipView.exe and select Register View. When prompted for a
definition file, pick the file named DS33Z11.def. Three definition files will load: DS33Z11 control, DS33Z11
port, and DS2155 transceiver. Go to the File menu and select File→Memory Config File→Load .MFG file.
When prompted, select the file named
basic_config.mfg. Following this, load the file
e1_gapclk_crc4_hdb3_nocas.ini using the menu selection File→Initalization Config File→Load .INI file.
Additional Configuration for DS33R11 • Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should
cause the link LED to turn on. • Place a loopback connector at the T1E1 network side; RLOS LED DS05 should go out. • At this point any packets sent to the DS33R11 are echoed back. Incoming packets (i.e., ping) should cause the
RX LED to blink, after which the TX LED should also blink.
DS33R11DK/DS33ZH11DK
Basic DS33ZH11 Initialization This section covers the EEPROM methods for configuring the DS33ZH11.
1) If the HWMODE jumper is installed, the DS33ZH11 will retrieve configuration settings from the on-board
EEPROM during power-up.
2) Select which serial device to use: either the DS3150 T3E3 LIU or the DS21348 T1E1 LIU can be selected. In
making this selection the backplane jumpers JP05–JP08 must be installed to select between the two serial
devices. Connecting pins 2+3 of each jumper selects the DS3150, connecting pins 1+2 of each jumper selects
the DS21348.
3) Configure the serial device as shown in Table 2.
Additional Configuration for DS33ZH11 • Using a patch cable, connect the Ethernet connector to an ordinary PC, or network test equipment. This should
cause the link LED to turn on. • Place a loopback connector at the network side; the RLOS LED should go out. The RLOS LED is DS15 for
T1E1 and DS13 for T3E3. • At this point any packets sent to the DS33ZH11 are echoed back. Incoming packets (i.e., ping) should cause
the RX LED to blink, after which the TX LED should also blink.
Monitor and Capture Ethernet Traffic • Although ping is mentioned, it is not recommended. The ping command goes through the computer’s TCPIP
stack, and sometimes is not sent out the PC’s network connector (i.e., if the PC’s ARP cache is out of date).
Additionally, ping requires two PCs, as a PC with only one adapter cannot ping itself (a local ping gets sent to a
local host instead of out the connector). However, note that ping is still a valuable test once the prototyping
stage is complete. • Generation and capture of arbitrary (raw) packets can be accomplished using CommView. A time-limited demo
is available at the website www.tamos.com/products/commview. • Ethereal is an excellent (and free) packet capture utility. Download at www.ethereal.com. • Adding additional Ethernet ports to a PC is rather simple when a USB-to-Ethernet adapter is used. This allows
for end-to-end testing using a single PC. When using two adapters, the PC has a different IP address for each
adapter. Test equipment allows selection of either adapter. Operating system-based network traffic is sent out
the default adapter. Typically, this is the adapter that has recently had connection to a live network.
DS33R11DK/DS33ZH11DK
LEDS, CONFIGURATION SWITCHES, JUMPERS, AND CONNECTORS The DS33Z11DK has several configuration switches, banana plugs, oscillators, and jumpers. Table 2 provides a
description of these signals, given in order of appearance on the PC board, from top to bottom then left to right
(with the board held so that the RS232 connector is on the left edge).
Table 2. Main Board PC Board Configuration
SILKSCREEN
REFERENCE FUNCTION BASIC
SETTING
SCHEMATIC
PAGE DESCRIPTION GROUND
(banana plug) Power supply ground — 2
VDD 3.3V
(banana plug) Power supply VDD — 2
System power. Always connected
to power supply. Connectors are
provided at the top left and bottom
right of board. Connect either set to
power supply.
J01 JTAG — 17 JTAG interface for Lattice EC3
FPGA.
J02 RS-232 DB9
connector — 14 RS-232 DB9 connector, operates in
ASCII mode at 57.6K baud, 8, N, 1.
SW01 Reset 12 Drives reset controller U01.
DS01 LED — 15
Displays interrupt status of
DS33R11 (lit when interrupt is
asserted).
DS02 LED 7
Displays Queue overflow status of
DS33R11 (lit when Queue
overflows).
J04 OnCe BDM — 14 Debug connector for processor.
J03 Flash VPP 3.3V 14 Jumper for driving MMC2107 flash
VPP to 5V .
J05 JTAG — 10 JTAG interface for DS2155 portion
of DS33R11.
J06 JTAG — 11 JTAG interface for DS33Z11
portion of DS33R11.
Y01 Clock — 11 Oscillator for DS2155 portion of the
DS33R11.
J07, J08 Addr / Dat — 16 Address and Databus Test points
for DS33R11.
J09
Configuration pins
(See next two rows
for details.)
Schematic
Page16 Configuration switches for selecting device driver
behavior. Additional detail given below.
J09.2+J09.4 Removed Not installed Pin J09.2 has been removed. Jumpering this pin to
J09.4 causes a conflict with J09.6 FPGA pin.
J09.4+J09.6 Driver Enable Installed Enables device driver and interrupt handler when
jumper is installed.
J09.8+J09.10 RCLK select (FPGA) User selection
Causes device to select serial link TCLK = RCLK
when jumpered. When not jumpered TCLK =
MCLK.
Y02 Ethernet PHY Clock — 3 25.000MHz clock for DS33R11
Ethernet PHY.
JP03 Clock select Pins 1+2
Jumpered 3
Must be set with pins 1+2
jumpered. SDRAM oscillator does
not meet jitter requirement of the
Ethernet PHY.
J10 Jumper Installed 10 Connects DS33R11 receive serial
lines.
J11 Jumper Installed 10 Connects DS33R11 transmit serial
DS33R11DK/DS33ZH11DK
SILKSCREEN
REFERENCE FUNCTION BASIC
SETTING
SCHEMATIC
PAGE DESCRIPTION JP01 3-pin jumper Pins 2+3
jumpered 10 Drives DS33R11 TDEN pin to
VCC.
JP02 3-pin jumper Pins 2+3
jumpered 10 Drives DS33R11 RDEN pin to
VCC.
J18 Test points Pins 9+10 and
5+6 jumpered 10
Test points, connecting RCLK and
TCLK to channel clock pins of
transceiver.
J12, J13 Test points — 11 Test points for integrated
transceiver of DS33R11.
J14, J15, J16 Jumpers Not installed 4
Installation forces Ethernet PHY
mode. When not installed the PHY
autonegotiates its settings.
DS06, DS07,
DS08 LED — 4
Activity LEDs for Ethernet PHY. Tx
lights when PHY sends a packet;
Link lights when the PHY has found
a link partner.
DS10, DS11,
DS09 LED — 4
Ethernet PHY mode LEDs. Used
for display of Speed, Duplex, and
Collision.
J21 LAN network
connection — 5 RJ45 connector for Ethernet PHY.
J22, J23 Test points — 4 Test points for MII interface
between PHY and DS33R11.
J19, J20 J24 WAN Network
Connection — 11 T1E1 coax and RJ45 connectors
for network.
J17, J25 Jumper Not installed 11 Connects adjacent coax connector
to ground.
Y03 Clock — 10 100MHz SDRAM clock for
DS33R11.
J28
Configuration pins
(See next 10 rows for
details.)
Schematic
Page 23 Pin bias for DS3150. When not jumpered, this pin is
pulled to ground, jumper drives pin to VCC. A basic
description of the pin function is given below. Refer
to the data sheet for full detail.
J28.20 DS3150 pin (ZCSE) Not installed
0 = B3ZS/HDB3 encoder/decoder enabled (NRZ
interface enabled)
1 = B3ZS/HDB3 encoder/decoder disabled (bipolar
interface enabled)
J28.18 DS3150 pin (TTS) Installed
0 = tri-state the transmit output driver, disable the
jitter attenuator in the transmit path
1 = enable the transmit output driver, disable the
jitter attenuator in the transmit path
J28.16 DS3150 pin (TESS) Installed 0 = E3
1 = T3 (DS3)
J28.14 DS3150 pin (TDS1) Not installed
J28.12 DS3150 pin (TDS0) Not installed
00=Transmit normal data clocked in on
TPOS/TNRZ and TNEG
11=Transmit PRBS
J28.10 DS3150 pin (RMON) Not installed
0 = disable the monitor preamp, disable the jitter
attenuator in the receive path
1 = enable the monitor preamp, disable the jitter
attenuator in the receive path
J28.8 DS3150 pin (LBKS) Installed 0 = analog loopback enabled
1 = no loopback enabled
J28.6 DS3150 pin (LBO) Installed 0 = cable length 225ft
DS33R11DK/DS33ZH11DK
SILKSCREEN
REFERENCE FUNCTION BASIC
SETTING
SCHEMATIC
PAGE DESCRIPTION J28.4 DS3150 pin (ICE) —
0 = Normal RCLK/Normal TCLK: update
RPOS/RNRZ and RNEG/RLCV on falling edge of
RCLK; sample TPOS/TNRZ and TNEG on rising
edge of TCLK
1 = Normal RCLK/Inverted TCLK: update
RPOS/RNRZ and RNEG/RLCV on falling edge of
RCLK; sample TPOS/TNRZ and TNEG on falling
edge of TCLK
J28.2 DS3150 pin (EFE) Not installed 0 = enhanced features disabled
1 = enhanced features enabled
JP09 Clock selection Pins 3+2
jumpered 23
Selects DS3150 MCLK. Jumper
pins 1+2 for MCLK = RCLK; jumper
pins 3+2 for MCLK = OSC_YB01.
DS12, DS13,
DS14 LED — 23 DS3150 LEDs for PRBS, LOS and
DM.
J38, J39 BNC — 23 DS3150 BNC network interface.
JP05–JP08 Serial backplane User config 18
Jumper pins 1+2 to select
DS21348 T1E1, jumper pins 2+3 to
select DS3150.
J29
Configuration pins
(See next 10 rows for
details.)
Pin bias for DS21348. When not jumpered, this pin
is pulled to ground, jumper drives pin to VCC. A
basic description of the pin function is given below.
Refer to the data sheet for full details.
J29.1 DS21348 pin
(CS_EGL)
0 = -12dB (short haul)
1 = -43dB (long haul)
J29.3 DS21348 pin
(RD_ETS)
0 = E1
1 = T1
J29.5 DS21348 pin
(WR_NRZ)
0 = Bipolar data at RPOS/RNEG and TPOS/TNEG
1 = NRZ data at RPOS and TPOS or TNEG; RNEG
outputs a positive-going pulse when device
receives a BPV, CV, or EXZ
J29.7 DS21348 pin
(ALE/SCLKE)
0 = disable 2.048MHz synchronization transmit and
receive mode
1 = enable 2.048Hz synchronization transmit and
receive mode
J29.9 DS21348 pin (VSM) Should be tied low for 3.3V operation.
J29.11 DS21348 pin (LO) Transmit LIU waveshape select bits. (Refer to the
DS21348 data sheet Table 7-1 and 7-2.)
J29.13 DS21348 pin (DJA) 0 = jitter attenuator enabled
1 = jitter attenuator disabled
J29.15 DS21348 pin
(JAMUX)
E1 (ETS = 0) JAMUX
MCLK = 2.048MHz 0
T1 (ETS = 1)
MCLK = 2.048MHz 1
MCLK = 1.544MHz 0
J29.17 DS21348 pin (JAS) 0 = place the jitter attenuator on the receive side
1 = place the jitter attenuator on the transmit side
J29.19 DS21348 pin (HBE)
Schematic
Page 25 0 = enable HDB3 (E1)/B8ZS (T1)
1 = disable HDB3 (E1)/B8ZS (T1)
DS33R11DK/DS33ZH11DK
SILKSCREEN
REFERENCE FUNCTION BASIC
SETTING
SCHEMATIC
PAGE DESCRIPTION J31
Configuration pins
(See next 10 rows for
details)
Pin bias for DS21348. When not jumpered, this pin
is pulled to ground, jumper drives pin to VCC. A
basic description of the pin function is given below.
Refer to the data sheet for full details.
J31.1 DS21348 pin (MM1)
J31.3 DS21348 pin (MM0)
Monitor mode selection. See Table 2-11 in the
DS21348 data sheet.
J31.5 DS21348 pin
(LOOP1)
J31.7 DS21348 pin
(LOOP0)
Loop 1, Loop 0:
11 = RLB
10 = LLB
01 = ALB
J31.9 DS21348 pin (TX1)
J31.11 DS21348 pin (TX0) Transmit data control (pattern vs. TPOS/TNEG)
J31.13 DS21348 pin (TPD)
0 = normal transmitter operation
1 = powers down the transmitter and tri-states the
TTIP and TRING pins
J31.15 DS21348 pin (CES)
0 = update RNEG/RPOS on rising edge of RCLK;
sample TPOS/TNEG on falling edge of TCLK
1 = update RNEG/RPOS on falling edge of RCLK;
sample TPOS/TNEG on rising edge of TCLK
J31.17 DS21348 pin
(TEST) Set high to tri-state all outputs and I/O pins.
J31.19 DS21348 pin
(PBTS/RT0)
Schematic
Page 25 Selects receive termination in conjunction with RT1.
J36
Configuration pins
(See next three rows
for details.)
Pin bias for DS21348. When not jumpered, this pin
is pulled to ground, jumper drives pin to VCC. A
basic description of the pin function is given below.
Refer to the data sheet for full details.
J36.2 DS21348 pin (L1) Transmit LIU waveshape select bits. (Refer to the
DS21348 data sheet Table 7-1 and 7-2.)
J36.4 DS21348 pin (L2) Transmit LIU waveshape select bits. (Refer to the
DS21348 data sheet Table 7-1 and 7-2.)
J36.6 DS21348 pin (RT1)
The silkscreen on this pin is mislabeled. Should
read RT1 with a function of selecting receive
termination.
JP10 Clock selection 25 —
DS15 LED 25 —
J40, J41 Network connection 24 —
J27 DS33ZH11 pin
(MODEC1) 21 —
J26 DS33ZH11 pin
(HWMODE) 21 —
JPB01 Jumper 21 —
J30, J33 Test points
Schematic
Page 25 26 Test points for MII interface
between PHY and DS33ZH11.
JP11 Clock selection Pins 2+3
jumpered 18
Must be set with pins 1+2
jumpered. SDRAM oscillator does
not meet jitter requirement of the
Ethernet PHY.
J32, J35, J34 Jumpers Not installed 26
Installation forces Ethernet PHY
mode. When not installed, the PHY
autonegotiates its settings
DS33R11DK/DS33ZH11DK
SILKSCREEN
REFERENCE FUNCTION BASIC
SETTING
SCHEMATIC
PAGE DESCRIPTION DS19, DS20,
DS21 LED — 19
Activity LEDs for Ethernet PHY. Tx
lights when PHY sends a packet;
Link lights when the PHY has found
a link partner.
DS16, DS17,
DS18 LED — 19
Ethernet PHY mode LEDs. Used
for display of Speed, Duplex, and
Collision.
SW02 Reset button — 19 —
GROUND
(banana plug) Power supply ground — 2 Redundant power supply
connection (see top left of board).
VDD 3.3V
(banana plug) Power supply VDD — 2 Redundant power supply
connection (see top left of board).
YB01 DS3150 MCLK — 23 44.736MHz, for use with DS3150 in
T3 mode (bottom side of PC board)
YB02 DS21348 MCLK — 25 1.544MHz, for use with DS21348 in
T1 mode (bottom side of PC board)
YB04 Ethernet clock — 18
25.000MHz driver for DS33ZH11
Ethernet PHY (bottom side of PC
board).
YB03 SDRAM clock — 21
100MHz SDRAM clock for
DS33ZH11 (bottom side of PC
board).
YB05 Spare oscillator — 25
2.048MHz, for use with DS21348 in
E1 mode (bottom side of PC
board).
Y05 Spare oscillator — 23
34.368MHz for use with DS3150 in
E3 mode (bottom side of PC
board).
ADDRESS MAP (ALL CARDS) The external device address space begins at 0x81000000. All offsets given below are relative to this offset.
Table 3. Overview of Daughter Card Address Map
OFFSET DEVICE DESCRIPTION 0X0000 to
0X0087 FPGA Processor board identification
0X1000 to
0X1FFF
DS33R11 Ethernet to Serial Engine. Uses
CS_X1.
0X4000 to
0X4FFF
DS33R11
T1E1 portion of DS33R11. Uses CS_X4.
Registers in the DS33R11 can be easily modified using the ChipView host-based user-interface software with the
definition files previously mentioned.
DS33R11 INFORMATION For more information about the DS33R11, refer to the DS33R11 data sheet available on our website at
/DS33R11.
DS33R11DK/DS33ZH11DK
DS33R11DK/DS33ZH11DK INFORMATION For more information about the DS33R11DK/DS33ZH11DK, including software downloads, refer to the data sheet
available on the our website at /DS33R11DK.
TECHNICAL SUPPORT For additional technical support, go to /support.
SCHEMATICS The DS33R11/DS33ZH11DK schematics are featured in the following pages. As this is a hierarchal schematic
some explanation is in order. The board is composed of two top-level hierarchal blocks: the DS33R11 block and
the DS33ZH11, both of these are nested hierarchy blocks. The DS33R11 hierarchy block contains individual
hierarchy blocks for the Ethernet PHY, DS33R11 and microprocessor portions of the design. The DS33ZH11
hierarchy block contains individual hierarchy blocks for the Ethernet PHY, DS33ZH11, T1E1 LIU, and the T3E3 LIU
portions of the design.
All signals inside a hierarchy block are local, with exception for VCC and ground. In-port and out-port connectors are
used to allow signals inside a hierarchy block to become accessible as pins on the hierarchy blocks symbol. From
here blocks are wired together as if they were ordinary components. The system diagram is shown again below,
with schematic page numbers given for each functional block.
DS21348 LIU BLOCK
PAGE 18 SYMBOL
SCHEMATIC
PAGES 24-25
ETHERNET PHY
PAGE 3 SYMBOL
SCHEMATIC
PAGES 04-05
DS3150 LIU BLOCK
PAGE 18 SYMBOL
SCHEMATIC
PAGE 23
ETHERNET PHY
PAGE 18 SYMBOL
SCHEMATIC
PAGES 26-27
DS33ZH11 BLOCK
PAGE 18 SYMBOL
SCHEMATIC
PAGES 20-22
DS33ZH11 BLOCK
PAGE 3 SYMBOL
SCHEMATIC
PAGES 06-11
µP BLOCK
PAGE 3 SYMBOL
SCHEMATIC
PAGES 12-17
DS33R11 SECTION
PAGE 1 TOP LEVEL
OF DESIGN
CONTAINS 34
HIERARCHY
BLOCKS
SCHEMATIC
PAGES 18-27
DS33R11 SECTION
PAGE 1 TOP LEVEL
OF DESIGN
CONTAINS 3
HIERARCHY
BLOCKS
SCHEMATIC
PAGES 03-17
DS33RZH11 PC BOARD LAYOUT & SCHEMATIC HIERARCY BLOCK PAGE LISTING
01:
DS33R11
AND
DS33ZH11
DESIGN
TOP
LEVEL
HIERARCHY
BLOCKS
03:
HIERARCHY
BLOCKS
FOR
DS33R11,
PROCESSOR
AND
ETHERNET
ONLY
SIGNALS
WITH
IMPORT/OUTPORT
CONNECTORS
HAVE
CONNECTION
OUTSIDE
THE
18-19:
HIERARCHY
BLOCKS
FOR
DS33ZH11,
ETHERNET
AND
SERIAL
(WAN)
INTERFACE
04-05:
ETHERNET
PHYSICAL
INTERFACE
(PHY)
06-11:
DS33R11
12-17:
PROCESSOR
CARD
20-22:
DS33ZH11
23:
DS3150
LINE
INTERFACE
UNIT
(LIU)
24-25:
DS21348
LINE
INTERFACE
UNIT
(LIU)
26-27:
ETHERNET
PHYSICAL
INTERFACE
(PHY)
DS33ZH11
TOP
LEVEL
HIERARCHY
BLOCK
PAGES
HIERARCHY
BLOCK
PAGES
DS33R11
TOP
LEVEL
NOTES:
EACH
HIERARCHY
BLOCK
INDEPENDENT
THE
NEXT.
02:
DECOUPLING
MOUNTING
HOLES
DESIGN
DS33R11
DESIGN:
CONTENTS
HIERARCHY
BLOCK.
THESE
SIGNALS
APPEAR
PINS
THE
HIERARCHY
BLOCK
CONNECTOR
PRINTED
Fri
Sep
11:01:48
BLOCK
NAME:
_ztopdn_.
PARENT
BLOCK:
01/05/2005
1/2(BLOCK)
1/27(TOTAL)
STEVE
SCULLY
DS33ZH11-R11DK01A0
FPGA_ZHSPICS
FPGA_ZHSPISCK
FPGA_ZHMISOFPGA_ZHMOSI
FPGA_SPICSZMISOZSPISCKZMOSI
PAGE:DATE:
TITLE:
ENGINEER:
_ds33zh11dk_design
ZMOSIZSPISCKZMISOFPGA_SPICS
_ds33r11dk_design
FPGA_ZHMOSIFPGA_ZHMISO
FPGA_ZHSPISCK
FPGA_ZHSPICS
http://www.ic-phoenix.com/
GROUND
TESTPOINTS
2/2(BLOCK)
STEVE
SCULLY
DS33ZH11-R11DK01A0
2/27(TOTAL)
01/05/2005
BLOCK
NAME:
_ztopdn_.
PARENT
BLOCK:
ABAAA
JB051
JB021
JB011
JB04
CB151
CB175
CB74
CB125
CB127
C14
H03
H04
HB01
H01
HB03
H02
H05
DB01
CB58
CB64
CB131
CB22
CB20
CB54
C03
CB47
CB48
C17
C20
CB132
CB62
C22
CB32
CB19
CB28
CB59
CB60
CB124
CB61
CB31
CB10
CB139
CB38
CB118
CB140
CP01
CP02
CP03
C01
C28
CB136
CB03
C19
CB52
CB100
C16
C18
C12
C08
CB51
CB17
C09
CB75
CB50
CB06
CB18
CB01
CB149
CB150
CB134
CB133
CB53
CB57
CB55
CB107
CB16
CB13
CB116
CB09
CB15
CB35
CB14
CB34
CB05
CB04
CB46
CB138
CB02
CB143
CB142
C23
CB141
CB07
CB147
C21
C24
CB145
CB144
CB08
CB137
CB135
GND_TPP05
GND_TPP04
GND_TPP03
GND_TPP02
GND_TPP09
GND_TPP08
GND_TPP07
GND_TPP06
GND_TPB01
GND_TPP13
GND_TPP12
GND_TPP11
GND_TPP10
GND_TP02
GND_TPP16
GND_TPP15
GND_TPP14
GND_TPP20
GND_TPP19
GND_TP03
GND_TPP18
GND_TPP17
GND_TPP21
GND_TPP22
GND_TP01
GND_TPP23
GND_TPP01
10UF
.1UF
RED
BLACK
BLACK
RED
10UF
470UF
1.00STANDOFF_NUT
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
10UF
10UF
0.1UF
0.1UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
470UF
470UF
10UF
10UF
470UF
470UF
470UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
470UF
10UF
10UF
10UF
10UF
10UF
10UF
10UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
0.1UF
10UF
10UF
10UF
10UF
10UF
10UF
.1UF
PAGE:DATE:
TITLE:
ENGINEER:BB
CONN_BANANA_2PB
V3_3
CONN_BANANA_2PB
V3_3
V3_3
V3_3
http://www.ic-phoenix.com/
PAGES
PAGES
PAGES
HIERARCHY
BLOCK
R11
HIERARCHY
BLOCK
MII
ETHERNET
HIERARCHY
BLOCK
DS33R11
DESIGN
KIT
(BOTTOM
RIGHT)
ARE
LISTED
BOTH
THE
PAGE
NUMBER
THE
BLOCK,
AND
THE
PAGE
NUMBER
WITHIN
THE
ENTIRE
DESIGN
ALL
HIERARCHY
BLOCK
NAMES
END
_DN.
PINS
HIERARCHY
BLOCKS
NOT
HAVE
PIN
NUMBERS
(BUT
PINS
SYMBOLS
DO).
INSIDE
HIERARCHY
BLOCK
ARE
LOCAL
THAT
BLOCK
THE
SIGNAL
TEMP
BLOCK_A_DN
DIFFERENT
THAN
TEMP
BLOCK_B_DN.
REFERENCE
INDICATORS
ARE
REFERENCEING
GIVEN
NET
OTHER
PAGES
THE
DESIGN
(PAGE
NUMBER
GIVEN
ACCORDING
ENTIRE
DESIGN,
NOT
THE
CURRENT
BLOCK)
DS33ZH11-R11DK01A0
01/05/2005
STEVE
SCULLY
BLOCK
NAME:
_ds33r11dk_design.
PARENT
BLOCK:
\_ztopdn_\
3/27(TOTAL)
1/1(BLOCK)
PRINTED
Sat
Sep
15:05:43
TXD0
MII_CLK
MDC
MDIO
TXD1TXD2TXD3
TX_CLK
RXDVCOL_DET
RX_CRSRX_ERRRX_CLK
LED_DPLX_ADD0
LED_COL_ADD1
LED_GDLINK_ADD2
LED_RX_ADD4LED_TX_ADD3
RXD0RXD3RXD2RXD1
TX_EN
RESET
CS_ETHCS_SERRDDAT<7..0>ADDR<9..0>
REF_CLK_IN
MDIO
RST_SERIAL
RST_ETH
COL_DET
TXD0
TX_EN
INT
RXD0RXD1RXD2RXD3
RX_CLKRX_CRSRX_ERR
RXDV
TXD1
REF_CLKO_PN
TXD2TXD3
TX_CLK
MDC
FPGA_ZHSPISCKFPGA_ZHSPICSFPGA_ZHMOSI
RESET
RD_DUTWR_DUT
INT3
CS_X1CS_X2CS_X5
INT4INT5
CS_X3CS_X4
D_DUT<7..0>
RESET_AH
INT2
a_dut_<9..0>
FPGA_ZHMISO
RESET
TX_ENRXD1RXD2RXD3RXD0
LED_TX_A3LED_RX_A4LED_GDLINK_A2LED_COL_A1LED_DPLX_A0
RX_CLKRX_ERRRX_CRSCOL_DETRXDVTX_CLKTXD3TXD2TXD1
MDIO
MDC
TXD0
I25
DAT<7..0>
Y02
JP03
R04
R05
DS08DS06
RB57
RB68
DS07
RB66
RB55
RB67
DS09
RB56
RB75
RB72
DS11
RB71
RB76
ADDR<9..0>RD
CS_ETH
INT
I28
I34
RST_SERIAL
RESET
REF_CLKO
REF_CLK_IN
MDC
RESET
MDIO
CS_SER
I32NPOP-25.000MHZ_3.3V
I30I20
AMBER
5.1K
LED_GDLINK_A2
5.1K
AMBER
5.1K
AMBER
5.1K
GREEN
5.1K
RED
LED_DPLX_A0
LED_COL_A1
LED_TX_A3
LED_RX_A4
GND
V3_3
I11
I15
I19
I21I22
PAGE:DATE:
TITLE:
ENGINEER:
_motprocrescard_dnFPGA_ZHMISO
a_dut_<9..0>
INT2
RESET_AH
D_DUT<7..0>
CS_X4CS_X3
INT5INT4
CS_X5CS_X2CS_X1
INT3
WR_DUTRD_DUT
RESET
FPGA_ZHMOSIFPGA_ZHSPICSFPGA_ZHSPISCK
VCC
OSC
GND
OUT
V3_3
_z11andlan_dn
MDC
TX_CLK
TXD3TXD2
REF_CLKO_PN
TXD1
RXDV
RX_ERRRX_CRSRX_CLK
RXD3RXD2RXD1RXD0
INT
TX_EN
TXD0
COL_DET
RST_ETH
RST_SERIAL
MDIO
REF_CLK_IN
ADDR<9..0>DAT<7..0>RDCS_SERCS_ETH
_mii_wan_dn
RESET
TX_EN
RXD1RXD2RXD3RXD0
LED_TX_ADD3LED_RX_ADD4
LED_GDLINK_ADD2
LED_COL_ADD1
LED_DPLX_ADD0
RX_CLKRX_ERRRX_CRS
COL_DETRXDV
TX_CLK
TXD3TXD2TXD1
MDIO
MDC
MII_CLK
TXD0
V3_3
V3_3
http://www.ic-phoenix.com/
BEGINNING
MII
ETHERNET
HIERARCHY
BLOCK
PLACEMENT
NOTE:
LEDS
NEED
ATTACHED
OUTSIDE
MODULE
DUE
CLOSE
PIN
RBIAS
MUST
FOR
TESTPOINTS
(SHOWN
ABOVE)
MUST
PLACED
THE
SAME
FOR
EACH
PORT
BETWEEN
CONNECTORS.
ALLOW
USE
DIFFERENT
PHY
CARD
DESIRED.
PLACEMENT
SHOULD
ALLOW
Z44
CARD
ALL
PORTS
MUST
PLACED
WITH
EQUAL
SPACING
AND
COMMON
CENTER
LINE
STRAP
ADAPTING
OPTION
DP83847
ANALOG
SUPPLY
CAPS
PLACED
CLOSE
PIN
PHY
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_ds33r11dk_design\
4/27(TOTAL)
PRINTED
Fri
Sep
11:01:50
DS33ZH11-R11DK01A0
STEVE
SCULLY
01/05/2005
1/2(BLOCK)
RESERVED12
RESERVED13
RESERVED16
RESERVED17
RESERVED18
GND1
GND2
GND3
GND4
GND5
RESERVED10RESERVED11
RESERVED4
RESERVED5
RESERVED6
RESERVED7
RESERVED8
RESERVED9
VDD/IO_VDD1
VDD/IO_VDD2
VDD/ANA_VDD
VDD1
VDD2
VDD3
RESERVED2RESERVED1RBIASRESET*C1X2X1
AN_0AN_1
AN_EN
LED_SPEED
LED_RX/PHYAD4
LED_COL/PHYAD1
LED_DPLX/PHYAD0
MDIO
MDC
RESERVED3
LED_GDLNK/PHYAD2
LED_TX/PHYAD3
RESERVED15
RESERVED14
0.1UF
CM98
CM32
0.1UF
CP15
0.1UF
CM82
CP09
10UF
AN0AN1AN_EN
AMBER
CM77
AN_V3_3
CP08
CM75
CM29
CM89
JP24
JP25
RM36RM35RM34
TPP01
RM24
TPP02
RP11
UP15
CP07
RM02
LED_DPLX_ADD0
LED_TX_ADD3
10.0K
RESET
0.1UF
MII_CLK
LED_COL_ADD1
LED_RX_ADD4
RBIAS
AN_V3_3
C1PIN
0.1UF
0.1UF
5.1K
TX_EN
TX_CLK
COL_DET
RX_CRS
RXD3RXD2RXD1
RX_CLKRX_ERR
RXD0
RXDV
5.1K
MDC
MDIO30
TXD1TXD0TXD3TXD2
0.1UF
0.1UF
10UF
CP17
10UF
10UF
0.1UF
CM67
LED_SPEED<1>
LED_GDLINK_ADD2
5.1K
JMP_2JMP_2JMP_2
PAGE:DATE:
TITLE:
ENGINEER:
V3_3479
CONN_10P
OUTOUTOUTOUT
OUTOUTOUTOUTOUT479
CONN_10P
OUTININ
V3_3IN
CONTROL
DP83847_U1
RESERVED14
RESERVED15
LED_TX/PHYAD3
LED_GDLNK/PHYAD2
RESERVED3
MDC
MDIO
LED_DPLX/PHYAD0
LED_COL/PHYAD1
LED_RX/PHYAD4
LED_SPEED
AN_EN
AN_1AN_0X2C1RESET*RBIASRESERVED1RESERVED2
VDD3
VDD2
VDD1
VDD/ANA_VDD
VDD/IO_VDD2
VDD/IO_VDD1
RESERVED9
RESERVED8
RESERVED7
RESERVED6
RESERVED5
RESERVED4
RESERVED11RESERVED10
GND5
GND4
GND3
GND2
GND1
RESERVED18
RESERVED17
RESERVED16
RESERVED13
RESERVED12
V3_3IOIOIOIO
http://www.ic-phoenix.com/
RESISTORS
FOR
TD+-/RD+-
SHOULD
PLACED
CLOSE
XFRM
SHOULD
PLACED
CLOSE
PHY
END
MII
ETHERNET
HIERARCHY
BLOCK
CAPS
FOR
XFRM
CENTER
TAP
BLOCK
NAME:
_mii_wan_dn.
PARENT
BLOCK:
\_ds33r11dk_design\
5/27(TOTAL)
2/2(BLOCK)
STEVE
SCULLY
DS33ZH11-R11DK01A0
01/05/2005
SH1P8P6P3P4
SH2P5
COL
TXD<2>RD+RD-RXD<3>TXD<3>
RX_CLK
RXD<1>RXD<0>RXD<2>
TD-TD+
CRS/LED_CFG*
TX_CLK
TX_ERTX_ENTXD<0>TXD<1>
RX_DV
RX_ER/PAUSE_EN*
TD_N
.1UF
.1UF
RXDV
TD_PTD_N
COL_DET
RX_CRS30
.1UF
RD_N
TD_P
RD_P
SYM_1
TXD330
TXD2TXD1TXD0TX_EN
RX_ERR30
TX_CLKRX_CLK
UP15
CM59
JP21
RM10
CP12
RM06
RM21RM03
RP08
RM05RM08
RP06
RM13RM09
CM63
RM12RM14
PAGE:DATE:
TITLE:
ENGINEER:
PORT
DP83847_U1
RX_ER/PAUSE_EN*
RX_DV
TXD<1>TXD<0>TX_ENTX_ER
TX_CLK
CRS/LED_CFG*
TD+TD-
RXD<2>RXD<0>RXD<1>
RX_CLK
TXD<3>RXD<3>RD-RD+TXD<2>
COL
V3_3
CONN_HFJ11_2450_UJ2J3J6
J4,5J7,8P1
SH2P3P6P8P2
SH1
http://www.ic-phoenix.com/
