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DS33R11
Ethernet Mapper with Integrated T1/E1/J1 Transceiver
Note: Some revisions of this device may incorporate deviations from published specifications known as errata. Multiple revisions of any device
GENERAL DESCRIPTION The DS33R11 extends a 10/100 Ethernet LAN
segment by encapsulating MAC frames in HDLC or X.86 (LAPS) for transmission over a T1/E1/J1 data stream.
The device performs store-and-forward of packets with full wire-speed transport capability. The built-in
Committed Information Rate (CIR) Controller provides fractional bandwidth allocation up to the line rate in increments of 512kbps. The DS33R11 can
operate with an inexpensive external processor.
APPLICATIONS Transparent LAN Service
LAN Extension Ethernet Delivery Over T1/E1/J1
FUNCTIONAL DIAGRAM
FEATURES ��10/100 IEEE 802.3 Ethernet MAC (MII and RMII) Half/Full Duplex with Automatic Flow Control
��Integrated T1/E1/J1 Framer and LIU
��HDLC/LAPS Encapsulation with Programmable FCS and Interframe Fill
��Committed Information Rate Controller Provides Fractional Allocations in 512kbps Increments
��Programmable BERT for Serial (TDM) Interface
��External 16MB, 100MHz SDRAM Buffering
��Parallel Microprocessor Interface
��1.8V, 3.3V Supplies
��Reference Design Routes on Two Signal Layers
��IEEE 1149.1 JTAG Support
Features continued on page 11.
ORDERING INFORMATION
DS33R11
Ethernet Mapper with Integrated
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
TABLE OF CONTENTS DESCRIPTION...............................................................................................................................9 FEATURE HIGHLIGHTS..............................................................................................................11 2.1 GENERAL..................................................................................................................................11
2.2 MICROPROCESSOR INTERFACE..................................................................................................11 2.3 HDLC ETHERNET MAPPING.......................................................................................................11
2.4 X.86 (LINK ACCESS PROTOCOL FOR SONET/SDH) ETHERNET MAPPING....................................11
2.5 ADDITIONAL HDLC CONTROLLERS IN THE INTEGRATED T1/E1/J1 TRANSCEIVER..........................12 2.6 COMMITTED INFORMATION RATE (CIR) CONTROLLER..................................................................12
2.7 SDRAM INTERFACE..................................................................................................................12
2.8 MAC INTERFACE.......................................................................................................................12
2.9 T1/E1/J1 LINE INTERFACE.........................................................................................................13 2.10 CLOCK SYNTHESIZER................................................................................................................13
2.11 JITTER ATTENUATOR.................................................................................................................13
2.12 T1/E1/J1 FRAMER....................................................................................................................14 2.13 TDM BUS.................................................................................................................................14
2.14 TEST AND DIAGNOSTICS............................................................................................................15
2.15 SPECIFICATIONS COMPLIANCE...................................................................................................16
APPLICATIONS...........................................................................................................................17 ACRONYMS AND GLOSSARY....................................................................................................18 MAJOR OPERATING MODES.....................................................................................................19 BLOCK DIAGRAMS.....................................................................................................................20 PIN DESCRIPTIONS....................................................................................................................25 7.1 PIN FUNCTIONAL DESCRIPTION..................................................................................................25
FUNCTIONAL DESCRIPTION.....................................................................................................41 8.1 PROCESSOR INTERFACE....................................................................................................42 8.1.1 Read-Write / Data Strobe Modes........................................................................................................42
8.1.2 Clear on Read.....................................................................................................................................42 8.1.3 Interrupt and Pin Modes......................................................................................................................42
ETHERNET MAPPER..................................................................................................................43 9.1 ETHERNET MAPPER CLOCKS.....................................................................................................43
9.1.1 Ethernet Interface Clock Modes..........................................................................................................45 9.1.2 Serial Interface Clock Modes..............................................................................................................45
9.2 RESETS AND LOW POWER MODES.............................................................................................46 9.3 INITIALIZATION AND CONFIGURATION..........................................................................................47
9.4 GLOBAL RESOURCES................................................................................................................47
9.5 PER-PORT RESOURCES............................................................................................................47
9.6 DEVICE INTERRUPTS.................................................................................................................48 9.7 INTERRUPT INFORMATION REGISTERS........................................................................................50
9.8 STATUS REGISTERS..................................................................................................................50
9.9 INFORMATION REGISTERS..........................................................................................................50
9.10 SERIAL INTERFACE....................................................................................................................50 9.11 CONNECTIONS AND QUEUES......................................................................................................51
9.12 ARBITER...................................................................................................................................52
9.13 FLOW CONTROL........................................................................................................................53 9.13.1 Full Duplex Flow Control.....................................................................................................................54
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
9.14 ETHERNET INTERFACE PORT......................................................................................................56
9.14.1 DTE and DCE Mode............................................................................................................................58 9.15 ETHERNET MAC.......................................................................................................................59
9.15.1 MII Mode Options................................................................................................................................61 9.15.2 RMII Mode...........................................................................................................................................61
9.15.3 PHY MII Management Block and MDIO Interface...............................................................................62
9.16 BERT IN THE ETHERNET MAPPER..............................................................................................62 9.16.1 Receive Data Interface........................................................................................................................63
9.16.2 Repetitive Pattern Synchronization.....................................................................................................64 9.16.3 Pattern Monitoring...............................................................................................................................64
9.16.4 Pattern Generation..............................................................................................................................64 9.17 TRANSMIT PACKET PROCESSOR................................................................................................65
9.18 RECEIVE PACKET PROCESSOR..................................................................................................66
9.19 X.86 ENCODING AND DECODING................................................................................................68
9.20 COMMITTED INFORMATION RATE CONTROLLER.............................................................71
10 INTEGRATED T1/E1/J1 TRANSCEIVER.....................................................................................72 10.1 T1/E1/J1 CLOCKS....................................................................................................................72
10.2 PER-CHANNEL OPERATION........................................................................................................73
10.3 T1/E1/J1 TRANSCEIVER INTERRUPTS........................................................................................73
10.4 T1 FRAMER/FORMATTER CONTROL AND STATUS...........................................................74 10.4.1 T1 Transmit Transparency..................................................................................................................74
10.4.2 AIS-CI and RAI-CI Generation and Detection.....................................................................................74 10.4.3 T1 Receive-Side Digital-Milliwatt Code Generation............................................................................75
10.5 E1 FRAMER/FORMATTER CONTROL AND STATUS........................................................................76
10.5.1 Automatic Alarm Generation...............................................................................................................77 10.6 PER-CHANNEL LOOPBACK.........................................................................................................77
10.7 ERROR COUNTERS....................................................................................................................78 10.7.1 Line-Code Violation Counter (TR.LCVCR)..........................................................................................78
10.7.2 Path Code Violation Count Register (TR.PCVCR)..............................................................................79
10.7.3 Frames Out-of-Sync Count Register (TR.FOSCR).............................................................................80 10.7.4 E-Bit Counter (TR.EBCR)....................................................................................................................80
10.8 DS0 MONITORING FUNCTION.....................................................................................................81 10.9 SIGNALING OPERATION..............................................................................................................82
10.9.1 Processor-Based Receive Signaling...................................................................................................82
10.9.2 Hardware-Based Receive Signaling....................................................................................................83 10.9.3 Processor-Based Transmit Signaling..................................................................................................84
10.9.4 Hardware-Based Transmit Signaling...................................................................................................85 10.10 PER-CHANNEL IDLE CODE GENERATION.....................................................................................86
10.10.1 Idle-Code Programming Examples.....................................................................................................87 10.11 CHANNEL BLOCKING REGISTERS................................................................................................88
10.12 ELASTIC STORES OPERATION....................................................................................................88
10.12.1 Receive Elastic Store..........................................................................................................................88 10.12.2 Transmit Elastic Store.........................................................................................................................89
10.12.3 Elastic Stores Initialization...................................................................................................................89 10.12.4 Minimum Delay Mode..........................................................................................................................89
10.13 G.706 INTERMEDIATE CRC-4 UPDATING (E1 MODE ONLY).........................................................90
10.14 T1 BIT-ORIENTED CODE (BOC) CONTROLLER............................................................................91 10.14.1 Transmit BOC......................................................................................................................................91
10.15 RECEIVE BOC..........................................................................................................................91
10.16 ADDITIONAL (SA) AND INTERNATIONAL (SI) BIT OPERATION (E1 ONLY)........................................92 10.16.1 Method 1: Internal Register Scheme Based on Double-Frame...........................................................92
10.16.2 Method 2: Internal Register Scheme Based on CRC4 Multiframe......................................................92 10.17 ADDITIONAL HDLC CONTROLLERS IN T1/E1/J1 TRANSCEIVER....................................................93
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
10.17.3 HDLC Mapping....................................................................................................................................95 10.17.4 FIFO Information.................................................................................................................................96
10.17.5 Receive Packet-Bytes Available.........................................................................................................96
10.18 LEGACY FDL SUPPORT (T1 MODE)............................................................................................97 10.18.1 Overview.............................................................................................................................................97
10.18.2 Receive Section..................................................................................................................................97 10.18.3 Transmit Section.................................................................................................................................98
10.19 D4/SLC-96 OPERATION............................................................................................................98
10.20 PROGRAMMABLE IN-BAND LOOP CODE GENERATION AND DETECTION..........................................99 10.21 LINE INTERFACE UNIT (LIU).....................................................................................................100
10.21.1 LIU Operation....................................................................................................................................100 10.21.2 Receiver............................................................................................................................................100
10.21.3 Transmitter........................................................................................................................................102
10.22 MCLK PRESCALER.................................................................................................................103 10.23 JITTER ATTENUATOR...............................................................................................................103
10.24 CMI (CODE MARK INVERSION) OPTION....................................................................................103
10.25 RECOMMENDED CIRCUITS........................................................................................................104 10.26 T1/E1/J1 TRANSCEIVER BERT FUNCTION........................................................................108
10.26.1 BERT Status......................................................................................................................................108
10.26.2 BERT Mapping..................................................................................................................................108 10.26.3 BERT Repetitive Pattern Set.............................................................................................................110
10.26.4 BERT Bit Counter..............................................................................................................................110 10.26.5 BERT Error Counter..........................................................................................................................110
10.26.6 BERT Alternating Word-Count Rate.................................................................................................110 10.27 PAYLOAD ERROR-INSERTION FUNCTION (T1 MODE ONLY).........................................................111
10.27.1 Number-of-Errors Registers..............................................................................................................111
10.28 PROGRAMMABLE BACKPLANE CLOCK SYNTHESIZER..................................................................112 10.29 FRACTIONAL T1/E1 SUPPORT..................................................................................................112
10.30 T1/E1/J1 TRANSMIT FLOW DIAGRAMS.....................................................................................113
11 DEVICE REGISTERS.................................................................................................................117 11.1 REGISTER BIT MAPS................................................................................................................118
11.1.1 Global Ethernet Mapper Register Bit Map.........................................................................................118 11.1.2 Arbiter Register Bit Map....................................................................................................................119
11.1.3 BERT Register Bit Map.....................................................................................................................119 11.1.4 Serial Interface Register Bit Map.......................................................................................................120
11.1.5 Ethernet Interface Register Bit Map..................................................................................................122 11.1.6 MAC Register Bit Map.......................................................................................................................123
11.2 GLOBAL REGISTER DEFINITIONS FOR ETHERNET MAPPER.........................................................130 11.3 ARBITER REGISTERS...............................................................................................................139
11.3.1 Arbiter Register Bit Descriptions.......................................................................................................139
11.4 BERT REGISTERS..................................................................................................................140 11.5 SERIAL INTERFACE REGISTERS................................................................................................147
11.5.1 Serial Interface Transmit and Common Registers............................................................................147
11.5.2 Serial Interface Transmit Register Bit Descriptions...........................................................................147 11.5.3 Transmit HDLC Processor Registers................................................................................................148
11.5.4 X.86 Registers...................................................................................................................................155 11.5.5 Receive Serial Interface....................................................................................................................157
11.6 ETHERNET INTERFACE REGISTERS...........................................................................................170 11.6.1 Ethernet Interface Register Bit Descriptions.....................................................................................170
11.6.2 MAC Registers..................................................................................................................................182
11.7 T1/E1/J1 TRANSCEIVER REGISTERS........................................................................................197 11.7.1 Number-of-Errors Left Register.........................................................................................................293
12 FUNCTIONAL TIMING...............................................................................................................294
DS33R11 Ethernet Mapper with Integrated T1/E1/J1 Transceiver
12.2 MII AND RMII INTERFACES......................................................................................................295
12.3 TRANSCEIVER T1 MODE FUNCTIONAL TIMING...........................................................................297 12.4 E1 MODE...............................................................................................................................302
13 OPERATING PARAMETERS.....................................................................................................307 13.1 THERMAL CHARACTERISTICS...................................................................................................308
13.2 MII INTERFACE........................................................................................................................309
13.3 RMII INTERFACE.....................................................................................................................311
13.4 MDIO INTERFACE...................................................................................................................313 13.5 TRANSMIT WAN INTERFACE....................................................................................................314
13.6 RECEIVE WAN INTERFACE......................................................................................................315
13.7 SDRAM TIMING......................................................................................................................316 13.8 MICROPROCESSOR BUS AC CHARACTERISTICS........................................................................318
13.9 AC CHARACTERISTICS: RECEIVE-SIDE.....................................................................................321
13.10 AC CHARACTERISTICS: BACKPLANE CLOCK TIMING..................................................................325
13.11 AC CHARACTERISTICS: TRANSMIT SIDE...................................................................................326 13.12 JTAG INTERFACE TIMING........................................................................................................329
14 JTAG INFORMATION................................................................................................................330 14.1 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION..........................................................331
14.2 INSTRUCTION REGISTER..........................................................................................................333
14.3 JTAG ID CODES.....................................................................................................................335 14.4 TEST REGISTERS....................................................................................................................335
14.4.1 Boundary Scan Register...................................................................................................................335
14.4.2 Bypass Register................................................................................................................................335 14.4.3 Identification Register........................................................................................................................335
14.5 JTAG FUNCTIONAL TIMING......................................................................................................336
15 PACKAGE INFORMATION........................................................................................................337 15.1 PACKAGE OUTLINE DRAWING OF 256-BGA (VIEW FROM BOTTOM OF DEVICE)...........................337
16 REVISION HISTORY..................................................................................................................338
