DS33M33N+ ,Ethernet Over SONET/SDH MapperFeatures ♦ Support for EoS in One STS-3c/VC-4, EoS The DS33M30 family of products provides a compac ..
DS33R11 ,Ethernet Mapper with Integrated T1/E1/J1 TransceiverFEATURES 10/100 IEEE 802.3 Ethernet MAC (MII and RMII) The DS33R11 extends a 10/100 Ethernet LAN ..
DS33R11+ ,Ethernet Mapper with Integrated T1/E1/J1 TransceiverTABLE OF CONTENTS 1 DESCRIPTION ..... 9 2 FEATURE HIGHLIGHTS...... 11 2.1 GENERAL........ 11 2.2 MI ..
DS33R11DK ,Ethernet Transport Design KitGENERAL DESCRIPTION The DS33R11/DS33ZH11 design kit is an easy-to- Demonstrates Key Functions of D ..
DS33R41 ,Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 TransceiversTABLE OF CONTENTS 1 DESCRIPTION ..... 9 2 FEATURE HIGHLIGHTS...... 11 2.1 GENERAL........ 11 2.2 MI ..
DS33R41+ ,Inverse-Multiplexing Ethernet Mapper with Quad Integrated T1/E1/J1 TransceiversAPPLICATIONS μC ETHERNET Bonded Transparent LAN Service MAPPER LAN Extension SDRAM Ethernet Deliv ..
EB2-12 ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEFEATURESª Compact and lightweight : 7.5 mm · 14.3 mm · 9.3 mm, 1.5 gª 2 form c contact arrangementª ..
EB2-12NU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
EB2-12TNU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
DS33M33N+
Ethernet Over SONET/SDH Mapper
Maxim Integrated Products 1 DS33M30/DS33M31/DS33M33 Ethernet Over SONET/SDH Mapper
________________________ General Description The DS33M30 family of products provides a compact
and efficient solution for transporting Gigabit Ethernet
traffic over OC-3/STM-1 optical networks. With the
addition of an optical transceiver, Ethernet PHY,
DDR SDRAM, and host processor, a complete
solution of GbE over OC-3/STM-1 can be
implemented. The family supports Ethernet over
SONET/SDH (EoS) at VC-4, “Next-Generation” EoS
high-order mapping with multiple concatenated
VC-3s, and Ethernet over PDH over SONET/SDH
(EoPoS) with up to three virtually concatenated
DS3/E3 tributaries. The supported frame
encapsulations include GFP-F, HDLC, cHDLC, and
X.86 (LAPS).
_______________________________ Applications Ethernet Service Delivery Over SONET/SDH
Multiservice Provisioning Platforms (MSPPs)
Transparent LAN Services
LAN Extension
_____________________________________Features ♦
Support for EoS in One STS-3c/VC-4, EoS
Over Up to Three Concatenated STS-1/VC-3s,
and EoPoS Over Up to Three Concatenated
DS-3s ♦
Two Independent 155.52Mbps SerDes Ports ♦
One 10/100/1000 IEEE 802.3 Ethernet MAC
Port ♦
Configurable MII/RMII/GMII MAC Interface ♦
GFP/LAPS/HDLC/cHDLC Encapsulation ♦
IEEE 802.1Q VLAN and Q-in-Q Support ♦
Add/Drop OAM Frames from µP Interface ♦
Quality of Service (QoS) Support ♦
Traffic Policing Through CIR/CBS ♦
Classification Through PCP or DSCP ♦
Supports Up to 512Mb DDR SDRAM Buffer ♦
SPI and Parallel Microprocessor Interfaces ♦
1.8V, 2.5V, 3.3V Supplies
Features continued in Section 1.
_________________________ Functional Diagram
____________________________________________________________ Ordering Information/Selector Guide
PART SUPPORTED EoS/EoPoS
MODES 155Mbps PORTS EXT. DS3/E3 LINE PIN-PACKAGE
DS33M30N+ EoS at VC-4 1 No 144 CSBGA
DS33M31N+ EoS at VC-4,
EoS at 3xVC-3,
EoPoS at 3xDS3 No 256 CSBGA
DS33M33N+ EoS at VC-4,
EoS at 3xVC-3,
EoPoS at 3xDS3 Yes (3) 256 CSBGA
+Denotes a lead(Pb)-free/RoHS-compliant package.
Rev 1; 010809
CAS
DS3/E3
Framers
HDL
C /
ffi
van
ced
t M
ram3x VC-3
SER
ES ADS33M30/M31/M33 DS3 ADD/DROP (DS33M33 ONLY)
1 VC-4
SER
ES BSerDes B AND FRAMER B ON
(DS33M31/33 ONLY)
DS33M30/M31/M33 DATA SHEET Table of Contents
1. GENERAL DESCRIPTION AND FEATURE HIGHLIGHTS ........................................................... 4
1.1 DEVICE FEATURE OVERVIEW ........................................................................................................ 5
1.2 TDM FEATURE OVERVIEW ............................................................................................................ 6
1.3 SONET/SDH............................................................................................................................... 7
1.3.1 STS-3/STM-1 SerDes ....................................................................................................................... 7
1.3.2 STS-3/STM-1 Framer and Formatter ................................................................................................. 7
1.3.3 STS-3c/AU-4 Pointer Processing ...................................................................................................... 8
1.3.4 STS-3c SPE/VC-4 Path Termination ................................................................................................. 8
1.3.5 STS-3 Mux/Demux (DS33M31 and DS33M33 Only) .......................................................................... 8
1.3.6 STS-1/AU-3/TU-3 Formatter and Framer (DS33M31 and DS33M33 Only) ......................................... 9
1.3.7 STS-1/AU-3/TU-3 Pointer Processing (DS33M31 and DS33M33 only) .............................................. 9
1.3.8 STS-1/VC-3 Path Termination (DS33M31 and DS33M33 only) ........................................................ 10
1.4 PDH (DS33M31 AND DS33M33 ONLY) ...................................................................................... 12
1.4.1 Add/Drop DS3/E3 Framer/Formatter (DS33M31 and DS33M33 only) .............................................. 12
1.4.2 DS3/E3 Ethernet Mapping (DS33M31 and DS33M33 only) ............................................................. 13
1.4.3 Line DS3/E3 Framer/Formatter (DS33M33 only) ............................................................................. 13
1.4.4 Loopback ........................................................................................................................................ 14
1.5 VIRTUAL CONCATENATION (VCAT) (DS33M31 AND DS33M33 ONLY) ........................................... 14
1.5.1 SONET/SDH VCAT/LCAS .............................................................................................................. 14
1.5.2 PDH VCAT/LCAS ........................................................................................................................... 15
1.6 ENCAPSULATION ........................................................................................................................ 15
1.6.1 GFP-F Encapsulation (per ITU-T G.7041) ....................................................................................... 15
1.6.2 HDLC Encapsulation ....................................................................................................................... 15
1.6.3 cHDLC Encapsulation ..................................................................................................................... 15
1.6.4 X.86 Encapsulation Support ............................................................................................................ 15
1.7 ETHERNET FEATURE OVERVIEW .................................................................................................. 15
1.7.1 Ethernet MAC Interface ................................................................................................................... 16
1.7.2 Ethernet Bridging for 10/100............................................................................................................ 16
1.7.3 Ethernet Traffic Classification .......................................................................................................... 16
1.7.4 Ethernet Traffic Profiling and Policing .............................................................................................. 16
1.7.5 Ethernet Traffic Scheduling ............................................................................................................. 16
1.7.6 Ethernet Control Frame Processing................................................................................................. 16
1.7.7 Q-in-Q............................................................................................................................................. 16
1.8 SDRAM INTERFACE ................................................................................................................... 16
1.9 CLOCK RATE ADAPTER (CLAD) .................................................................................................. 16
1.10 SPI SERIAL MICROPROCESSOR FEATURES ............................................................................... 17
1.11 PARALLEL MICROPROCESSOR INTERFACE (DS33M31 AND DS33M33 ONLY) ............................. 17
1.12 TEST AND DIAGNOSTICS .......................................................................................................... 17
2. STANDARDS COMPLIANCE...................................................................................................... 18
3. APPLICATIONS .......................................................................................................................... 20
4. REVISION HISTORY ................................................................................................................... 21
DS33M30/M31/M33 DATA SHEET List of Figures
Figure 1-1 TDM Functional Blocks ......................................................................................................................... 6
Figure 3-1. Example Application 1: EoS for DS33M30 .......................................................................................... 20
Figure 3-2. Example Application 2: EoPoS for DS33M31 Interworking with EoP in DS33X162 Family of Devices . 20
Figure 3-3. Example Application 3: EoPoS Transport for DS33M33 with Integrated Ethernet and PDH Services... 20
List of Tables
Table 1-1. Product Selection Matrix........................................................................................................................ 5
Table 1-2. Summary of Mapping Functions ............................................................................................................ 5
Table 2-1. Standards Compliance Summary ........................................................................................................ 18
DS33M30/M31/M33 DATA SHEET 1. General Description and Feature Highlights
The DS33M30 family of devices provides interconnection and mapping functionality between Ethernet and
SONET/SDH networking elements. The product family includes three devices with differing features: • DS33M30: One GMII mapped to STS-3c/VC-4 in a compact 10mm package. • DS33M31: One GMII/MII mapped to a protected interface, with higher order EoS and EoPoS. • DS33M33: One GMII/MII mapped to a protected interface, with higher order EoS, EoPoS and DS3/E3
add/drop mux.
All devices in the product family contain an Ethernet MAC port, one or two STS-3/STM-1 SerDes ports with the
LVDS/LVPECL interface, one or three GFP-F/HDLC/cHDLC/X.86 (LAPS) protocol encapsulators, one or three
higher order SONET/SDH mappers, a DDR SDRAM interface, and a local bus port for control/status. Ethernet
traffic is encapsulated with GFP-F, HDLC, cHDLC, or X.86 (LAPS) protocol to be transmitted onto the STS-3/
STM-1 interface. The family receives encapsulated Ethernet frames from the SerDes receiver interface and
transmits the de-encapsulated frames onto the Ethernet port.
With the smallest footprint, the DS33M30 contains the smallest feature set in the product family. It performs EoS
higher order mapping of Ethernet frames into a single STS-3c SPE or VC-4. The DS33M30 has one 1000Mbps
(GbE) port with GMII interface. The DS33M30 supports Ethernet OAM insert/extract capability, QoS Priority
Scheduling, VLAN processing, and committed information rate (CIR)-based policers for the delivery of carrier
Ethernet services.
The DS33M31 and DS33M33 expand on the features of the DS33M30 with additional mapping capabilities. They
support next-generation Ethernet over SONET/SDH in virtually concatenated higher order containers as well as
Ethernet-over-PDH-over-SONET/SDH (EoPoS) at the DS3/E3 level. They have an Ethernet interface that can be
configured as a 10/100Mbps MII/RMII port or a 1000Mbps (GbE) GMII port. They integrate four
mapping/demapping functions: • SONET/SDH mapping: STS-1/VC-3 to STS-3/STM-1; or TU-3 to VC-4 to STM-1 • PDH mapping: DS3/E3 to STS-1/VC-3 (or TUG-3/VC-4); • EoS higher order mapping: Ethernet to STS-1/VC-3 (or TU-3); and • EoPoS mapping: Ethernet to DS3/E3 to STS-1/VC-3 (or TUG-3/VC-4).
At the STS-3/STM-1 side, the DS33M31 and DS33M33 devices interface to an STS-3/STM-1 signal through dual
serial-data buses operating at the rate of 155.52Mbps. This allows the implementation of a protected SONET/SDH
at PHY layer. Each serializer/deserializer (SerDes) is supported with independent STS-3/STM-1 framer.
The DS33M33 supports all the features of the DS33M30 and DS33M31, with additional line interfaces for up to
three add/drop DS3/E3 tributaries.
The SerDes interfaces, with LVDS/LVPECL, can be seamlessly connected to commercially available optical
transceivers.
Microprocessor control can be accomplished through an 8/16-bit local bus or SPI bus. The family contains a
125MHz DDR SDRAM controller and interfaces to a 32-bit-wide 256Mb DDR SDRAM through a 16-bit data bus.
The DDR SDRAM is used to buffer data through the Ethernet and STS-3/STM-1 ports.
The power supplies consist of a 1.8V core supply, a 2.5V DDR SDRAM supply, and 3.3V I/O supply.
DS33M30/M31/M33 DATA SHEET Table 1-1. Product Selection Matrix
PART ETHERNET
PORT
STS-3/
STM-1
PORT
PDH
(DS3/E3)
PORT
ETHERNET
MAPPING
VLAN
FORWARDING
SUPPORT
PRIORITY
FORWARDING
SUPPORT
VCAT
GROUPS
(VCGS) µP
CONTROL PACKAGE
DS33M30 1 GbE 1 0 EoS NA Y 1 SPI 10mm, 144
CSBGA
DS33M31 1 (10/100,
GbE)
2 (1+1
protected) 0 EoS, EoPoS Y Y 3 SPI or
Parallel
17mm, 256
CSBGA
DS33M33 1 (10/100,
GbE)
2 (1+1
protected) 3 EoS, EoPoS Y Y 3 SPI or
Parallel
17mm, 256
CSBGA
Note: The number of members for a VCG in the DS33M31 and DS33M33 can be 1, 2, or 3.
1.1 Device Feature Overview
Note: See the glossary section (in the full data sheet) for the descriptions of terms used in this
documentation, especially for the terms referring to the ports, blocks, and directions.
Table 1-2. Summary of Mapping Functions MAPPING FUNCTIONS “>” DS33M30 DS33M31 DS33M33 NOTES Ethernet > STS-3c > STS-3 x x x — Ethernet > AU-4 > STM-1 x x x — Ethernet > STS-1 > STS-3 — x x — Ethernet > AU-3 > STM-1 — x x — Ethernet > TU-3 > AU-4 > STM-1 — x x — Ethernet > DS3 > STS-1 > STS-3 — x x Without
external DS3
port Ethernet > DS3 > AU-3 > STM-1 — x x Ethernet > DS3 > TU-3 > AU-4 > STM-1 — x x Ethernet > E3 > STS-1 > STS-3 — x x Without
external E3
port
10 Ethernet > E3 > AU-3 > STM-1 — x x
11 Ethernet > E3 > TU-3 > AU-4 > STM-1 — x x
12 DS3 > STS-1 > STS-3 — — x —
13 DS3 > AU-3 > STM-1 — — x —
14 DS3 > TU-3 > AU-4 > STM-1 — — x —
15 E3 > STS-1 > STS-3 — — x —
16 E3 > AU-3 > STM-1 — — x —
17 E3 > TU-3 > AU-4 > STM-1 — — x —
The DS33M30 family of devices offer the following features: • Supports the mapping protocols as listed in Table 1-2. • Supports single 10/100/1000Mbps Ethernet interface • STS-3/STM-1 interface operating at 155.52Mbps • Supports two transmit timing modes for STS-3/STM-1 port(s): • Loop timing (transmit timing reference = receive timing) • Local timing (transmit timing reference = CLAD timing) • Supports three transmit timing modes for Line DS3/E3 ports: (DS33M33) • Loop timed (transmit timing reference = receive timing) • Line timed (or thru timed) (transmit timing reference = Drop DS3/E3 thru timing) • Local timed (transmit timing reference = CLAD timing)
DS33M30/M31/M33 DATA SHEET Manual or automatic one-second update of performance monitoring counters • Single reference clock for all data rates using internal clock rate adapter (CLAD) • Detection of loss of transmit clock and loss of receive clock • Supports two packages: • 10mm, 144-pin CSBGA Package (DS33M30) • 17mm, 256-pin CSBGA Package (DS33M31/DS33M33) • 1.8V, 2.5V, 3.3V supplies • IEEE 1149.1 JTAG boundary scan • Software access to device ID and silicon revision • Development support includes evaluation kit, driver source code, and reference designs 1.2 TDM Feature Overview
Figure 1-1 describes the TDM side feature.
Figure 1-1. TDM Functional Blocks
STS-3
Section/Line
Termination
STS-3
Section/Line
TerminationSTS-3 Path
Termination
(VC-4)
STS-1 Path
Termination
(VC-3)
DS3/E3
MAPPERDS3/E3
Desync
Add/Drop
DS3/E3
FramerLine
DS3/E3
Framer
EoPoS
EoS (VC-3/STS-1)
SERDES
SERDES
EoS (VC-4/STS-3c)
Line DS3/E3 side
B3ZS/
HDB3
line coder
Encapsulated
Ethernet
STS-3/STM-1
Side
Drop Direction
Add Direction • Supports M23 DS3, C-bit DS3, G.751 E3, and G.832 E3 facilities • Mapping/demapping of three DS3/E3 tributaries to/from STS-3/STM-1 through STS-1 or AU-3 or TU-3/AU-4 • Fully integrated and compliant DS3/E3 mapper/demapper and synchronizers/desynchronizers per
Telcordia, ANSI, and ITU standards • High speed DS3/E3/STS-1/STS-3 overhead insertion/extraction with full access to all overhead bytes • Full-featured DS3/E3/STS-1/STS-3 defect and performance monitoring (PM) support Large PM counters
for accumulation intervals up to one second • Loopback capabilities at both STS-3/STM-1 side and line DS3/E3 side • Dual STS-3/STM-1 155.52Mbps serial interfaces with receive clock recovery and transmit clock synthesis • From a single reference clock the CLAD (cLock rate adapter) generates clock references for DS3
(44.736MHz), E3 (34.368MHz), and/or STS-3/STM-1 reference (77.76/19.44MHz)
DS33M30/M31/M33 DATA SHEET 1.3 SONET/SDH
1.3.1 STS-3/STM-1 SerDes • SerDes with clock recovery at 155.52Mbps interface for STS-3/STM-1 data stream • LVDS/LVPECL levels for glueless interconnect to 155.52Mbps optical transceiver device
1.3.2 STS-3/STM-1 Framer and Formatter
1.3.2.1 STS-3/STM-1 Formatter with Transport Overhead Insertion • User-configurable scrambling for transmit STS-3/STM-1 bit stream • User-configurable TOH bytes insertion for framing (A1, A2), Section trace (J0), Section BIP-8 (B1), Section
orderwire (E1), Section user channel (F1), Section Data Communication Channel (DCC) (D1-D3), STS-1
pointers (H1, H2, H3), Line BIP-8 (B2), automatic protection switching (APS) channel (K1, K2), Line DCC
(D4-D12), synchronization status message (S1), line Remote Error Indication (REI) (M1), and line
orderwire (E2). Note: B1 and B2 are configured as error masks • Automatic calculation and insertion of Section BIP-8 (B1) and Line BIP-8 (B2) • User configurable insertion of AIS-P, and AIS-L • Programmable generation of H1, H2, and H3 bytes as an error mask • All TOH bytes can be inserted from the associated transmit STS-3 transport overhead input port or
software accessible internal registers • Automatic or manual generation of line remote error indication (REI-L) and line remote defect indication
(RDI-L) • Programmable insertion of framing errors, B1 errors, B2 errors, and invalid pointer • Insertion of HDLC data stream into section DCC (D1-D3), line DCC (D4-D12), TOH DCC (D1-D12), or
section user channel (F1) • Insertion of trace ID message into section trace (J0)
1.3.2.2 STS-3/STM-1 Framer with Transport Overhead Extraction • Frame synchronization for STS-3 compliant to GR-253 so that SEF defect is not detected more than an
average of once every six minutes in the presence of STS-1 BER of 10-3 • Optional descrambler of incoming STS-1 data stream with polynomial of 1+x6+x7 • Extraction of all TOH bytes (per LTE requirement): Framing (A1, A2), Section trace (J0), Section BIP-8
(B1), Section orderwire (E1), Section user channel (F1), Section Data Communication Channel (DCC) (D1-
D3), STS-1 pointers (H1, H2, H3), Line BIP-8 (B2), automatic protection switching (APS) channel (K1, K2),
Line DCC (D4-D12), synchronization status message (S1), Line Remote Error Indication (REI) (M1), and
Line orderwire (E2) • All TOH bytes are presented on the associated receive STS-3 transport overhead output port and software
accessible internal registers • Detection of STE and LTE defects including LOS, LOF, SEF, COFA, and AIS-L • Fully programmable automatic downstream path AIS (AIS-P) insertion upon detection of LOS, LOF, TIM-S,
and/or AIS-L • Detection of STE and LTE defects including RDI-L, APS unstable, and sync message change (S1) • Detection and accumulation of framing errors (A1/A2), OOF occurrences, section BIP-8 (B1) errors (bit or
block basis), line BIP-8 (B2) errors (bit or block basis), and line remote error indications (REI-L) • Extraction of HDLC data stream from Section DCC (D1-D3), Line DCC (D4-D12), TOH DCC (D1-D12), or
Section user channel (F1) • Extraction of trace ID message from Section trace (J0) • Two line BIP-8 parity (B2) bit error rate (BER) measurement circuits with separate software programmable
detection and clearing settings
DS33M30/M31/M33 DATA SHEET 1.3.3 STS-3c/AU-4 Pointer Processing
1.3.3.1 STS-3c/AU-4 Pointer Generation • AU-4 pointer generation using the associated Add STS-3/STM-1 clock • Pointer generation of outgoing pointer values (H1/H2) per ITU G.707 specifications • Generation of AU-4 pointer bytes (H1, H2, and H3) and insertion of the VC-4 POH • User-configurable automatic or manual generation of AIS-P • Generation of an unequipped indication (“all zero” path (payload data and POH) with valid J1, B3, and G1) • Comprehensive software programmable pointer (H1, H2) diagnostics
1.3.3.2 STS-3c/AU-4 Pointer Interpretation • AU-4 pointer interpretation using the Drop STS-3/STM-1 clock • Pointer interpretation per ITU G.707 specifications • Extraction of AU-4 pointer bytes (H1, H2, and H3) and the VC-4 POH • Detection of alarm defects including LOP and “all ones” pointer (AIS-P) • Detection and accumulation of incoming pointer increments, decrements, changes, and new pointers
1.3.4 STS-3c SPE/VC-4 Path Termination
1.3.4.1 STS-3c SPE/VC-4 Path Overhead Generation • Generation of all POH bytes including Path trace ID (J1), Path BIP-8 (B3), Path signal label (C2), Path
status (G1), Path user byte (F2), Path concatenation indicator (H4), and Path growth (Z3, Z4, and Z5) • All POH bytes can be inserted from either the VC-4 POH input port or software accessible internal registers • User configurable automatic or manual generation of PTE defects including RDI-P and ERDI-P • Programmable error insertion of B3 and REI errors • Insertion of HDLC data stream into path user byte (F2) • Insertion of path trace ID into path trace byte (J1)
1.3.4.2 STS-3c SPE/VC-4 Path Overhead Reception and Monitoring • Monitoring of all POH bytes including Path trace ID (J1), Path BIP-8 (B3), Path signal label (C2), Path
status (G1), Path user byte (F2), Path concatenation indicator (H4), and Path growth (Z3, Z4, and Z5) • All POH bytes are presented to the VC-4 POH output port and software accessible internal registers • PTE defect detection: PLM-P, PLU-P, UNEQ-P, PDI-P, RDI-P, and Enhanced RDI-P (ERDI-P) • Detection and accumulation of Path BIP-8 (B3) errors and Path REI errors (part of G1) on a bit or block
basis • Two POH B3 bit-error rate (BER) measurement circuits with separate software programmable detection
and clearing thresholds • Extraction of HDLC data stream from path user byte (F2) • Extraction of path trace ID from path trace byte (J1)
1.3.4.3 STS-3c SPE/VC-4 Payload Mapper/Demapper • Mapping of Ethernet traffic into/out of VC-4 payload (C-4).
1.3.5 STS-3 Mux/Demux (DS33M31 and DS33M33 Only)
1.3.5.1 STS-3 Mux • Multiplexing of three TU-3 data streams (or ports) into a C-4 per ITU G.707 • Multiplexing of three STS-1/AU-3 data streams (or ports) into an STS-3/STM-1 per ITU G.707 and
Telcordia GR-253
1.3.5.2 STS-3 DeMux • Demultiplexing of three TU-3 data streams (or ports) from a C-4 per ITU G.707 • Demultiplexing of three STS-1/AU-3 data streams (or ports) from an STS-3/STM-1 per ITU G.707 and
Telcordia GR-253
DS33M30/M31/M33 DATA SHEET 1.3.6 STS-1/AU-3/TU-3 Formatter and Framer (DS33M31 and DS33M33 Only)
1.3.6.1 STS-1/AU-3 Formatter with Transport Overhead Insertion • User-configurable scrambling for transmit STS-1 data stream using a polynomial of 1 + x6 + x7 • Generation of all TOH bytes (per LTE requirement) including framing (A1, A2), Section trace (J0), Section
BIP-8 (B1), Section orderwire (E1), Section user channel (F1), Section Data Communication Channel
(DCC) (D1-D3), STS-1 pointers (H1, H2, H3), line BIP-8 parity (B2), automatic protection switching (APS)
channel (K1, K2), Line DCC (D4-D12), synchronization status message (S1), Line Remote Error Indication
(REI) (M1), and line orderwire (E2) Note: B1 and B2 are configured as error masks • Calculation and insertion of Section BIP-8 (B1) and Line BIP-8 (B2) • Programmable insertion of AIS-P, and AIS-L • Programmable generation of H1, H2, and H3 bytes as an error mask • All TOH bytes can be inserted from the associated transmit STS-1 transport overhead input port or
software accessible internal registers • Automatic or manual generation of Line remote error indication (REI-L) and Line remote defect indication
(RDI-L) • Programmable insertion of framing errors, B1 errors, B2 errors, and invalid pointer • Insertion of HDLC data stream into Section DCC (D1-D3), Line DCC (D4-D12), TOH DCC (D1-D12), or
Section user channel (F1) • Insertion of trace ID message into Section trace (J0)
1.3.6.2 STS-1/AU-3 Framer with Transport Overhead Extraction • User-configurable descrambler of incoming STS-1 data stream with polynomial of 1 + x6 + x7 • Extraction of all TOH bytes (per LTE requirement): Framing (A1, A2), Section trace (J0), Section BIP-8
(B1), Section orderwire (E1), Section user channel (F1), Section Data Communication Channel (DCC) (D1-
D3), STS-1 pointers (H1, H2, H3), Line BIP-8 (B2), automatic protection switching (APS) channel (K1, K2),
Line DCC (D4-D12), synchronization status message (S1), Line Remote Error Indication (REI) (M1), and
Line orderwire (E2) • All TOH bytes are presented on the associated receive STS-1 transport overhead output port and software
accessible internal registers • Detection of STE and LTE defects including LOS, LOF, SEF, COFA, and AIS-L • Fully programmable automatic downstream path AIS (AIS-P) insertion upon detection of LOS, LOF, TIM-S,
and/or AIS-L • Detection of STE and LTE defects including RDI-L, APS unstable, and sync message change (S1) • Detection and accumulation of framing errors (A1/A2), OOF occurrences, section BIP-8 (B1) errors (bit or
block basis), line BIP-8 (B2) errors (bit or block basis), and line remote error indications (REI-L) • Extraction of HDLC data stream from Section DCC (D1-D3), Line DCC (D4-D12), TOH DCC (D1-D12), or
Section user channel (F1) • Extraction of trace ID message from Section trace (J0)
1.3.7 STS-1/AU-3/TU-3 Pointer Processing (DS33M31 and DS33M33 only)
1.3.7.1 STS-1/AU-3/TU-3 Pointer Generation • Per STS-1/AU-3/TU-3 tributary pointer generation using the associated inbound Add STS-3/STM-1 clock • Pointer generation per Telcordia GR-253-CORE and ITU G.707 specifications • Generation of STS-1, AU-3, or TU-3 pointer bytes (H1, H2, and H3) and insertion of the STS-1 SPE/VC-3
POH • Detection and accumulation of pointer increments, decrements, and changes • User configurable automatic or manual generation of AIS-P • Generation of an unequipped indication (“all zero” path (payload data and POH) with valid J1, B3, and G1) • Comprehensive software programmable pointer (H1, H2) diagnostics (Performs a pointer increment
justification (PJC+), pointer decrement justification (PJC-), pointer change (PJC) to a programmable fixed
value (without NDF), or new pointer change (NDF) to a programmable fixed value (with NDF) via the
register interface)
DS33M30/M31/M33 DATA SHEET 1.3.7.2 STS-1/AU-3/TU-3 Pointer Interpreter • Per STS-1/AU-3/TU-3 tributary pointer interpretation using the outbound Drop STS-3/STM-1 clock • Pointer interpretation per Telcordia GR-253-CORE and ITU G.707 specifications • Extraction of STS-1, AU-3, or TU-3 pointer bytes (H1, H2, and H3) • Detection of defects including, LOP and “all-ones” pointer (AIS-P) • Detection and accumulation of incoming pointer increments, decrements, changes, and new pointers
1.3.8 STS-1/VC-3 Path Termination (DS33M31 and DS33M33 only)
1.3.8.1 STS-1/VC-3 Path Overhead Generation • Generation of all POH bytes including Path trace ID (J1), Path BIP-8 (B3), Path signal label (C2), Path
status (G1), Path user byte (F2), Path concatenation indicator (H4), and Path growth (Z3, Z4, and Z5) • All POH bytes can be inserted from either the associated inbound Add STS-1/VC-3 POH input port or
software accessible internal registers • Automatic or manual generation of PTE alarm defects including RDI-P and ERDI-P • Programmable error insertion of B3 and REI errors • Insertion of HDLC data stream into path user byte (F2) • Insertion of path trace ID into path trace byte (J1)
1.3.8.2 STS-1/VC-3 Path Overhead Reception and Monitoring • Termination of all POH bytes (per PTE requirement) including Path trace ID (J1), Path BIP-8 (B3), path
signal label (C2), Path status (G1), Path user byte (F2), path concatenation indicator (H4), and Path growth
(Z3, Z4, and Z5) • All POH bytes presented on the associated STS-1 SPE/VC-3 POH output port and software accessible
internal registers • Detection of PTE defects: PLM-P, PLU-P, UNEQ-P, PDI-P, RDI-P, and Enhanced RDI-P (ERDI-P) • Detection and accumulation of path B3 and path REI errors (part of G1) on a bit or block basis • Two POH B3 bit error rate (BER) measurement circuits with separate software programmable detection
and clearing thresholds • Extraction of HDLC data stream from path user byte (F2) • Extraction of path trace ID from path trace byte (J1)
1.3.8.3 STS-1/VC-3 Synchronizer • Synchronization of STS-1 SPE/VC-3 to accommodate asynchronous payload through pointer justifications • Accommodation of frequency offsets up to +100ppm between the SONET/SDH Telecom Bus reference
frequency of 77.76MHz and the line/tributary STS-1 frequency 51.84MHz • Elastic store overflow and underflow conditions • Selectable lock and fast lock modes of operation • Programmable frequency out of range indication (±5, ±10, ±20, or ±40ppm). • SONET mapping jitter conforming to GR-253 and GR-499 and SDH mapping jitter compliant to ITU G.825e
and O.172e
1.3.8.4 STS-1 SPE Payload Mapping • Each STS-1 SPE can be mapped with Asynchronous DS3/E3 or Ethernet traffic. These two mapping
modes are mutually exclusive.
1.3.8.5 STS-1 SPE Ethernet Mapping/Demapping • Mapping of Ethernet packets into STS-1 SPE
1.3.8.6 Async DS3/E3 Demapper/Desynchronizer • Extraction of DS3/E3 data stream from an STS-1 SPE compliant to Telcordia GR-253 or VC-3 compliant to
ITU G.707 • Generation of a nominal rate E3 (34.368MHz) or DS3 (44.736MHz) • Standard SONET STS-1 demapping for a DS3/E3 conforming with Telcordia GR-253 and GR-499 • Standard SDH VC-3 demapping for a DS3/E3 conforming to ITU-T G.707, G.825e, and O.172e
DS33M30/M31/M33 DATA SHEET Synchronization of DS3/E3 serial streams from SONET/SDH STS-1 SPE/VC-3 accommodating asynchronous timing between the DS3/E3 line/tributary and the STS-3/STM-1 references, through
appropriate processing of bit stuffing and pointer justifications • Full integration of the DS3/E3 desynchronization and PLL circuitry necessary to produce smooth DS3/E3
data and clock signals that meet the Telcordia (GR-253-CORE and GR-499-CORE), ANSI (T1-105.03-
1994 and T1-105.03b-1997), and ITU (G.825e and O.172e) jitter and wander requirements. Desynchronize
circuitry includes clock smoother consisting of onboard analog/digital control modulators, analog/digital
filters, and frequency detectors • Absorption of SONET/SDH pointer justifications and DS3/E3 payload bit stuffs in an elastic store, and
controlling outgoing clock phase using the smooth clock generator circuit with selectable lock and fast lock
modes of operation • Tolerating frequency offsets up to ±200ppm between the inbound Add Telecom Bus clock (ACLK) and the
free-running DS3/E3 reference clocks generated by the internal Clock Rate Adapter • Monitoring and detection of the stability of the recovered DS3 clocks with frequency offset indications of ±20, ±100, and ±200ppm and the elastic store FIFO underflow/overflow conditions. The elastic store has
an auto center mechanism that separates the read and write pointers under normal operating conditions
and after underflow/overflow events occur • Programmable frequency out of range indication (±10, ±20, ±40, or ±100ppm) • Selectable lock and fast lock modes of operation • Maximum lock time for the smooth recovered/output DS3/E3 data and clock that is demapped from
SONET/SDH is 1.06ms (10 DS3, 24 G.751 E3, or nine G.832 E3 frames) (switch time to valid DS3 with a
smooth clock) • Controls include enables/disables/settings for serial data type, and demapping mode
1.3.8.7 Async DS3/E3 Mapper/Synchronizer • Synchronization of DS3/E3 serial streams to SONET/SDH STS-1 SPE/VC-3 accommodating
asynchronous timing between the DS3/E3 line/tributary and the STS-3/STM-1 references, through bit
stuffing • Accommodation of frequency offsets up to +200ppm between the 155.52Mbps inbound add STS-3/STM-1
serial data stream and the 44.736/34.368MHz line/tributary DS3/E3 clock (RLCLKn) • Elastic store overflow and underflow conditions • Programmable frequency out of range indication (±10, ±20, ±40, or ±100ppm) • SONET mapping jitter conforming to GR-253 and GR-499 and SDH mapping jitter compliant to ITU G.707,
G.825e and O.172e • Mapping of DS3/E3 serial data stream into an STS-1 SPE compliant to Telcordia GR-253 or VC-3
compliant to ITU G.707 • Standard SONET STS-1 mapping for DS3/E3 conforming to Telcordia GR-253 and GR-499 • Standard SDH VC-3 mapping for DS3/E3 conforming to ITU-T G.707 • All combinations of DS3 or E3 mapping configuration into STS-1, AU-3, or TU-3/AU-4 are possible • Software configuration for SONET/SDH mapping on a per tributary basis • Software configuration for all fixed stuff bits to zeros or ones • Controls include enables/disables/settings for mapping type, alarm insertion, stuff bits, frequency offset
(±100ppm to ±200ppm)
