DS3251 ,Single/Dual/Triple/Quad DS3/E3/STS-1 LIUsPIN DESCRIPTIONS...10 7. REGISTER DESCRIPTIONS ........15 8. RECEIVER 24 8.1 INTERFACING TO THE LIN ..
DS3251+ ,Single/Dual/Triple/Quad DS3/E3/STS-1 LIUsFEATURES The DS3251 (single), DS3252 (dual), DS3253 Pin-Compatible Family of Products (triple), a ..
DS32512+ ,6-/8-/12-Port DS3/E3/STS-1 LIUAPPLICATIONS 12.8MHz, 19.44MHz, 38.88MHz, 77.76MHz) Per-Port Programmable Internal Line Terminatio ..
DS32512+ ,6-/8-/12-Port DS3/E3/STS-1 LIUGENERAL DESCRIPTION Pin-Compatible Family of Products The DS32506 (6 port), DS32508 (8 port), and ..
DS32512+ ,6-/8-/12-Port DS3/E3/STS-1 LIUAPPLICATIONS 12.8MHz, 19.44MHz, 38.88MHz, 77.76MHz) Per-Port Programmable Internal Line Terminatio ..
DS32512N ,6-/8-/12-Port DS3/E3/STS-1 LIUBLOCK DIAGRAM ..7 3. APPLICATION EXAMPLE ........8 4. DETAILED DESCRIPTION........9 5. DETAILED
EB2-12 ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEFEATURESª Compact and lightweight : 7.5 mm · 14.3 mm · 9.3 mm, 1.5 gª 2 form c contact arrangementª ..
EB2-12NU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EB2-12T-L ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
EB2-12TNU ,COMPACT AND LIGHT WEIGHT SURFACE MOUNTING TYPEDATA SHEETMINIATURE SIGNAL RELAYEB2 SERIESCOMPACT AND LIGHT WEIGHTSURFACE MOUNTING TYPEDESCRIPTION ..
DS3251-DS3251+-DS3252-DS3252N-DS3252NA3-DS3253-DS3253+-DS3253N-DS3253N+-DS3253NA3-DS3254-DS3254+
Single/Dual/Triple/Quad DS3/E3/STS-1 LIUs
GENERAL DESCRIPTION The DS3251 (single), DS3252 (dual), DS3253
(triple), and DS3254 (quad) line interface units (LIUs)
perform the functions necessary for interfacing at the
physical layer to DS3, E3, or STS-1 lines. Each LIU
has independent receive and transmit paths and a
built-in jitter attenuator. An on-chip clock adapter
generates all line-rate clocks from a single input
clock. Control interface options include 8-bit parallel,
SPI, and hardware mode.
APPLICATIONS SONET/SDH and PDH Multiplexers
Digital Cross-Connects
Access Concentrators
ATM and Frame Relay Equipment
Routers
PBXs
DSLAMs
CSU/DSUs
FUNCTIONAL DIAGRAM
FEATURES � Pin-Compatible Family of Products � Each Port Independently Configurable � Receive Clock and Data Recovery for Up to 380
meters (DS3), 440 meters (E3), or 360 meters
(STS-1) of 75Ω Coaxial Cable � Standards-Compliant Transmit Waveshaping � Three Control Interface Options: 8-Bit Parallel,
SPI, and Hardware Mode � Built-In Jitter Attenuators can be Placed in Either
the Receive or Transmit Paths � Jitter Attenuators Have Provisionable Buffer
Depth: 16, 32, 64, or 128 Bits � Built-In Clock Adapter Generates All Line-Rate
Clocks from a Single Input Clock (DS3, E3,
STS-1, OC-3, 19.44MHz, 38.88MHz,
77.76MHz) � B3ZS/HDB3 Encoding and Decoding � Minimal External Components Required � Local and Remote Loopbacks � Low-Power 3.3V Operation (5V Tolerant I/O) � Industrial Temperature Range: -40°C to +85°C � Small Package: 144-Pin, 13mm x 13mm
Thermally Enhanced CSBGA � Drop-In Replacement for DS3151/52/53/54 LIUs � IEEE 1149.1 JTAG Support
Features continued on page 5.
ORDERING INFORMATION
PART LIU TEMP RANGE PIN-PACKAGE
DS3251 1 0°C to +70°C 144 TE-CSBGA
DS3251N 1 -40°C to +85°C 144 TE-CSBGA
DS3252 2 0°C to +70°C 144 TE-CSBGA
DS3252N 2 -40°C to +85°C 144 TE-CSBGA
DS3253 3 0°C to +70°C 144 TE-CSBGA
DS3253N 3 -40°C to +85°C 144 TE-CSBGA
DS3254 4 0°C to +70°C 144 TE-CSBGA
DS3254N 4 -40°C to +85°C 144 TE-CSBGA
RXP
RXN
TXP
TXN
CLK
DATA
CLK
DATA
LINE IN
DS3, E3,
OR STS-1
LINE OUT
DS3, E3,
OR STS-1
RECEIVE
CLOCK
AND DATA
TRANSMIT
CLOCK
AND DATA
EACH LIU
STATUS
CONTROL
Dallas
Semiconductor DS325x
DS3251/DS3252/DS3253/DS3254
Single/Dual/Triple/Quad
DS3/E3/STS-1 LIUs
DS3251/DS3252/DS3253/DS3254
TABLE OF CONTENTS
1. STANDARDS COMPLIANCE............................................................................................................6
2. DETAILED DESCRIPTION................................................................................................................7
3. APPLICATION EXAMPLE.................................................................................................................7
4. BLOCK DIAGRAMS..........................................................................................................................8
5. CONTROL INTERFACE MODES......................................................................................................9
6. PIN DESCRIPTIONS........................................................................................................................10
7. REGISTER DESCRIPTIONS...........................................................................................................15
8. RECEIVER.......................................................................................................................................24 8.1 INTERFACING TO THE LINE...........................................................................................................................24
8.2 OPTIONAL PREAMP.....................................................................................................................................24
8.3 AUTOMATIC GAIN CONTROL (AGC) AND ADAPTIVE EQUALIZER.....................................................................24
8.4 CLOCK AND DATA RECOVERY (CDR)...........................................................................................................24
8.5 LOSS-OF-SIGNAL (LOS) DETECTOR............................................................................................................24
8.6 FRAMER INTERFACE FORMAT AND THE B3ZS/HDB3 DECODER....................................................................25
8.7 RECEIVE LINE-CODE VIOLATION COUNTER..................................................................................................26
8.8 RECEIVER POWER-DOWN...........................................................................................................................26
8.9 RECEIVER JITTER TOLERANCE....................................................................................................................26
9. TRANSMITTER................................................................................................................................27 9.1 TRANSMIT CLOCK.......................................................................................................................................27
9.2 FRAMER INTERFACE FORMAT AND THE B3ZS/HDB3 ENCODER....................................................................27
9.3 PATTERN GENERATION...............................................................................................................................27
9.4 WAVESHAPING, LINE BUILD-OUT, LINE DRIVER............................................................................................28
9.5 INTERFACING TO THE LINE...........................................................................................................................28
9.6 TRANSMIT DRIVER MONITOR.......................................................................................................................28
9.7 TRANSMITTER POWER-DOWN......................................................................................................................28
9.8 TRANSMITTER JITTER GENERATION (INTRINSIC)...........................................................................................28
9.9 TRANSMITTER JITTER TRANSFER.................................................................................................................28
10. JITTER ATTENUATOR................................................................................................................32
11. DIAGNOSTICS.............................................................................................................................34 11.1 PRBS GENERATOR AND DETECTOR............................................................................................................34
11.2 LOOPBACKS...............................................................................................................................................34
12. CLOCK ADAPTER.......................................................................................................................35
13. RESET LOGIC.............................................................................................................................35
14. TRANSFORMERS........................................................................................................................36
15. CPU INTERFACES......................................................................................................................37 15.1 PARALLEL INTERFACE.................................................................................................................................37
15.2 SPI INTERFACE..........................................................................................................................................37
16. JTAG TEST ACCESS PORT AND BOUNDARY SCAN.............................................................40 16.1 JTAG DESCRIPTION...................................................................................................................................40
16.2 JTAG TAP CONTROLLER STATE MACHINE DESCRIPTION.............................................................................40
16.3 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS......................................................................................42
16.4 JTAG TEST REGISTERS..............................................................................................................................43
17. ELECTRICAL CHARACTERISTICS............................................................................................44
18. PIN ASSIGNMENTS.....................................................................................................................56
19. PACKAGE INFORMATION..........................................................................................................70 19.1 144-PIN TE-CSBGA (56-G6016-001).......................................................................................................70
20. THERMAL INFORMATION..........................................................................................................71
21. REVISION HISTORY....................................................................................................................71
DS3251/DS3252/DS3253/DS3254
LIST OF FIGURES Figure 2-1. External Connections................................................................................................................................7
Figure 3-1. 4-Port Unchannelized DS3/E3 Card.........................................................................................................7
Figure 4-1. CPU Bus Mode Block Diagram.................................................................................................................8
Figure 4-2. Hardware Mode Block Diagram................................................................................................................9
Figure 7-1. Status Register Logic..............................................................................................................................16
Figure 8-1. Receiver Jitter Tolerance........................................................................................................................27
Figure 9-1. E3 Waveform Template...........................................................................................................................30
Figure 9-2. DS3 AIS Structure...................................................................................................................................31
Figure 10-1. Jitter Attenuation/Jitter Transfer............................................................................................................33
Figure 11-1. PRBS Output with Normal RCLK Operation.........................................................................................34
Figure 11-2. PRBS Output with Inverted RCLK Operation........................................................................................34
Figure 15-1. SPI Clock Polarity and Phase Options..................................................................................................38
Figure 15-2. SPI Bus Transactions............................................................................................................................39
Figure 16-1. JTAG Block Diagram.............................................................................................................................41
Figure 16-2. JTAG TAP Controller State Machine....................................................................................................42
Figure 17-1. Transmitter Framer Interface Timing Diagram......................................................................................46
Figure 17-2. Receiver Framer Interface Timing Diagram..........................................................................................46
Figure 17-3. Parallel CPU Interface Timing Diagram (Nonmultiplexed)....................................................................50
Figure 17-4. Parallel CPU Interface Timing Diagram (Multiplexed)..........................................................................52
Figure 17-5. SPI Interface Timing Diagram...............................................................................................................54
Figure 17-6. JTAG Timing Diagram...........................................................................................................................55
Figure 18-1. DS3251 Hardware Mode Pin Assignment.............................................................................................58
Figure 18-2. DS3251 Parallel Bus Mode Pin Assignment.........................................................................................59
Figure 18-3. DS3251 SPI Bus Mode Pin Assignment...............................................................................................60
Figure 18-4. DS3252 Hardware Mode Pin Assignment.............................................................................................61
Figure 18-5. DS3252 Parallel Bus Mode Pin Assignment.........................................................................................62
Figure 18-6. DS3252 SPI Bus Mode Pin Assignment...............................................................................................63
Figure 18-7. DS3253 Hardware Mode Pin Assignment.............................................................................................64
Figure 18-8. DS3253 Parallel Bus Mode Pin Assignment.........................................................................................65
Figure 18-9. DS3253 SPI Bus Mode Pin Assignment...............................................................................................66
Figure 18-10. DS3254 Hardware Mode Pin Assignment...........................................................................................67
Figure 18-11. DS3254 Parallel Bus Mode Pin Assignment.......................................................................................68
Figure 18-12. DS3254 SPI Bus Mode Pin Assignment.............................................................................................69
DS3251/DS3252/DS3253/DS3254
LIST OF TABLES Table 1-A. Applicable Telecommunications Standards...............................................................................................6
Table 6-A. Global Pin Descriptions............................................................................................................................10
Table 6-B. Receiver Pin Descriptions........................................................................................................................11
Table 6-C. Transmitter Pin Descriptions....................................................................................................................11
Table 6-D. Hardware Mode Pin Descriptions............................................................................................................12
Table 6-E. Parallel Bus Mode Pin Descriptions.........................................................................................................13
Table 6-F. SPI Bus Mode Pin Descriptions...............................................................................................................13
Table 6-G. Transmitter Data Select Options.............................................................................................................14
Table 6-H. Receiver PRBS Pattern Select Options...................................................................................................14
Table 6-I. Hardware Mode Jitter Attenuator Configuration........................................................................................14
Table 7-A. Register Map............................................................................................................................................15
Table 9-A. DS3 Waveform Template.........................................................................................................................29
Table 9-B. DS3 Waveform Test Parameters and Limits............................................................................................29
Table 9-C. STS-1 Waveform Template.....................................................................................................................29
Table 9-D. STS-1 Waveform Test Parameters and Limits........................................................................................29
Table 9-E. E3 Waveform Test Parameters and Limits..............................................................................................30
Table 14-A. Transformer Characteristics...................................................................................................................36
Table 14-B. Recommended Transformers................................................................................................................36
Table 16-A. JTAG Instruction Codes.........................................................................................................................42
Table 16-B. JTAG ID Code........................................................................................................................................43
Table 17-A. Recommended DC Operating Conditions..............................................................................................44
Table 17-B. DC Characteristics.................................................................................................................................44
Table 17-C. Framer Interface Timing.........................................................................................................................45
Table 17-D. Receiver Input Characteristics—DS3 and STS-1 Modes......................................................................47
Table 17-E. Receiver Input Characteristics—E3 Mode.............................................................................................47
Table 17-F. Transmitter Output Characteristics—DS3 and STS-1 Modes................................................................48
Table 17-G. Transmitter Output Characteristics—E3 Mode......................................................................................48
Table 17-H. Parallel CPU Interface Timing...............................................................................................................49
Table 17-I. SPI Interface Timing................................................................................................................................54
Table 17-J. JTAG Interface Timing............................................................................................................................55
Table 18-A. Pin Assignments Sorted by Signal Name..............................................................................................56
Table 20-A. Thermal Properties, Natural Convection................................................................................................71
Table 20-B. Theta-JA (θJA) vs. Airflow.......................................................................................................................71
DS3251/DS3252/DS3253/DS3254
FEATURES (CONTINUED)
Receiver � AGC/equalizer block handles from 0 to 15dB of cable loss � Loss-of-lock (LOL) PLL status indication � Interfaces directly to a DSX monitor signal (~20dB flat loss) using built-in preamp � Digital and analog loss-of-signal (LOS) detectors (ANSI T1.231 and ITU G.775) � Optional B3ZS/HDB3 decoder � Line-code violation output pin and counter � Binary or bipolar framer interface � On-board 215 - 1 and 223 - 1 PRBS detector � Clock inversion for glueless interfacing � Tri-state clock and data outputs support protection switching applications � Per-channel power-down control
Transmitter � Binary or bipolar framer interface � Gapped clock capable up to 51.84MHz � Wide 50 ± 20% transmit clock duty cycle � Clock inversion for glueless interfacing � Optional B3ZS/HDB3 encoder � On-board 215 - 1 and 223 - 1 PRBS generator � Complete DS3 AIS generator (ANSI T1.107) � Unframed all-ones generator (E3 AIS) � Line build-out (LBO) control � Tri-state line driver outputs support protection switching applications � Per-channel power-down control � Output driver monitor
Jitter Attenuator � On-chip crystal-less jitter attenuator � Meets all applicable ANSI, ITU, ETSI and Telcordia jitter transfer and output jitter requirements � Can be placed in the transmit path, receive path or disabled � Selectable FIFO depth: 16, 32, 64 or 128 bits � Overflow and underflow status indications
Clock Adapter � Operates from a single DS3, E3, STS-1, 19.44 MHz, 38.88 MHz, or 77.76 MHz master clock � Synthesizes clock rates that are not provided externally � Use of common system timing frequencies such as 19.44 MHz eliminates the need for any local oscillators,
reduces cost and board space � Very small jitter gain and intrinsic jitter generation � Optionally provides synthesized clocks on output pins for use by neighboring components, such as framers or
mappers
Parallel CPU Interface � Multiplexed or nonmultiplexed 8-bit interface � Configurable for Intel mode (CS, WR, RD) or Motorola mode (CS, DS, R/W)
SPI CPU Interface � Operation up to 10 Mbit/s � Burst mode for multi-byte read and write accesses � Programmable clock polarity and phase � Half-duplex operation gives option to tie SDI and SDO together externally to reduce wire count
