DS3182 ,Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIUFEATURES Test Equipment Single (DS3181), Dual (DS3182), Triple Routers and Switches PDH Multiple ..
DS3182N ,3.3 V, Single/dual/triple/quad ATM/packet PHY with Built-in LIUFEATURES Test Equipment Single (DS3181), Dual (DS3182), Triple Routers and Switches PDH Multiple ..
DS3183 ,Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIUFEATURES (continued) Direct and Clear-Channel Packet Mapping Loopbacks Include Line, Diagnosti ..
DS3183N ,3.3 V, Single/dual/triple/quad ATM/packet PHY with Built-in LIUGENERAL DESCRIPTION FUNCTIONAL DIAGRAM The DS3181, DS3182, DS3183, and DS3184 (DS318x) integrate AT ..
DS3184 ,Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIUFEATURES..... 22 4 STANDARDS COMPLIANCE 23 5 ACRONYMS AND GLOSSARY 25 6 MAJOR OPERATIONAL MODES 26 ..
DS3184DK ,Quad ATM/Packet PHYs for DS3/E3/STS-1 with Built-In LIU Demo Kit DS3184DK Quad ATM/Packet PHYs for DS3/E3/STS-1 with Built-In LIU Demo Kit
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS3182-DS3183-DS3184
Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIU
GENERAL DESCRIPTION The DS3181, DS3182, DS3183, and DS3184
(DS318x) integrate ATM cell/HDLC packet processor(s) with a DS3/E3 framer(s) and LIU(s) to
map/demap ATM cells or packets into as many as four DS3/E3 physical copper lines with DS3-framed,
E3-framed, or clear-channel data streams on per-port basis.
APPLICATIONS Access Concentrators
SONET/SDH ADM
Multiservice Access Platform (MSAP)
SONET/SDH Muxes
PBXs
Multiservice Protocol Platform (MSPP)
Digital Cross Connect
Test Equipment
ATM and Frame Relay Equipment
Routers and Switches
Integrated Access
Device (IAD)
PDH Multiplexer/ Demultiplexer
ORDERING INFORMATION
FUNCTIONAL DIAGRAM
FEATURES Single (DS3181), Dual (DS3182), Triple (DS3183), or Quad (DS3184) with Integrated LIU
ATM/Packet PHYs for DS3, E3, and Clear-Channel 52Mbps (CC52) Pin Compatible for Ease of Port Density
Migration in the Same PC Board Platform Each Port Independently Configurable Perform Receive Clock/Data Recovery and Transmit Waveshaping Jitter Attenuator can be Placed Either in the
Receive or Transmit Paths Interfaces to 75� Coaxial Cable at Lengths Up to 380 Meters or 1246 Feet (DS3) or 440 Meters or
1443 Feet (E3) Uses 1:2 Transformers on Both Tx and Rx Universal PHYs Map ATM Cells and/or HDLC
Packets into DS3 or E3 Data Streams UTOPIA L2/L3 or POS-PHY L2/L3 or SPI-3 Interface with 8-, 16-, or 32-Bit Bus Width 66MHz UTOPIA L3 and POS-PHY L3 Clock 52MHz UTOPIA L2 and POS-PHY L2 Clock Ports Independently Configurable for Cell or
Packet Traffic in POS-PHY Bus Modes Direct, PLCP, DSS, and Clear-Channel Cell Mapping
DS3181/DS3182/DS3183/DS3184
Single/Dual/Triple/Quad
ATM/Packet PHYs with Built-In LIUPOS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
DS3181/DS3182/DS3183/DS3184
FEATURES (continued)Direct and Clear-Channel Packet Mapping On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or G.832) Framer(s) Ports Independently Configurable for DS3, E3
(Full or Subrate) or Arbitrary Framing Protocols Up to 52Mbps Programmable (Externally Controlled or
Internally Finite State Machine Controlled) Subrate DS3/E3 Full-Featured DS3/E3/PLCP Alarm Generation
and Detection Built-In HDLC Controllers with 256-Byte FIFOs for Insertion/Extraction of DS3 PMDL, G.751 Sn
Bit, and G.832 NR/GC Bytes and PLCP NR/GC Bytes On-Chip BERTs for PRBS and Repetitive Pattern
Generation, Detection, and Analysis Large Performance-Monitoring Counters for Accumulation Intervals of at Least 1 Second Flexible Overhead Insertion/Extraction Ports for
DS3, E3, and PLCP Framers Loopbacks Include Line, Diagnostic, Framer, Payload, Analog, and System Interface with
Capabilities to Insert AIS in the Directions Away from Loopback Directions Ports can be Disabled to Reduce Power Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz (DS3), 34.368MHz (E3), and 52MHz (Arbitrary
Framing at Up to 52Mbps) from a Single Clock Reference Source at One of Those Three
Frequencies Pin Compatible with the DS3171/2/3/4 Family and the DS3161/2/3/4 Family 8/16-Bit Generic Microprocessor Interface Low-Power (2.7W typ) 3.3V Operation (5V-
Tolerant I/O) Small, High-Density, Thermally Enhanced, Chip-Scale BGA Packaging (TE-CSBGA) with 1.27mm
Pin Pitch Industrial Temperature Operation: -40°C to +85°C IEEE1149.1 JTAG Test Port
DETAILED DESCRIPTION The DS3181 (single), DS3182 (dual), DS3183 (triple), and DS3184 (quad) PHYs perform all the functions necessary for mapping/demapping ATM cells and/or packets into as many as four DS3 (44.736Mbps) framed, E3
(34.368Mbps) framed, or 52Mbps clear-channel data streams on DS3, E3, or STS-1 physical copper lines. Each line interface unit (LIU) has independent receive and transmit paths. The receiver LIU block performs clock and
data recovery from a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal or can be bypassed for direct clock and data inputs. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The
transmitter LIU drives standard pulse-shape waveforms onto 75� coaxial cable or can be bypassed for direct clock and data outputs. The jitter attenuator can be placed in either transmit or receive data path when the LIU is enabled. Dedicated cell processor and packet processor blocks prepare outgoing cells or packets for transmission
and check incoming cells or packets upon arrival. Built-in DS3/E3 framers transmit and receive cell/packet data in properly formatted M23 DS3, C-bit DS3, G.751 E3, or G.832 E3 data streams. PLCP framers provide legacy ATM
transmission-convergence support. DSS scrambling is performed for clear-channel ATM cell support. With integrated hardware support for both cells and packets, the DS318x DS3/E3 ATM/Packet PHYs provide system on-
chip solutions (from DS3/E3/STS-1 physical copper lines to ATM/Packet UTOPIA/POS-PHY Level 2/3 system switch) for universal high-density line cards in the unchannelized DS3/E3/clear-channel DS3 ATM/Packet
applications. Unused functions can be powered down to reduce device power. The DS318x ATM/Packet PHYs with embedded LIU conform to the telecommunications standards listed in Section 4.
DS3181/DS3182/DS3183/DS3184
TABLE OF CONTENTS BLOCK DIAGRAMS 14 APPLICATIONS 15 FEATURE DETAILS 17 3.1 GLOBAL FEATURES........................................................................................................................................17
3.2 RECEIVE DS3/E3/STS-1 LIU FEATURES.......................................................................................................17 3.3 RECEIVE DS3/E3 FRAMER FEATURES...........................................................................................................17
3.4 RECEIVE PLCP FRAMER FEATURES...............................................................................................................18 3.5 RECEIVE CELL PROCESSOR FEATURES..........................................................................................................18
3.6 RECEIVE PACKET PROCESSOR FEATURES......................................................................................................18 3.7 RECEIVE FIFO FEATURES.............................................................................................................................19
3.8 RECEIVE SYSTEM INTERFACE FEATURES........................................................................................................19 3.9 TRANSMIT SYSTEM INTERFACE FEATURES......................................................................................................19
3.10 TRANSMIT FIFO FEATURES...........................................................................................................................19 3.11 TRANSMIT CELL PROCESSOR FEATURES........................................................................................................19
3.12 TRANSMIT PACKET PROCESSOR FEATURES....................................................................................................19 3.13 TRANSMIT PLCP FORMATTER FEATURES.......................................................................................................20
3.14 TRANSMIT DS3/E3 FORMATTER FEATURES....................................................................................................20 3.15 TRANSMIT DS3/E3/STS-1 LIU FEATURES.....................................................................................................20
3.16 JITTER ATTENUATOR FEATURES.....................................................................................................................20 3.17 CLOCK RATE ADAPTER FEATURES.................................................................................................................20
3.18 HDLC OVERHEAD CONTROLLER FEATURES...................................................................................................20 3.19 FEAC CONTROLLER FEATURES.....................................................................................................................21
3.20 TRAIL TRACE BUFFER FEATURES...................................................................................................................21 3.21 BIT ERROR RATE TESTER (BERT) FEATURES................................................................................................21
3.22 LOOPBACK FEATURES...................................................................................................................................21 3.23 MICROPROCESSOR INTERFACE FEATURES.....................................................................................................21
3.24 SUBRATE FEATURES (FRACTIONAL DS3/E3)..................................................................................................21 3.25 TEST FEATURES............................................................................................................................................22
STANDARDS COMPLIANCE 23 ACRONYMS AND GLOSSARY 25 MAJOR OPERATIONAL MODES 26 6.1 DS3/E3 ATM/PACKET MODE........................................................................................................................26 6.2 DS3/E3 ATM/PACKETOHM MODE............................................................................................................27 6.3 DS3/E3 INTERNAL FRACTIONAL (SUBRATE) ATM/PACKET MODE....................................................................28
6.4 DS3/E3 EXTERNAL FRACTIONAL (SUBRATE) ATM/PACKET MODE..................................................................29
6.5 DS3/E3 FLEXIBLE EXTERNAL FRACTIONAL (SUBRATE) MODE CONFIGURATION MODE.....................................30 6.6 DS3/E3 G.751 PLCP ATM MODE................................................................................................................31
6.7 DS3/E3 G.751 PLCP ATMOHM MODE....................................................................................................32 6.8 CLEAR-CHANNEL ATM/PACKET MODE...........................................................................................................34 6.9 CLEAR-CHANNEL ATM/PACKETOHM MODE...............................................................................................35
6.10 CLEAR-CHANNEL OCTET ALIGNED ATM/PACKETOHM MODE......................................................................36
MAJOR LINE INTERFACE OPERATING MODES 37 7.1 DS3HDB3/B3ZS/AMI LIU MODE.................................................................................................................37
7.2 HDB3/B3ZS/AMI NON-LIU LINE INTERFACE MODE.......................................................................................39 7.3 UNI LINE INTERFACE MODE...........................................................................................................................40
7.4 UNI LINE INTERFACEOHM MODE...............................................................................................................41
PIN DESCRIPTIONS 42 8.1 SHORT PIN DESCRIPTIONS.............................................................................................................................42 8.2 DETAILED PIN DESCRIPTIONS.........................................................................................................................47
8.3 PIN FUNCTIONAL TIMING................................................................................................................................65 8.3.1 Line IO..................................................................................................................................................65
DS3181/DS3182/DS3183/DS3184
8.3.4 Flexible Fractional (FFRAC) DS3/E3 Overhead Interface Functinal Timing.......................................72
8.3.5 UTOPIA/POS-PHY/SPI-3 System Interface Functional Timing...........................................................74 8.3.6 Microprocessor Interface Functional Timing........................................................................................87
8.3.7 JTAG Functional Timing.......................................................................................................................91
INITIALIZATION AND CONFIGURATION 92 9.1 MONITORING AND DEBUGGING.......................................................................................................................94 9.1.1 Cell/Packet FIFO..................................................................................................................................94
9.1.2 Cell Processor......................................................................................................................................94 9.1.3 Packet Processor.................................................................................................................................95
10 FUNCTIONAL DESCRIPTION 96 10.1 PROCESSOR BUS INTERFACE.........................................................................................................................96
10.1.1 8/16-Bit Bus Widths..............................................................................................................................96
10.1.2 Ready Signal (RDY).............................................................................................................................96 10.1.3 Byte Swap Modes................................................................................................................................96
10.1.4 Read-Write / Data Strobe Modes.........................................................................................................96 10.1.5 Clear on Read / Clear on Write Modes................................................................................................96
10.1.6 Global Write Method............................................................................................................................97 10.1.7 Interrupt and Pin Modes.......................................................................................................................97
10.1.8 Interrupt Structure................................................................................................................................97 10.2 CLOCKS........................................................................................................................................................98
10.2.1 Line Clock Modes.................................................................................................................................98 10.2.2 Sources of Clock Output Pin Signals.................................................................................................100
10.2.3 Line IO Pin Timing Source Selection.................................................................................................102 10.2.4 Clock Structures On Signal IO Pins...................................................................................................105
10.2.5 Gapped Clocks...................................................................................................................................106 10.3 RESET AND POWER-DOWN..........................................................................................................................107
10.4 GLOBAL RESOURCES...................................................................................................................................109 10.4.1 Clock Rate Adapter (CLAD)...............................................................................................................109
10.4.2 8 kHz Reference Generation.............................................................................................................111 10.4.3 One Second Reference Generation...................................................................................................113
10.4.4 General-Purpose IO Pins...................................................................................................................113 10.4.5 Performance Monitor Counter Update Details...................................................................................114
10.4.6 Transmit Manual Error Insertion........................................................................................................115 10.5 PER-PORT RESOURCES...............................................................................................................................116
10.5.1 Loopbacks..........................................................................................................................................116 10.5.2 Loss Of Signal Propagation...............................................................................................................118
10.5.3 AIS Logic............................................................................................................................................118 10.5.4 Loop Timing Mode.............................................................................................................................121
10.5.5 HDLC Overhead Controller................................................................................................................121 10.5.6 Trail Trace..........................................................................................................................................121
10.5.7 BERT..................................................................................................................................................121 10.5.8 Fractional Payload Controller.............................................................................................................122
10.5.9 PLCP/Fractional port pins..................................................................................................................122 10.5.10 Framing Modes..................................................................................................................................126
10.5.11 Mapping Modes..................................................................................................................................128 10.5.12 Line Interface Modes..........................................................................................................................132
10.6 UTOPIA/POS-PHY/SPI-3 SYSTEM INTERFACE...........................................................................................134 10.6.1 General Description...........................................................................................................................134
10.6.2 Features.............................................................................................................................................134 10.6.6 System Interface Bus Controller........................................................................................................135
10.7 ATM CELL / HDLC PACKET PROCESSING....................................................................................................140 10.7.1 General Description...........................................................................................................................140
10.7.2 Features.............................................................................................................................................140 10.7.3 Transmit Cell/Packet Processor.........................................................................................................141
10.7.4 Receive Cell/Packet Processor..........................................................................................................141
DS3181/DS3182/DS3183/DS3184
10.7.8 System Loopback...............................................................................................................................150
10.8 DS3/E3 PLCP FRAMER..............................................................................................................................152 10.8.1 General Description...........................................................................................................................152
10.8.2 Features.............................................................................................................................................152 10.8.3 Transmit PLCP Frame Processor......................................................................................................153
10.8.4 Receive PLCP Frame Processor.......................................................................................................153 10.8.5 Transmit DS3 PLCP Frame Processor..............................................................................................153
10.8.6 Receive DS3 PLCP Frame Processor...............................................................................................156 10.8.7 Transmit E3 PLCP Frame Processor.................................................................................................157
10.8.8 Receive E3 PLCP Frame Processor..................................................................................................160 10.9 FRACTIONAL PAYLOAD CONTROLLER...........................................................................................................162
10.9.1 General Description...........................................................................................................................162 10.9.2 Features.............................................................................................................................................162
10.9.3 Transmit Fractional Interface.............................................................................................................163 10.9.4 Transmit Fractional Controller............................................................................................................163
10.9.5 Receive Fractional Interface..............................................................................................................163 10.9.6 Receive Fractional Controller.............................................................................................................163
10.10 DS3/E3 FRAMER / FORMATTER...................................................................................................................165 10.10.1 General Description...........................................................................................................................165
10.10.2 Features.............................................................................................................................................165 10.10.3 Transmit Formatter.............................................................................................................................166
10.10.4 Receive Framer..................................................................................................................................166 10.10.5 C-bit DS3 Framer/Formatter..............................................................................................................170
10.10.6 M23 DS3 Framer/Formatter...............................................................................................................173 10.10.7 G.751 E3 Framer/Formatter...............................................................................................................176
10.10.8 G.832 E3 Framer/Formatter...............................................................................................................178 10.10.9 Clear-Channel Frame Processor.......................................................................................................183
10.11 HDLC OVERHEAD CONTROLLER..................................................................................................................183 10.11.1 General Description...........................................................................................................................183
10.11.2 Features.............................................................................................................................................184 10.11.3 Transmit FIFO....................................................................................................................................184
10.11.4 Transmit HDLC Overhead Processor................................................................................................184 10.11.5 Receive HDLC Overhead Processor.................................................................................................185
10.11.6 Receive FIFO.....................................................................................................................................186 10.12 TRAIL TRACE CONTROLLER..........................................................................................................................186
10.12.1 General Description...........................................................................................................................186 10.12.2 Features.............................................................................................................................................187
10.12.3 Functional Description........................................................................................................................187 10.12.4 Transmit Data Storage.......................................................................................................................187
10.12.5 Transmit Trace ID Processor.............................................................................................................188 10.12.6 Transmit Trail Trace Processing........................................................................................................188
10.12.7 Receive Trace ID Processor..............................................................................................................188 10.12.8 Receive Trail Trace Processing.........................................................................................................188
10.12.9 Receive Data Storage........................................................................................................................189 10.13 FEAC CONTROLLER...................................................................................................................................189
10.13.1 General Description...........................................................................................................................189 10.13.2 Features.............................................................................................................................................190
10.13.3 Functional Description........................................................................................................................190 10.14 LINE ENCODER/DECODER............................................................................................................................191
10.14.1 General Description...........................................................................................................................191 10.14.2 Features.............................................................................................................................................192
10.14.3 B3ZS/HDB3 Encoder.........................................................................................................................192 10.14.4 Transmit Line Interface......................................................................................................................192
10.14.5 Receive Line Interface.......................................................................................................................193 10.14.6 B3ZS/HDB3 Decoder.........................................................................................................................193
10.15 BERT.........................................................................................................................................................195
