DS3174N+ ,Single/Dual/Triple/Quad DS3/E3 Single-Chip TransceiversFEATURES ORDERING INFORMATION Single (DS3171), Dual (DS3172), Triple PART TEMP RANGE PIN-PACKAGE ..
DS3174N+ ,Single/Dual/Triple/Quad DS3/E3 Single-Chip TransceiversGENERAL DESCRIPTION FUNCTIONAL DIAGRAM The DS3171, DS3172, DS3173, and DS3174 (DS317x) combine a D ..
DS3174N+ ,Single/Dual/Triple/Quad DS3/E3 Single-Chip TransceiversBLOCK DIAGRAMS Figure 1-1 shows the external components required at each LIU interface for proper o ..
DS3181N ,3.3 V, Single/dual/triple/quad ATM/packet PHY with Built-in LIUFEATURES (continued) Direct and Clear-Channel Packet Mapping Loopbacks Include Line, Diagnosti ..
DS3182 ,Single/Dual/Triple/Quad ATM/Packet PHYs with Built-In LIUFEATURES Test Equipment Single (DS3181), Dual (DS3182), Triple Routers and Switches PDH Multiple ..
DS3182N ,3.3 V, Single/dual/triple/quad ATM/packet PHY with Built-in LIUFEATURES Test Equipment Single (DS3181), Dual (DS3182), Triple Routers and Switches PDH Multiple ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS3171N+-DS3172N+-DS3174N+
Single/Dual/Triple/Quad DS3/E3 Single-Chip Transceivers
GENERAL DESCRIPTION The DS3171, DS3172, DS3173, and DS3174
(DS317x) combine a DS3/E3 framer(s) and LIU(s) to
interface to as many as four DS3/E3 physical copper
lines.
APPLICATIONS Access Concentrators Multiservice Access
Platform (MSAP) SONET/SDH ADM
and Muxes
PBXs
Multiservice Protocol
Platform (MSPP)
Digital Cross Connect
Test Equipment
PDH Multiplexer/
Demultiplexer
Routers and Switches Integrated Access Device
(IAD)
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE
DS3171 0°C to +70°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3171N -40°C to +85°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3172 0°C to +70°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3172N -40°C to +85°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3173 0°C to +70°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3173N -40°C to +85°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3174 0°C to +70°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
DS3174N -40°C to +85°C 400 TE-PBGA (27mm x
27mm, 1.27mm pitch)
Note: Add the “+” suffix for the lead-free package option.
FUNCTIONAL DIAGRAM
DS317x DS3/E3
PORTS
DS3/
LIU
DS3/E3
FRAMER/
FORMATTER
SYSTEM
BACKPLANE
FEATURES � Single (DS3171), Dual (DS3172), Triple
(DS3173), or Quad (DS3174) Single-Chip
Transceiver for DS3 and E3 � All Four Devices are Pin Compatible for Ease of
Port Density Migration in the Same Printed
Circuit Board Platform � Each Port Independently Configurable � Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3 � Jitter Attenuator can be Placed Either in the
Receive or Transmit Paths � Interfaces to 75Ω Coaxial Cable at Lengths Up to
380 meters, or 1246 feet (DS3) or 440 meters, or
1443 feet (E3) � Uses 1:2 Transformers on Both Tx and Rx � On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer(s) � Ports Independently Configurable for DS3, E3 � Built-In HDLC Controllers with 256-Byte FIFOs
for the Insertion/Extraction of DS3 PMDL, G.751
Sn Bit, and G.832 NR/GC Bytes � On-Chip BERTs for PRBS and Repetitive Pattern
Generation, Detection, and Analysis � Large Performance-Monitoring Counters for
Accumulation Intervals of at Least 1 Second � Flexible Overhead Insertion/Extraction Ports for
DS3, E3 Framers
DS3171/DS3172/DS3173/DS3174
Single/Dual/Triple/Quad
DS3/E3 Single-Chip Transceivers
DS3171/DS3172/DS3173/DS3174
FEATURES (CONTINUED) � Loopbacks Include Line, Diagnostic, Framer,
Payload, and Analog with Capabilities to Insert
AIS in the Directions Away from Loopback
Directions � Ports can be Disabled to Reduce Power � Integrated Clock Rate Adapter to Generate the
Remaining Internally Required 44.736MHz (DS3)
and 34.368MHz (E3) from a Single Clock
Reference Source at One of Three Standard
Frequencies (DS3, E3, STS-1) Pin Compatible with the DS318x Family of
Devices and the DS316x Family of Devices � 8-/16-Bit Generic Microprocessor Interface � Low-Power (~1.73W) 3.3V Operation (5V
Tolerant I/O) � Small High-Density Thermally Enhanced Plastic
BGA Packaging (TE-PBGA) with 1.27mm Pitch � Industrial Temperature Operation:
-40°C to +85°C � IEEE1149.1 JTAG Test Port
DETAILED DESCRIPTION The DS3171 (single), DS3172 (dual), DS3173 (triple), and DS3174 (quad) perform framing, formatting, and line
transmission and reception. These devices contain integrated LIU(s), framer/formatter for M23 DS3, C-bit DS3,
G.751 E3, G.832 E3, or a combination of the above signal formats.
Each LIU has independent receive and transmit paths. The receiver LIU block performs clock and data recovery
from a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal, or can be bypassed for
direct clock and data inputs. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The transmitter LIU
drives standard pulse-shape waveforms onto 75Ω coaxial cable or can be bypassed for direct clock and data
outputs. The jitter attenuator can be placed in either transmit or receive data path when the LIU is enabled. The
DS3/E3 framers transmit and receive serial data in properly formatted M23 DS3, C-bit DS3, G.751 E3, or G.832 E3
data streams. Unused functions can be powered down to reduce device power. The DS317x DS3/E3 SCTs
conform to the telecommunications standards listed in Section 4.
DS3171/DS3172/DS3173/DS3174
1 BLOCK DIAGRAMS Figure 1-1 shows the external components required at each LIU interface for proper operation. Figure 1-2 shows
the functional block diagram of one channel DS3/E3 LIU.
Figure 1-1. LIU External Connections for a DS3/E3 Port of a DS317x Device 1:2ct
1:2ct
Transmit
Receive
TXP
TXN
RXP
RXN
0.01uF3.3V
Power
Plane
Ground
Plane
VDD
Each DS3/E3 LIU Interface
0.1uF1uF
330Ω
(1%)
330Ω
(1%)
0.01uF0.1uF1uF
0.01uF0.1uF1uF
VDD
VDD
VSS
VSS
VSS
Figure 1-2. DS317x Functional Block Diagram RLCLKn
RXPn
RXNn
TPOSn/TDATn
TNEGn
TLCLKn
Microprocessor
Interface
TXPn
TXNn
RDATn
RNEGn/RLCVn
RST
n = port # (1-4)
[15:0]
A[10:1]
ALE
/DS
/ R/
MOD
WIDTH
RDY
DS3/E3
Transmit
LIU
IEEE P1149.1
JTAG Test
Access Port
JTDO
JTCLK
JTMS
JTDI
JTRST
HDLCFEAC
LLBDS3 / E3
Transmit
Formatter
DS3 / E3
Receive
Framer
Trail
Trace
Buffer
ROHn
ROHCLKnROHSOFn
TCLKIn
RSERn
RCLKOn/RGCLKnRSOFOn/RDENn
DS3/E3
Receive
LIU
TAIS
TUA1
Clock Rate
Adapter
CLKA
CLKBCLKC
PLBUA1
GEN
TSERnB3ZS/
HDB3
Encoder
B3ZS/
HDB3
Decoder
TSOFIn
TX BERT
RX BERT
OFOn/TD
TOHnTO
HCL
TOHSOFnTO
HENn
On/TGC
DS317x
DS3171/DS3172/DS3173/DS3174
TABLE OF CONTENTS BLOCK DIAGRAMS 3 APPLICATIONS 12 FEATURE DETAILS 13 3.1 GLOBAL FEATURES........................................................................................................................................13
3.2 RECEIVE DS3/E3 LIU FEATURES..................................................................................................................13
3.3 RECEIVE DS3/E3 FRAMER FEATURES............................................................................................................13
3.4 TRANSMIT DS3/E3 FORMATTER FEATURES....................................................................................................13
3.5 TRANSMIT DS3/E3 LIU FEATURES................................................................................................................14
3.6 JITTER ATTENUATOR FEATURES.....................................................................................................................14
3.7 CLOCK RATE ADAPTER FEATURES.................................................................................................................14
3.8 HDLC OVERHEAD CONTROLLER FEATURES...................................................................................................14
3.9 FEAC CONTROLLER FEATURES.....................................................................................................................14
3.10 TRAIL TRACE BUFFER FEATURES...................................................................................................................15
3.11 BIT ERROR RATE TESTER (BERT) FEATURES................................................................................................15
3.12 LOOPBACK FEATURES...................................................................................................................................15
3.13 MICROPROCESSOR INTERFACE FEATURES......................................................................................................15
3.14 TEST FEATURES............................................................................................................................................15
STANDARDS COMPLIANCE 16 ACRONYMS AND GLOSSARY 17 MAJOR OPERATIONAL MODES 18 6.1 DS3/E3 SCT MODE.....................................................................................................................................18
6.2 DS3/E3 CLEAR CHANNEL MODE...................................................................................................................20
MAJOR LINE INTERFACE OPERATING MODES 21 7.1 DS3HDB3/B3ZS/AMI LIU MODE.................................................................................................................21
7.2 HDB3/B3ZS/AMI NON-LIU LINE INTERFACE MODE.......................................................................................23
7.3 UNI LINE INTERFACE MODE...........................................................................................................................24
PIN DESCRIPTIONS 25 8.1 SHORT PIN DESCRIPTIONS.............................................................................................................................25
8.2 DETAILED PIN DESCRIPTIONS.........................................................................................................................28
8.3 PIN FUNCTIONAL TIMING................................................................................................................................36
8.3.1 Line IO..................................................................................................................................................36
8.3.2 DS3/E3 Framing Overhead Functional Timing....................................................................................39
8.3.3 DS3/E3 Serial Data Interface...............................................................................................................40
8.3.4 Microprocessor Interface Functional Timing........................................................................................42
8.3.5 JTAG Functional Timing.......................................................................................................................47
INITIALIZATION AND CONFIGURATION 48 9.1 MONITORING AND DEBUGGING.......................................................................................................................49
10 FUNCTIONAL DESCRIPTION 50 10.1 PROCESSOR BUS INTERFACE.........................................................................................................................50
10.1.1 8/16 Bit Bus Widths..............................................................................................................................50
10.1.2 Ready Signal (RDY).............................................................................................................................50
10.1.3 Byte Swap Modes................................................................................................................................50
10.1.4 Read-Write / Data Strobe Modes.........................................................................................................50
10.1.5 Clear on Read / Clear on Write Modes................................................................................................50
10.1.6 Global Write Method............................................................................................................................51
10.1.7 Interrupt and Pin Modes.......................................................................................................................51
10.1.8 Interrupt Structure................................................................................................................................51
DS3171/DS3172/DS3173/DS3174
10.2.2 Sources of Clock Output Pin Signals...................................................................................................54
10.2.3 Line IO Pin Timing Source Selection...................................................................................................57
10.2.4 Clock Structures On Signal IO Pins.....................................................................................................59
10.2.5 Gapped Clocks.....................................................................................................................................60
10.3 RESET AND POWER-DOWN............................................................................................................................60
10.4 GLOBAL RESOURCES.....................................................................................................................................63
10.4.1 Clock Rate Adapter (CLAD).................................................................................................................63
10.4.2 8 kHz Reference Generation...............................................................................................................64
10.4.3 One Second Reference Generation.....................................................................................................66
10.4.4 General-Purpose IO Pins.....................................................................................................................66
10.4.5 Performance Monitor Counter Update Details.....................................................................................67
10.4.6 Transmit Manual Error Insertion..........................................................................................................68
10.5 PER PORT RESOURCES.................................................................................................................................69
10.5.1 Loopbacks............................................................................................................................................69
10.5.2 Loss Of Signal Propagation.................................................................................................................71
10.5.3 AIS Logic..............................................................................................................................................71
10.5.4 Loop Timing Mode...............................................................................................................................74
10.5.5 HDLC Overhead Controller..................................................................................................................74
10.5.6 Trail Trace............................................................................................................................................74
10.5.7 BERT....................................................................................................................................................74
10.5.8 SCT port pins.......................................................................................................................................74
10.5.9 Framing Modes....................................................................................................................................76
10.5.10 Line Interface Modes............................................................................................................................76
10.6 DS3/E3 FRAMER / FORMATTER.....................................................................................................................78
10.6.1 General Description.............................................................................................................................78
10.6.2 Features...............................................................................................................................................78
10.6.3 Transmit Formatter...............................................................................................................................79
10.6.4 Receive Framer....................................................................................................................................79
10.6.5 C-Bit DS3 Framer/Formatter................................................................................................................83
10.6.6 M23 DS3 Framer/Formatter.................................................................................................................86
10.6.7 G.751 E3 Framer/Formatter.................................................................................................................88
10.6.8 G.832 E3 Framer/Formatter.................................................................................................................90
10.7 HDLC OVERHEAD CONTROLLER....................................................................................................................96
10.7.1 General Description.............................................................................................................................96
10.7.2 Features...............................................................................................................................................96
10.7.3 Transmit FIFO......................................................................................................................................97
10.7.4 Transmit HDLC Overhead Processor..................................................................................................97
10.7.5 Receive HDLC Overhead Processor...................................................................................................98
10.7.6 Receive FIFO.......................................................................................................................................98
10.8 TRAIL TRACE CONTROLLER............................................................................................................................99
10.8.1 General Description.............................................................................................................................99
10.8.2 Features...............................................................................................................................................99
10.8.3 Functional Description........................................................................................................................100
10.8.4 Transmit Data Storage.......................................................................................................................100
10.8.5 Transmit Trace ID Processor.............................................................................................................100
10.8.6 Transmit Trail Trace Processing........................................................................................................100
10.8.7 Receive Trace ID Processor..............................................................................................................100
10.8.8 Receive Trail Trace Processing.........................................................................................................101
10.8.9 Receive Data Storage........................................................................................................................101
10.9 FEAC CONTROLLER...................................................................................................................................102
10.9.1 General Description...........................................................................................................................102
10.9.2 Features.............................................................................................................................................102
10.9.3 Functional Description........................................................................................................................102
10.10 LINE ENCODER/DECODER............................................................................................................................104
10.10.1 General Description...........................................................................................................................104
10.10.2 Features.............................................................................................................................................104
