DS3170 ,DS3/E3 Single-Chip Transceiverblock diagram of the one channel DS3/E3 SCT. Figure 1-1. LIU External Connections for the DS3/E3 Po ..
DS3170+ ,DS3/E3 Single-Chip TransceiverAPPLICATIONS Receive or Transmit Path Access Concentrators Multiservice Access Interfaces to 75 ..
DS3170DK ,DS3/E3 Single-Chip Transceiver Design Kit DS3170DK DS3/E3 Single-Chip Transceiver Design Kit
DS3170N ,DS3/E3 Single-Chip TransceiverFEATURES Single-Chip Transceiver for DS3 and E3 The DS3170 combines a DS3/E3 framer and an LIU ..
DS3170N+ ,DS3/E3 Single-Chip TransceiverFUNCTIONAL DESCRIPTION 53 10.1 PROCESSOR BUS INTERFACE ........ 53 10.1.1 SPI Serial Port Mode.. 53 ..
DS3171N+ ,Single/Dual/Triple/Quad DS3/E3 Single-Chip TransceiversFEATURES (CONTINUED) Devices and the DS316x Family of Devices Loopbacks Include Line, Diagnostic, ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS3170-DS3170N
DS3/E3 Single-Chip Transceiver
GENERAL DESCRIPTION The DS3170 combines a DS3/E3 framer and an LIU (single-chip transceiver) to interface to a DS3/E3
physical copper line.
APPLICATIONS Access Concentrators
Routers and Switches
Multiservice Access
Platforms (MSAPs)
SONET/SDH ADM
SONET/SDH Muxes
Multiservice Protocol
Platform (MSPPs)
PBXs Test Equipment
Digital Cross Connect PDH Multiplexer/ Demultiplexer Integrated-Access Device
(IAD)
ORDERING INFORMATION
FUNCTIONAL DIAGRAM
FEATURES Single-Chip Transceiver for DS3 and E3 Performs Receive Clock/Data Recovery and
Transmit Waveshaping for DS3 and E3 Jitter Attenuator can be Placed Either in the
Receive or Transmit Path Interfaces to 75� Coaxial Cable at Lengths Up to
380 Meters or 1246 Feet (DS3), or 440 Meters or 1443 Feet (E3) Uses 1:2 Transformers on Both Tx and Rx On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer Built-In HDLC Controller with 256-Byte FIFO for
the Insertion/Extraction of DS3 PMDL, G.751 Sn Bit, and G.832 NR/GC Bytes On-Chip BERT for PRBS and Repetitive Pattern Generation, Detection and Analysis Large Performance-Monitoring Counters for Accumulation Intervals of At Least 1 Second Flexible Overhead Insertion/Extraction Port for DS3, E3 Framers Loopbacks Include Line, Diagnostic, Framer, Payload, and Analog with Capabilities to Insert
AIS in the Directions Away from Loopback Directions Integrated Clock Rate Adapter to Generate the Remaining Internally Required 44.736MHz (DS3)
and 34.368MHz (E3) from a Single-Clock Reference Source CLAD Reference Clock can be 44.736MHz, 34.368MHz, 77.76MHz, 51.84MHz, or 19.44MHz Software Compatible with DS3171–DS3174 SCT Product Family 8-/16-Bit Parallel and Slave SPI Serial (≤10Mbps) Microprocessor Interface Low-Power (0.5W) 3.3V Operation (5V Tolerant I/O) 100-Pin Small 11mm (1mm) CSBGA and 14mm (1.4mm) LQFP Package Options Industrial Temperature Operation: -40°C to +85°C IEEE1149.1 JTAG Test Port
PRODUCT BRIEF
DS3170
DS3/E3 Single-Chip Transceiver
DS3170 DS3/E3 Single-Chip Transceiver
DETAILED DESCRIPTION The DS3170 is a software-configured, DS3/E3, single-chip transceiver (SCT). The line interface unit (LIU) has
independent receive and transmit paths. The receiver LIU block performs clock and data recovery from a B3ZS- or HDB3-coded AMI signal and monitors for loss of the incoming signal, and can be bypassed for direct clock and
data input. The receiver LIU block optionally performs B3ZS/HDB3 decoding. The transmitter LIU drives standard
pulse-shape waveforms onto 75� coaxial cable and can be bypassed for direct clock and data output. The jitter attenuator can be put in the transmit or receive data path when the LIU is enabled. Built-in DS3/E3 framers transmit
and receive data in properly formatted C-bit DS3, M23 DS3, G.751 E3 or G.832 E3 data streams. Functions not used are powered down to reduce system power requirements. The DS3170 conforms to the telecommunications
standards listed in Section 3.2.
1 BLOCK DIAGRAMS Figure 1-1 shows the external components required at the LIU interface for proper operation. Figure 1-2 shows the functional block diagram of the one channel DS3/E3 SCT.
Figure 1-1. LIU External Connections for the DS3/E3 Port of DS3170
DS3170 DS3/E3 Single-Chip Transceiver
Figure 1-2. Block Diagram DS3170 DS3/E3 Single-Chip Transceiver
TABLE OF CONTENTS BLOCK DIAGRAMS 2 APPLICATIONS 12 FEATURE DETAILS 13 3.1 GLOBAL FEATURES........................................................................................................................................13
3.2 RECEIVE DS3/E3 LIU FEATURES..................................................................................................................13 3.3 JITTER ATTENUATOR FEATURES.....................................................................................................................13
3.4 RECEIVE DS3/E3 FRAMER FEATURES...........................................................................................................13 3.5 TRANSMIT DS3/E3 FORMATTER FEATURES....................................................................................................14
3.6 TRANSMIT DS3/E3 LIU FEATURES.................................................................................................................14 3.7 CLOCK RATE ADAPTER FEATURES.................................................................................................................14
3.8 HDLC CONTROLLER FEATURES.....................................................................................................................14 3.9 FEAC CONTROLLER FEATURES.....................................................................................................................14
3.10 TRAIL TRACE BUFFER FEATURES...................................................................................................................15 3.11 BIT ERROR-RATE TESTER (BERT) FEATURES................................................................................................15
3.12 LOOPBACK FEATURES...................................................................................................................................15 3.13 MICROPROCESSOR INTERFACE FEATURES.....................................................................................................15
3.14 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES................................................................................15 3.15 TEST FEATURES............................................................................................................................................15
STANDARDS COMPLIANCE 16 ACRONYMS AND GLOSSARY 17 MAJOR OPERATIONAL MODES 18 6.1 DS3/E3 FRAMED LIU MODE..........................................................................................................................18 6.2 DS3/E3 UNFRAMED LIU MODE.....................................................................................................................20
6.3 DS3/E3 FRAMED POS/NEG MODE...............................................................................................................21 6.4 DS3/E3 UNFRAMED POS/NEG MODE..........................................................................................................22
6.5 DS3/E3 FRAMED UNI MODE.........................................................................................................................23 6.6 DS3/E3 UNFRAMED UNI MODE.....................................................................................................................24
PIN DESCRIPTIONS 25 7.1 SHORT PIN DESCRIPTIONS.............................................................................................................................25
7.2 DETAILED PIN DESCRIPTIONS.........................................................................................................................27 7.3 PIN FUNCTIONAL TIMING................................................................................................................................37
7.3.1 Line IO..................................................................................................................................................37 7.3.2 DS3/E3 Framing Overhead Functional Timing....................................................................................40
7.3.3 DS3/E3 Serial Data Interface...............................................................................................................41 7.3.4 Microprocessor Interface Functional Timing........................................................................................43
7.3.5 JTAG Functional Timing.......................................................................................................................50
INITIALIZATION AND CONFIGURATION 51 8.1 MONITORING AND DEBUGGING.......................................................................................................................52
FUNCTIONAL DESCRIPTION 53 9.1 PROCESSOR BUS INTERFACE.........................................................................................................................53 9.1.1 SPI Serial Port Mode............................................................................................................................53
9.1.2 8/16 Bit Bus Widths..............................................................................................................................53
9.1.3 Ready Signal (RDY).............................................................................................................................53 9.1.4 Byte Swap Modes................................................................................................................................53
9.1.5 Read-Write/Data Strobe Modes...........................................................................................................53 9.1.6 Clear on Read/Clear on Write Modes..................................................................................................53
9.1.7 Interrupt and Pin Modes.......................................................................................................................54 9.1.8 Interrupt Structure................................................................................................................................54
9.2 CLOCKS........................................................................................................................................................55 9.2.1 Line Clock Modes.................................................................................................................................55
DS3170 DS3/E3 Single-Chip Transceiver
9.2.5 Gapped Clocks.....................................................................................................................................63
9.3 RESET AND POWER-DOWN............................................................................................................................63 9.4 GLOBAL RESOURCES.....................................................................................................................................66
9.4.1 Clock Rate Adapter (CLAD).................................................................................................................66 9.4.2 8 kHz Reference Generation...............................................................................................................66
9.4.3 One Second Reference Generation.....................................................................................................67 9.4.4 General-Purpose IO Pins.....................................................................................................................68
9.4.5 Performance Monitor Counter Update Details.....................................................................................69 9.4.6 Transmit Manual Error Insertion..........................................................................................................70
9.5 PORT RESOURCES........................................................................................................................................71 9.5.1 Loopbacks............................................................................................................................................71
9.5.2 Loss Of Signal Propagation.................................................................................................................73 9.5.3 AIS Logic..............................................................................................................................................73
9.5.4 Loop Timing Mode...............................................................................................................................75 9.5.5 HDLC Overhead Controller..................................................................................................................75
9.5.6 Trail Trace............................................................................................................................................75 9.5.7 BERT....................................................................................................................................................75
9.5.8 System Port Pins..................................................................................................................................76 9.5.9 Framing Modes....................................................................................................................................77
9.5.10 Line Interface Modes............................................................................................................................77 9.6 DS3/E3 FRAMER / FORMATTER.....................................................................................................................79
9.6.1 General Description.............................................................................................................................79 9.6.2 Features...............................................................................................................................................79
9.6.3 Transmit Formatter...............................................................................................................................80 9.6.4 Receive Framer....................................................................................................................................80
9.6.5 C-bit DS3 Framer/Formatter................................................................................................................84 9.6.6 M23 DS3 Framer/Formatter.................................................................................................................87
9.6.7 G.751 E3 Framer/Formatter.................................................................................................................89 9.6.8 G.832 E3 Framer/Formatter.................................................................................................................91
9.7 HDLC OVERHEAD CONTROLLER....................................................................................................................96 9.7.1 General Description.............................................................................................................................96
9.7.2 Features...............................................................................................................................................97 9.7.3 Transmit FIFO......................................................................................................................................97
9.7.4 Transmit HDLC Overhead Processor..................................................................................................98 9.7.5 Receive HDLC Overhead Processor...................................................................................................98
9.7.6 Receive FIFO.......................................................................................................................................99 9.8 TRAIL TRACE CONTROLLER............................................................................................................................99
9.8.1 General Description.............................................................................................................................99 9.8.2 Features.............................................................................................................................................100
9.8.3 Functional Description........................................................................................................................100 9.8.4 Transmit Data Storage.......................................................................................................................101
9.8.5 Transmit Trace ID Processor.............................................................................................................101 9.8.6 Transmit Trail Trace Processing........................................................................................................101
9.8.7 Receive Trace ID Processor..............................................................................................................101 9.8.8 Receive Trail Trace Processing.........................................................................................................101
9.8.9 Receive Data Storage........................................................................................................................102 9.9 FEAC CONTROLLER...................................................................................................................................102
9.9.1 General Description...........................................................................................................................102 9.9.2 Features.............................................................................................................................................103
9.9.3 Functional Description........................................................................................................................103 9.10 LINE ENCODER/DECODER............................................................................................................................104
9.10.1 General Description...........................................................................................................................104 9.10.2 Features.............................................................................................................................................105
9.10.3 B3ZS/HDB3 Encoder.........................................................................................................................105 9.10.4 Transmit Line Interface......................................................................................................................105
9.10.5 Receive Line Interface.......................................................................................................................106
