DS3164N ,3.3 V, Single/dual/triple/quad ATM/packet PHY for DS3/E3/STS-1FEATURES Equipment Single (DS3161), Dual (DS3162), Triple Test Equipment (DS3163), or Quad (DS31 ..
DS3170 ,DS3/E3 Single-Chip Transceiverblock diagram of the one channel DS3/E3 SCT. Figure 1-1. LIU External Connections for the DS3/E3 Po ..
DS3170+ ,DS3/E3 Single-Chip TransceiverAPPLICATIONS Receive or Transmit Path Access Concentrators Multiservice Access Interfaces to 75 ..
DS3170DK ,DS3/E3 Single-Chip Transceiver Design Kit DS3170DK DS3/E3 Single-Chip Transceiver Design Kit
DS3170N ,DS3/E3 Single-Chip TransceiverFEATURES Single-Chip Transceiver for DS3 and E3 The DS3170 combines a DS3/E3 framer and an LIU ..
DS3170N+ ,DS3/E3 Single-Chip TransceiverFUNCTIONAL DESCRIPTION 53 10.1 PROCESSOR BUS INTERFACE ........ 53 10.1.1 SPI Serial Port Mode.. 53 ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS3164N
3.3 V, Single/dual/triple/quad ATM/packet PHY for DS3/E3/STS-1
GENERAL DESCRIPTION The DS3161, DS3162, DS3163, and DS3164
(DS316x) integrate ATM cell/HDLC packet processor(s) with DS3/E3 framer(s) to map/demap
ATM cells or packets into as many as four DS3/E3 digital lines with DS3-framed, E3-framed, or clear-
channel data streams on per-port basis.
APPLICATIONS Access Concentrators
SONET/SDH ADM
Multiservice Access
Platform (MSAP)
SONET/SDH Muxes
PBXs
Multiservice Protocol
Platform (MSPP)
Digital Cross Connect
Test Equipment
ATM and Frame Relay
Equipment
Routers and Switches
Integrated Access Device (IAD)
PDH Multiplexer/
Demultiplexer
ORDERING INFORMATION *Future productcontact factory for availability.
FUNCTIONAL DIAGRAM SYST
INTE
RFA
CELL/PACKET
PROCESSOR
DS316x
POS-PHYor
UTOPIADS3/E3 LINEINTERFACE
DS3/E3FRAMER/
FORMATTER
FEATURES Single (DS3161), Dual (DS3162), Triple (DS3163), or Quad (DS3164) ATM/Packet PHYs
for DS3, E3, and Clear-Channel 52Mbps (CC52) Pin Compatible for Ease of Port Density Migration in the Same PC Board Platform Each Port Independently Configurable Universal PHYs Map ATM Cells and/or HDLC
Packets into DS3 or E3 Data Streams UTOPIA L2/L3 or POS-PHY L2/L3 or SPI-3 Interface with 8-, 16-, or 32-Bit Bus Width 66MHz UTOPIA L3 and POS-PHY L3 Clock 52MHz UTOPIA L2 and POS-PHY L2 Clock Ports Independently Configurable for Cell or
Packet Traffic in POS-PHY Bus Modes Direct, PLCP, DSS, and Clear-Channel Cell Mapping Direct and Clear-Channel Packet Mapping On-Chip DS3 (M23 or C-Bit) and E3 (G.751 or
G.832) Framer(s) Ports Independently Configurable for DS3, E3 (Full or Subrate) or Arbitrary Framing Protocols
Up to 52Mbps Programmable (Externally Controlled or Internally Finite State Machine Controlled)
Subrate DS3/E3
DS3161/DS3162/DS3163/DS3164
Single/Dual/Triple/Quad
ATM/Packet PHYs for DS3/E3/STS-1POS-PHY and POS-PHY Level 3 are trademarks of PMC-Sierra, Inc.
DS3161/DS3162/DS3163/DS3164
FEATURES (continued) Full-Featured DS3/E3/PLCP Alarm Generation and Detection Built-In HDLC Controllers with 256-Byte FIFOs
for Insertion/Extraction of DS3 PMDL, G.751 Sn Bit, and G.832 NR/GC Bytes and PLCP NR/GC
Bytes On-Chip BERTs for PRBS and Repetitive Pattern Generation, Detection, and Analysis Large Performance-Monitoring Counters for Accumulation Intervals of at Least 1 Second Flexible Overhead Insertion/Extraction Ports for
DS3, E3, and PLCP Framers Pin and Software Compatible with DS3181–DS3184 Single–Quad ATM/Packet PHYs with
Built-In LIUs and DS3171–DS3174 Single–Quad DS3/E3 Single-Chip Transceivers—Framers and
LIUs
DETAILED DESCRIPTION The DS3161 (single), DS3162 (dual), DS3163 (triple), and DS3164 (quad) PHYs perform all the functions
necessary for mapping/demapping ATM cells and/or packets into as many as four DS3 (44.736Mbps) framed, E3 (34.368Mbps) framed, or 52Mbps clear-channel data streams. Dedicated cell processor and packet processor
blocks prepare outgoing cells or packets for transmission and check incoming cells or packets upon arrival. Built-in DS3/E3 framers transmit and receive cell/packet data in properly formatted M23 DS3, C-bit DS3, G.751 E3, or
G.832 E3 data streams. PLCP framers provide legacy ATM transmission-convergence support. DSS scrambling is performed for clear-channel ATM cell support. With integrated hardware support for both cells and packets, the
DS316x DS3/E3 ATM/Packet PHYs provide system-on-chip solutions (from DS3/E3/STS-1 digital lines to ATM/Packet UTOPIA/POS-PHY Level 2/3 system switch) for universal high-density line cards in the unchannelized
DS3/E3/clear-channel DS3 ATM/Packet applications. Unused functions can be powered down to reduce device power. The DS316x ATM/Packet PHYs with embedded framers conform to the telecommunications standards
listed in Section 4.
1 BLOCK DIAGRAMS Figure 1-1 shows the functional block diagram of one channel ATM/Packet PHY.
Figure 1-1. DS316x Functional Block Diagram
DS3161/DS3162/DS3163/DS3164
TABLE OF CONTENTS BLOCK DIAGRAM 2 APPLICATIONS 14 FEATURE DETAILS 16 3.1 GLOBAL FEATURES........................................................................................................................................16
3.2 RECEIVE DS3/E3 FRAMER FEATURES...........................................................................................................17 3.3 RECEIVE PLCP FRAMER FEATURES...............................................................................................................17
3.4 RECEIVE CELL PROCESSOR FEATURES..........................................................................................................17 3.5 RECEIVE PACKET PROCESSOR FEATURES......................................................................................................18
3.6 RECEIVE FIFO FEATURES.............................................................................................................................18 3.7 RECEIVE SYSTEM INTERFACE FEATURES........................................................................................................18
3.8 TRANSMIT SYSTEM INTERFACE FEATURES......................................................................................................18 3.9 TRANSMIT FIFO FEATURES...........................................................................................................................18
3.10 TRANSMIT CELL PROCESSOR FEATURES........................................................................................................18 3.11 TRANSMIT PACKET PROCESSOR FEATURES....................................................................................................19
3.12 TRANSMIT PLCP FORMATTER FEATURES.......................................................................................................19 3.13 TRANSMIT DS3/E3 FORMATTER FEATURES....................................................................................................19
3.14 CLOCK RATE ADAPTER FEATURES.................................................................................................................19 3.15 HDLC OVERHEAD CONTROLLER FEATURES...................................................................................................20
3.16 FEAC CONTROLLER FEATURES.....................................................................................................................20 3.17 TRAIL TRACE BUFFER FEATURES...................................................................................................................20
3.18 BIT ERROR RATE TESTER (BERT) FEATURES................................................................................................20 3.19 LOOPBACK FEATURES...................................................................................................................................20
3.20 MICROPROCESSOR INTERFACE FEATURES.....................................................................................................20 3.21 SUBRATE FEATURES (FRACTIONAL DS3/E3)..................................................................................................21
3.22 TEST FEATURES............................................................................................................................................21
STANDARDS COMPLIANCE 22 ACRONYMS AND GLOSSARY 24 MAJOR OPERATIONAL MODES 25 6.1 DS3/E3 ATM/PACKET MODE........................................................................................................................25
6.2 DS3/E3 ATM/PACKETOHM MODE............................................................................................................26 6.3 DS3/E3 INTERNAL FRACTIONAL (SUBRATE) ATM/PACKET MODE....................................................................27
6.4 DS3/E3 EXTERNAL FRACTIONAL (SUBRATE) ATM/PACKET MODE..................................................................28 6.5 DS3/E3 FLEXIBLE EXTERNAL FRACTIONAL (SUBRATE) MODE CONFIGURATION MODE.....................................29 6.6 DS3/E3 G.751 PLCP ATM MODE................................................................................................................30
6.7 DS3/E3 G.751 PLCP ATMOHM MODE....................................................................................................31
6.8 CLEAR-CHANNEL ATM/PACKET MODE...........................................................................................................33 6.9 CLEAR-CHANNEL ATM/PACKETOHM MODE...............................................................................................34
6.10 CLEAR-CHANNEL OCTET ALIGNED ATM/PACKETOHM MODE......................................................................35
MAJOR LINE INTERFACE OPERATING MODES 36 7.1 HDB3/B3ZS/AMI LINE INTERFACE MODE......................................................................................................36 7.2 UNI LINE INTERFACE MODE...........................................................................................................................37
7.3 UNI LINE INTERFACEOHM MODE...............................................................................................................38
PIN DESCRIPTIONS 39 8.1 SHORT PIN DESCRIPTIONS.............................................................................................................................39 8.2 DETAILED PIN DESCRIPTIONS.........................................................................................................................44
8.3 PIN FUNCTIONAL TIMING................................................................................................................................62 8.3.1 Line I/O.................................................................................................................................................62
8.3.2 DS3/E3 Framing and PLCP Overhead Functional Timing...................................................................65 8.3.3 Internal (IFRAC) and External (XFRAC) Fractional DS3/E3 Overhead Functional Timing.................68
DS3161/DS3162/DS3163/DS3164
8.3.6 Microprocessor Interface Functional Timing........................................................................................85
8.3.7 JTAG Functional Timing.......................................................................................................................90
INITIALIZATION AND CONFIGURATION 91 9.1 MONITORING AND DEBUGGING.......................................................................................................................93 9.1.1 Cell/Packet FIFO..................................................................................................................................93
9.1.2 Cell Processor......................................................................................................................................93 9.1.3 Packet Processor.................................................................................................................................93
10 FUNCTIONAL DESCRIPTION 94 10.1 PROCESSOR BUS INTERFACE.........................................................................................................................94
10.1.1 8/16-Bit Bus Widths..............................................................................................................................94
10.1.2 Ready Signal (RDY).............................................................................................................................94 10.1.3 Byte Swap Modes................................................................................................................................94
10.1.4 Read-Write/Data Strobe Modes...........................................................................................................94 10.1.5 Clear on Read/Clear on Write Modes..................................................................................................94
10.1.6 Global Write Method............................................................................................................................95 10.1.7 Interrupt and Pin Modes.......................................................................................................................95
10.1.8 Interrupt Structure................................................................................................................................95 10.2 CLOCKS........................................................................................................................................................97
10.2.1 Line Clock Modes.................................................................................................................................97 10.2.2 Sources of Clock Output Pin Signals...................................................................................................98
10.2.3 Line I/O Pin Timing Source Selection..................................................................................................99 10.2.4 Clock Structures On Signal IO Pins...................................................................................................102
10.2.5 Gapped Clocks...................................................................................................................................102 10.3 RESET AND POWER-DOWN..........................................................................................................................103
10.4 GLOBAL RESOURCES...................................................................................................................................105 10.4.1 Clock Rate Adapter (CLAD)...............................................................................................................105
10.4.2 8 kHz Reference Generation.............................................................................................................107 10.4.3 One-Second Reference Generation..................................................................................................109
10.4.4 General-Purpose I/O Pins..................................................................................................................109 10.4.5 Performance Monitor Counter Update Details...................................................................................111
10.4.6 Transmit Manual Error Insertion........................................................................................................111 10.5 PER PORT RESOURCES...............................................................................................................................112
10.5.1 Loopbacks..........................................................................................................................................112 10.5.2 Loss Of Signal Propagation...............................................................................................................114
10.5.3 AIS Logic............................................................................................................................................114 10.5.4 Loop Timing Mode.............................................................................................................................116
10.5.5 HDLC Overhead Controller................................................................................................................116 10.5.6 Trail Trace..........................................................................................................................................117
10.5.7 BERT..................................................................................................................................................117 10.5.8 Fractional Payload Controller.............................................................................................................117
10.5.9 PLCP/Fractional port pins..................................................................................................................117 10.5.10 Framing Modes..................................................................................................................................121
10.5.11 Mapping Modes..................................................................................................................................123 10.5.12 Line Interface Modes..........................................................................................................................127
10.6 UTOPIA/POS-PHY/SPI-3 SYSTEM INTERFACE...........................................................................................128 10.6.1 General Description...........................................................................................................................128
10.6.2 Features.............................................................................................................................................128 10.6.6 System Interface Bus Controller........................................................................................................129
10.7 ATM CELL / HDLC PACKET PROCESSING....................................................................................................134 10.7.1 General Description...........................................................................................................................134
10.7.2 Features.............................................................................................................................................134 10.7.3 Transmit Cell/Packet Processor.........................................................................................................135
10.7.4 Receive Cell/Packet Processor..........................................................................................................135 10.7.5 Cell Processor....................................................................................................................................136
10.7.6 Packet Processor...............................................................................................................................141
DS3161/DS3162/DS3163/DS3164
10.7.8 System Loopback...............................................................................................................................145
10.8 DS3/E3 PLCP FRAMER..............................................................................................................................146 10.8.1 General Description...........................................................................................................................146
10.8.2 Features.............................................................................................................................................146 10.8.3 Transmit PLCP Frame Processor......................................................................................................147
10.8.4 Receive PLCP Frame Processor.......................................................................................................147 10.8.5 Transmit DS3 PLCP Frame Processor..............................................................................................147
10.8.6 Receive DS3 PLCP Frame Processor...............................................................................................150 10.8.7 Transmit E3 PLCP Frame Processor.................................................................................................151
10.8.8 Receive E3 PLCP Frame Processor..................................................................................................154 10.9 FRACTIONAL PAYLOAD CONTROLLER...........................................................................................................156
10.9.1 General Description...........................................................................................................................156 10.9.2 Features.............................................................................................................................................156
10.9.3 Transmit Fractional Interface.............................................................................................................157 10.9.4 Transmit Fractional Controller............................................................................................................157
10.9.5 Receive Fractional Interface..............................................................................................................157 10.9.6 Receive Fractional Controller.............................................................................................................157
10.10 DS3/E3 FRAMER / FORMATTER...................................................................................................................159 10.10.1 General Description...........................................................................................................................159
10.10.2 Features.............................................................................................................................................159 10.10.3 Transmit Formatter.............................................................................................................................160
10.10.4 Receive Framer..................................................................................................................................160 10.10.5 C-bit DS3 Framer/Formatter..............................................................................................................164
10.10.6 M23 DS3 Framer/Formatter...............................................................................................................167 10.10.7 G.751 E3 Framer/Formatter...............................................................................................................169
10.10.8 G.832 E3 Framer/Formatter...............................................................................................................172 10.10.9 Clear-Channel Frame Processor.......................................................................................................177
10.11 HDLC OVERHEAD CONTROLLER..................................................................................................................177 10.11.1 General Description...........................................................................................................................177
10.11.2 Features.............................................................................................................................................178 10.11.3 Transmit FIFO....................................................................................................................................178
10.11.4 Transmit HDLC Overhead Processor................................................................................................179 10.11.5 Receive HDLC Overhead Processor.................................................................................................179
10.11.6 Receive FIFO.....................................................................................................................................180 10.12 TRAIL TRACE CONTROLLER..........................................................................................................................181
10.12.1 General Description...........................................................................................................................181 10.12.2 Features.............................................................................................................................................182
10.12.3 Functional Description........................................................................................................................182 10.12.4 Transmit Data Storage.......................................................................................................................182
10.12.5 Transmit Trace ID Processor.............................................................................................................183 10.12.6 Transmit Trail Trace Processing........................................................................................................183
10.12.7 Receive Trace ID Processor..............................................................................................................183 10.12.8 Receive Trail Trace Processing.........................................................................................................183
10.12.9 Receive Data Storage........................................................................................................................184 10.13 FEAC CONTROLLER...................................................................................................................................184
10.13.1 General Description...........................................................................................................................184 10.13.2 Features.............................................................................................................................................185
10.13.3 Functional Description........................................................................................................................185 10.14 LINE ENCODER/DECODER............................................................................................................................186
10.14.1 General Description...........................................................................................................................186 10.14.2 Features.............................................................................................................................................187
10.14.3 B3ZS/HDB3 Encoder.........................................................................................................................187 10.14.4 Transmit Line Interface......................................................................................................................188
10.14.5 Receive Line Interface.......................................................................................................................188 10.14.6 B3ZS/HDB3 Decoder.........................................................................................................................188
10.15 BERT.........................................................................................................................................................190
