DS3150T ,3.3V, DS3/E3/STS-1 Line Interface UnitBlock Diagram ........4 Figure 1-2. External Connections.......6 Figure 1-3. Receiver Jitter Tolera ..
DS3150T ,3.3V, DS3/E3/STS-1 Line Interface UnitAPPLICATIONS Interfaces Directly to a DSX Monitor Signal SONET/SDH and PDH Multiplexers (20dB Fla ..
DS3150T+ ,3.3V, DS3/E3/STS-1 Line Interface UnitAPPLICATIONS Interfaces Directly to a DSX Monitor Signal SONET/SDH and PDH Multiplexers (20dB Fla ..
DS3150T+ ,3.3V, DS3/E3/STS-1 Line Interface UnitPIN DESCRIPTIONS .....17 3.
DS3150TN+ ,3.3V, DS3/E3/STS-1 Line Interface UnitFEATURES The DS3150 performs all the functions necessary for Integrated Transmitter, Receiver, an ..
DS3152N+ ,Single/Dual/Triple/Quad DS3/E3/STS-1 LIUsFeatures continued on page 5. RXN DATAOR STS-1 AND DATA Dallas Semiconductor ORDERING INFORMATIO ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS3150Q-DS3150QN-DS3150T
3.3V, DS3/E3/STS-1 Line Interface Unit
GENERAL DESCRIPTION The DS3150 performs all the functions necessary for
interfacing at the physical layer to DS3, E3, and
STS-1 lines. The receiver performs clock and data recovery, B3ZS/HDB3 decoding, and loss-of-signal
monitoring. The transmitter encodes outgoing data and drives standards-compliant waveforms onto 75Ω
coaxial cable. The jitter attenuator can be mapped
into the receive path or the transmit path.
APPLICATIONS SONET/SDH and PDH Multiplexers
Digital Cross-Connects
Access Concentrators ATM and Frame Relay Equipment
Routers
PBXs DSLAMs
CSUs/DSUs
ORDERING INFORMATION
FUNCTIONAL DIAGRAM
FEATURES ��Integrated Transmitter, Receiver, and Jitter Attenuator for DS3, E3, and STS-1
��Performs Receive Clock/Data Recovery and
Transmit Waveshaping
��Jitter Attenuator Can Be Placed in the Receive
Path or the Transmit Path
��AGC/Equalizer Block Handles from 0dB to
15dB of Cable Loss
��Interfaces to 75� Coaxial Cable at Lengths Up to
380m (DS3), 440m (E3), or 360m (STS-1)
��Interfaces Directly to a DSX Monitor Signal
(20dB Flat Loss) Using Built-In Preamp
��Built-In B3ZS and HDB3 Encoder/Decoder
��Bipolar and NRZ Interfaces
��Local and Remote Loopbacks
��On-Board 215 - 1 and 223 - 1 Pseudorandom Bit
Sequence (PRBS) Generator and Detector
��Line Build-Out (LBO) Control
��Transmit Line-Driver Monitor Checks for a
Faulty Transmitter or a Shorted Output
��Complete DS3 AIS Generator (ANSI T1.107)
��Unframed All-Ones Generator (E3 AIS)
��Clock Inversion for Glueless Interfacing
��Tri-State Line Driver for Low-Power Mode and Protection Switching Applications
��Loss-of-Signal (LOS) Detector (ANSI T1.231
and ITU G.775)
��Requires Minimal External Components
��Drop-In Replacement for TDK 78P2241/B and
78P7200L (Refer to Application Note 362)
��Pin Compatible with TDK 78P7200
��3.3V Operation (5V Tolerant I/O), 110mA (max)
��Industrial Temperature Range: -40�C to +85�C
��Small Packaging: 28-Pin PLCC and
48-Pin TQFP
Pin Configurations appear at end of data sheet.
DS3150
3.3V, DS3/E3/STS-1 Line Interface Unit
DS3150
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................4 1.1 RECEIVER....................................................................................................................................7
1.2 TRANSMITTER.............................................................................................................................10
1.3 DIAGNOSTICS..............................................................................................................................15 1.4 JITTER ATTENUATOR...................................................................................................................16
2. PIN DESCRIPTIONS........................................................................................................17
3. ELECTRICAL CHARACTERISTICS................................................................................21
4. PIN CONFIGURATIONS..................................................................................................25
5. PACKAGE INFORMATION..............................................................................................26
6. REVISION HISTORY........................................................................................................28 DS3150
LIST OF FIGURES Figure 1-1. Block Diagram...........................................................................................................4
Figure 1-2. External Connections.................................................................................................6
Figure 1-3. Receiver Jitter Tolerance...........................................................................................9
Figure 1-4. E3 Waveform Template...........................................................................................13
Figure 1-5. DS3 AIS Structure...................................................................................................14
Figure 1-6. PRBS Output with Normal RCLK Operation............................................................15
Figure 1-7. PRBS Output with Inverted RCLK Operation...........................................................15
Figure 1-8. Jitter Attenuation and Jitter Transfer........................................................................16
Figure 3-1. Framer Interface Timing Diagram............................................................................22
LIST OF TABLES Table 1-A. Applicable Telecommunications Standards................................................................5
Table 1-B. Transformer Recommendations.................................................................................6
Table 1-C. DS3 Waveform Template.........................................................................................11
Table 1-D. DS3 Waveform Test Parameters and Limits............................................................11
Table 1-E. STS-1 Waveform Template......................................................................................12
Table 1-F. STS-1 Waveform Test Parameters and Limits.........................................................12
Table 1-G. E3 Waveform Test Parameters and Limits...............................................................13
Table 2-A. Pin Descriptions........................................................................................................17
Table 2-B. Transmit Data Selection...........................................................................................20
Table 2-C. RMON and TTS Signal Decode................................................................................20
DS3150
1. DETAILED DESCRIPTION The DS3150 performs all the functions necessary for interfacing at the physical layer to DS3, E3, and
STS-1 lines. The device has independent receive and transmit paths and a built-in jitter attenuator
(Figure 1-1). The receiver performs clock and data recovery from a B3ZS- or HDB3-coded alternate mark
inversion (AMI) signal and monitors for loss-of-signal. The receiver optionally performs B3ZS/HDB3 decoding and outputs the recovered data in either NRZ or bipolar format. The transmitter accepts data in
either NRZ or bipolar format, optionally performs B3ZS/HDB3 encoding, and drives standards-compliant
waveforms onto the outgoing 75Ω coaxial cable. The jitter attenuator can be mapped into the receiver
data path, mapped into the transmitter data path, or disabled. The DS3150 conforms to the
telecommunication standards listed in Table 1-A. Figure 1-2 shows the external components required for proper operation.
Figure 1-1. Block Diagram
DS3150
Table 1-A. Applicable Telecommunications Standards DS3150
Figure 1-2. External Connections Table 1-B. Transformer Recommendations
Note: Table subject to change. Industrial temperature range and dual transformers also available. Contact the manufacturers for details. DS3150
1.1 Receiver
Interfacing to the Line. The receiver can be transformer-coupled or capacitor-coupled to the line.
Typically, the receiver interfaces to the incoming coaxial cable (75�) through a 1:2 step-up transformer.
Figure 1-2 shows the arrangement of the transformer and other recommended interface components. The device expects the incoming signal to be in B3ZS- or HDB3-coded AMI format.
Optional Preamp. The receiver can be used in monitoring applications, which typically have series
resistors that result in a resistive loss of approximately 20dB. When the RMON input pin is high, the
receiver compensates for this resistive loss by applying flat gain to the incoming signal before sending the
signal to the equalizer block.
Adaptive Equalizer. The adaptive equalizer applies both frequency-dependent gain and flat gain to
offset signal losses from the coaxial cable and provides a signal of nominal amplitude and pulse shape to
the clock and data recovery block. The equalizer circuitry automatically adapts to coaxial cable losses
from 0 to 15dB, which translates into 0 to 380 meters (DS3), 0 to 440 meters (E3), or 0 to 360 meters (STS-1) of coaxial cable (AT&T 734A or equivalent). The equalizer can perform direct (0 meter)
monitoring of the transmitter output signal.
Clock and Data Recovery. The clock and data recovery (CDR) block takes the amplified, equalized signal from the equalizer and produces separate clock, positive data and negative data signals. The CDR
requires a master clock (44.736MHz for DS3, 34.368MHz for E3, 51.840MHz for STS-1). If the signal on MCLK is toggling, the device selects the MCLK signal as the master clock. If MCLK is wired high or
left floating, the device uses the signal on the TCLK pin as the master clock. If MCLK is wired low, the
device takes its master clock from an internal oscillator. The selected master clock is also used by the
jitter attenuator.
Loss-of-Signal Detector. The receiver contains both analog and digital LOS detectors. The analog
LOS detector resides in the equalizer block. If the incoming signal level is less than a signal level
approximately 24dB below nominal, analog loss-of-signal (ALOS) is declared. The ALOS signal cannot
be directly examined, but when ALOS occurs the equalizer mutes the recovered data, forcing all zeros out
of the clock and data recovery circuitry and subsequently causing digital loss-of-signal (DLOS), which is indicated on the LOS pin. ALOS clears when the incoming signal level is greater than or equal to a signal
level approximately 18dB below nominal.
The digital loss-of-signal detector declares DLOS when it detects 175 �75 consecutive zeros in the
recovered data stream. When DLOS occurs, the receiver asserts the LOS pin. DLOS is cleared when there
are no excessive zero occurrences over a span of 175 �75 clock periods. An excessive zero occurrence is
defined as three or more consecutive zeros in the DS3 and STS-1 modes and four or more consecutive
zeros in the E3 mode. The LOS pin is deasserted when the DLOS condition is cleared. The requirements of ANSI T1.231 and ITU-T G.775 for DS3 LOS defects are met by the DLOS detector,
which asserts LOS when it counts 175 �75 consecutive zeros coming out of the clock and data recovery
block and clears LOS when it counts 175 �75 consecutive pulse intervals without excessive zero
occurrences.
The requirements of ITU-T G.775 for E3 LOS defects are met by a combination of the ALOS detector
DS3150
For E3 LOS Assertion: 1) The ALOS circuitry detects that the incoming signal is less than or equal to a signal level
approximately 24dB below nominal and mutes the data coming out of the clock and data recovery block. (24dB below nominal is in the tolerance range of G.775, where LOS may or may not be
declared.)
2) The DLOS detector counts 175 �75 consecutive zeros coming out of the clock and data recovery
block and asserts LOS. (175 �75 meets the 10 � N � 255 pulse interval duration requirement of G.775.)
For E3 LOS Clear: 1) The ALOS circuitry detects that the incoming signal is greater than or equal to a signal level
approximately 18dB below nominal and enables data to come out of the clock and data recovery
block. (18dB below nominal is in the tolerance range of G.775 where LOS may or may not be declared.)
2) The DLOS detector counts 175 �75 consecutive pulse intervals without excessive zero occurrences
and deasserts LOS. (175 �75 meets the 10 � N � 255 pulse interval duration requirement of G.775.) The requirements of ANSI T1.231 for STS-1 LOS defects are supported by the DLOS detector. At STS-1
rate, the time required for the DLOS detector to count 175 �75 consecutive zeros falls in the range of
2.3�T�100�s required by ANSI T1.231 for declaring an LOS defect. Although the time required for the
DLOS detector to count 175 �75 consecutive pulse intervals with no excessive zeros is less than the
125µs to 250�s period required by ANSI T1.231 for clearing an LOS defect, a period of this length where
LOS is inactive can easily be timed in software.
During LOS, the RCLK output signal is derived from the devices master clock. The ALOS detector has a longer time constant than the DLOS detector. Thus, when the incoming signal is lost, the DLOS detector
activates first, asserting the LOS pin, followed by the ALOS detector. When a signal is restored, the
DLOS detector does not get a valid signal that it can qualify for no excessive zero occurrences until the
ALOS detector has seen the incoming signal rise above a signal level approximately 18dB below
nominal.
Framer Interface Format and the B3ZS/HDB3 Decoder. The recovered data can be output in
either NRZ or bipolar format. To select the bipolar format, wire the ZCSE input pin high. In this format,
the B3ZS/HDB3 decoder is disabled, and the recovered data is buffered and output on the RPOS and
RNEG output pins. Received positive-polarity pulses are indicated by RPOS = 1, while negative-polarity pulses are indicated by RNEG = 1. In bipolar interface format the receiver simply passes on the data
received and does not check it for bipolar violations or excessive zero occurrences.
To select the NRZ format, wire ZCSE low. In this format, the B3ZS/HDB3 decoder is enabled, and the
recovered data is decoded and output as a composite NRZ value on the RNRZ pin. Code violations are flagged on the RLCV pin. In the discussion that follows, a valid pulse that conforms to the AMI rule is
denoted as B. A pulse that violates the AMI rule is known as bipolar violation (BPV) and is denoted as V.
In DS3 and STS-1 modes, B3ZS decoding is performed. RLCV is asserted during any RCLK cycle where
the data on RNRZ causes ones of the following code violations:
DS3150
��A third consecutive zero (0, 0, 0)
In E3 mode, HDB3 decoding is performed. RLCV is asserted during any RCLK cycle where the data on
RNRZ causes one of the following code violations:
��A BPV immediately preceded by a valid pulse (B, V) or by a valid pulse and a zero (B, 0, V)
��A BPV with the same polarity as the last BPV
��A fourth consecutive zero (0, 0, 0, 0) When RLCV is asserted to flag a BPV, the RNRZ pin outputs a 1. The state bit that tracks the polarity of
the last BPV is toggled on every BPV, whether part of a valid B3ZS/HDB3 codeword or not.
To support a glueless interface to a variety of neighboring components, the polarity of RCLK can be
inverted using the ICE input pin. See the ICE pin description in Table 2-A for details.
Receiver Jitter Tolerance. The receiver exceeds the input jitter tolerance requirements of all
applicable telecommunication standards in Table 1-A. See the graphs in Figure 1-3.
Receiver Jitter Transfer. The jitter transfer performance of the receiver, with and without the jitter
attenuator enabled, is shown in Figure 1-8.
Figure 1-3. Receiver Jitter Tolerance
Note 1: All jitter tolerance curves are worst case over temperature, voltage, cable length (0 to 900 feet), and RMON pin setting.
Note 2: The low-frequency plateau seen in most of the jitter tolerance curves is not the actual performance of the DS3150 but rather
the limit of the measuring equipment (64 UIP-P). Actual jitter
tolerance in these low-frequency ranges is greater than or equal
to 64 UIP-P.
Note 3: Receiver jitter tolerance is not tested during production test.
DS3150
1.2 Transmitter
Transmit Clock. The clock applied at the TCLK input is used to clock in data on the TPOS/TNRZ and TNEG pins. If the jitter attenuator is not enabled in the transmit path, the signal on TCLK is the transmit
line clock and must be transmission quality (i.e., �20ppm frequency accuracy and low jitter). If the jitter attenuator is enabled in the transmit path, the signal on TCLK can be jittery and/or periodically gapped
(not exceeding 8 UI) but must still have an average frequency within �20ppm of the nominal line rate.
When enabled in the transmit path, the jitter attenuator generates the transmit line clock from the signal
applied on the MCLK pin. The signal on MCLK must, therefore, be a transmission-quality clock
(�20ppm frequency accuracy and low jitter). The duty cycle of TCLK is not restricted as long as the high and low times listed in Section 3 are met.
To support a glueless interface to a variety of neighboring components, the polarity of TCLK can be
inverted using the ICE input pin. See the ICE pin description in Table 2-A for details.
Framer Interface Format and the B3ZS/HDB3 Encoder. Data to be transmitted can be input in either NRZ or bipolar format. To select the bipolar format, wire the ZCSE input pin high. In this format,
the B3ZS/HDB3 encoder is disabled, and the data to be transmitted is sampled on the TPOS and TNEG
input pins. Positive-polarity pulses are indicated by TPOS = 1 while negative-polarity pulses are indicated
by TNEG = 1. TPOS and TNEG should not be active at the same time.
To select the NRZ format, wire ZCSE low. In this format, the B3ZS/HDB3 encoder is enabled, and the
data to be transmitted is sampled on the TNRZ pin. The TNEG pin is ignored in NRZ mode and should
be tied low.
Pattern Generation. The transmitter can generate a number of different patterns internally, including unframed all ones (E3 AIS), 1010
, and DS3 AIS. See Figure 1-5 for the structure of the DS3 AIS
signal. The TDS0 and TDS1 inputs are used to select these on-board patterns. Table 2-B indicates the
possible selections.
Waveshaping, Line Build-Out, Line Driver. The waveshaping block converts the transmit clock, positive data, and negative data signals into a single AMI signal that meets applicable
telecommunications standards when transmitted on 75� coaxial cable. Table 1-C through Table 1-G and
Figure 1-4 show the waveform template specifications and test parameters from ANSI T1.102, Telcordia
GR-253-CORE and GR-499-CORE, and ITU-T G.703.
Because DS3 and STS-1 signals must meet the waveform templates at the cross-connect through any
cable length from 0 to 450 feet, the waveshaping circuitry includes a selectable LBO feature. For cable
lengths of 225 feet or greater, the LBO pin should be low. When LBO is low, output pulses are driven
onto the coaxial cable without any preattenuation. For cable lengths less than 225 feet, LBO should be high. When LBO is high, pulses are preattenuated before being driven onto the coaxial cable. The LBO
circuitry provides attenuation that mimics the attenuation of 225 feet of coaxial cable.
To power down the transmitter and tri-state the TX+ and TX- output pins, pull the TTS input pin low.
Interfacing to the Line. The transmitter interfaces to the outgoing DS3/E3/STS-1 coaxial cable (75�) through a 2:1 step-down transformer connected to the TX+ and TX- output pins. Figure 1-2 shows the
DS3150
Transmit Driver Monitor. If the transmit driver monitor detects a faulty transmitter, it activates the
DM output pin. When the transmitter is tri-stated (TTS = 0), the transmit driver monitor is also disabled.
The transmitter is declared to be faulty when the transmitter outputs see a load of less than about 25�. The DM pin is only available in the TQFP package.
Transmitter Jitter Generation (Intrinsic). The transmitter meets the jitter generation requirements of all applicable standards, with or without the jitter attenuator enabled.
Transmitter Jitter Transfer. Without the jitter attenuator enabled in the transmit side, the transmitter passes jitter through unchanged. With the jitter attenuator enabled in the transmit side, the transmitter
meets the jitter transfer requirements of all applicable telecommunication standards in Table 1-A. See
Figure 1-8.
Table 1-C. DS3 Waveform Template
Table 1-D. DS3 Waveform Test Parameters and Limits DS3150
Table 1-E. STS-1 Waveform Template
Table 1-F. STS-1 Waveform Test Parameters and Limits DS3150
Figure 1-4. E3 Waveform Template
Table 1-G. E3 Waveform Test Parameters and Limits DS3150
Figure 1-5. DS3 AIS Structure M1 Subframe
M2 Subframe
M3 Subframe
M4 Subframe
M5 Subframe
M6 Subframe
M7 Subframe
Note 1: X1 is transmitted first.
Note 2: The 84 info bits contain the sequence 101010
, where the first 1 immediately follows each X, P, F, C, or M bit.
