DS31412 ,6-/8-/12-Channel DS3/E3 FramersFUNCTIONAL DESCRIPTION ... 18 7.1 PIN INVERSIONS AND FORCE HIGH/LOW ..... 18 7.2 TRANSMITTER LOGIC ..
DS3146N ,6-/8-/12-Channel DS3/E3 FramersAPPLICATIONS Large Performance-Monitoring Counters SONET/SDH Muxes Line, Diagnostic, and Payloa ..
DS3148 ,6-/8-/12-Channel DS3/E3 FramersAPPLICATIONS Large Performance-Monitoring Counters SONET/SDH Muxes Line, Diagnostic, and Payloa ..
DS3148N ,6-/8-/12-Channel DS3/E3 FramersFUNCTIONAL DESCRIPTION ... 18 7.1 PIN INVERSIONS AND FORCE HIGH/LOW ..... 18 7.2 TRANSMITTER LOGIC ..
DS3150DK ,Demo Kit for the DS3150 DS3/E3/STS-1 LIUPRELIMINARYDS3150DKDemo Kit for theDS3150 DS3/E3/STS-1 LIU
DS3150Q ,3.3V, DS3/E3/STS-1 Line Interface UnitApplications DS3150T 48 TQFP 0C to +70C Loss-of-Signal (LOS) Detector (ANSI T1.231 and ITU G.7 ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS31412-DS3148
6-/8-/12-Channel DS3/E3 Framers
GENERAL DESCRIPTION The DS3146/DS3148/DS31412 (DS314x) devices include all necessary circuitry to frame and format up
to 12 separate DS3 or E3 channels. Each framer in these devices is independently configurable to
support M23 DS3, C-Bit Parity DS3, or G.751 E3. The framers interface to a variety of line interface
units (LIUs), microprocessor buses, and other system components without glue logic. Each DS3/E3 framer
has its own HDLC controller, FEAC controller, and BERT, as well as full support for error detection and
generation, performance monitoring, and loopbacks.
APPLICATIONS SONET/SDH Muxes PDH Muxes
Digital Cross-Connect Systems Access Concentrators
ATM and Frame Relay Equipment Routers
FUNCTIONAL DIAGRAM
FEATURES ��6/8/12 Independent DS3/E3 Framers on a Single
Die
��Framing and Formatting to M23 DS3, C-Bit Parity DS3, and G.751 E3
��LIU Interface can be Binary (NRZ) or Dual-Rail
(POS/NEG)
��B3ZS/HDB3 Encoder and Decoder
��Generate and Detect DS3/E3 Alarms ��Integrated HDLC Controller for Each Channel
��Integrated FEAC Controller for Each Channel
��Integrated Bit Error-Rate Tester (BERT) for Each
Channel
��Large Performance-Monitoring Counters ��Line, Diagnostic, and Payload Loopbacks
��Externally Controlled Transmit Overhead
Insertion Port
��Support External Timing or Loop-Timing
��Framers can be Powered Down When Not Used ��8-Bit Processor Port Supports Muxed or
Nonmuxed Bus Operation (Intel or Motorola)
��3.3V Supply with 5V Tolerant I/O
��349-Pin, 27mm x 27mm BGA Package
��IEEE 1149.1 JTAG Support
ORDERING INFORMATION
DS3146/DS3148/DS314126-/8-/12-Channel DS3/E3 FramersPin Configurations appear at end of data sheet.
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
TABLE OF CONTENTS
1. BLOCK DIAGRAM..........................................................................................................................6
2. APPLICATION EXAMPLE..............................................................................................................6
3. MAIN FEATURES...........................................................................................................................7
4. STANDARDS COMPLIANCE.........................................................................................................8
5. PIN DESCRIPTION.........................................................................................................................9 5.1 TRANSMIT FORMATTER LIU INTERFACE PINS.................................................................................9
5.2 RECEIVE FRAMER LIU INTERFACE PINS.........................................................................................9
5.3 TRANSMIT FORMATTER SYSTEM INTERFACE PINS........................................................................10
5.4 RECEIVE FRAMER SYSTEM INTERFACE PINS................................................................................12
5.5 CPU BUS INTERFACE PINS.........................................................................................................14
5.6 JTAG INTERFACE PINS...............................................................................................................14
5.7 SUPPLY, TEST, AND RESET PINS.................................................................................................14
6. REGISTERS..................................................................................................................................15 6.1 STATUS REGISTER DESCRIPTION................................................................................................17
7. FUNCTIONAL DESCRIPTION......................................................................................................18 7.1 PIN INVERSIONS AND FORCE HIGH/LOW......................................................................................18
7.2 TRANSMITTER LOGIC DESCRIPTION.............................................................................................18
7.2.1 Transmit Clock.....................................................................................................................................18
7.2.2 Loss-of-Clock Detection.......................................................................................................................19
7.3 RECEIVER LOGIC........................................................................................................................19
7.4 ERROR INSERTION......................................................................................................................20
7.5 LOOPBACKS...............................................................................................................................20
7.5.1 Line Loopback......................................................................................................................................20
7.5.2 Diagnostic Loopback............................................................................................................................20
7.5.3 Payload Loopback................................................................................................................................20
7.5.4 BERT and Loopback Interaction..........................................................................................................20
7.6 COMMON AND LINE INTERFACE REGISTERS.................................................................................22
7.6.1 Master Status Register (MSR).............................................................................................................29
7.7 DS3/E3 FRAMER.......................................................................................................................33
7.8 DS3/E3 PERFORMANCE ERROR COUNTERS................................................................................43
7.9 BERT........................................................................................................................................46
7.10 HDLC CONTROLLER...............................................................................................................54
7.10.1 Receive Operation...............................................................................................................................54
7.10.2 Transmit Operation..............................................................................................................................55
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
8. OPERATION DETAILS.................................................................................................................68 8.1 RESET.......................................................................................................................................68
8.2 DS3 AND E3 MODE CONFIGURATION..........................................................................................68
8.3 LIU AND SYSTEM INTERFACE CONFIGURATION.............................................................................68
8.4 LOOPBACK MODES.....................................................................................................................69
8.5 TRANSMIT OVERHEAD INSERTION................................................................................................69
9. JTAG INFORMATION...................................................................................................................70 9.1 JTAG TAP CONTROLLER STATE MACHINE..................................................................................70
9.2 JTAG INSTRUCTION REGISTER AND INSTRUCTIONS......................................................................72
9.3 JTAG SCAN REGISTERS.............................................................................................................73
10. DC ELECTRICAL CHARACTERISTICS.......................................................................................74
11. AC TIMING CHARACTERISTICS.................................................................................................75 11.1 SYSTEM INTERFACE TIMING.....................................................................................................75
11.2 MICROPROCESSOR INTERFACE TIMING.....................................................................................78
11.3 JTAG INTERFACE TIMING........................................................................................................83
12. PIN ASSIGNMENTS.....................................................................................................................84
13. PACKAGE INFORMATION...........................................................................................................88
14. THERMAL INFORMATION...........................................................................................................89
15. REVISION HISTORY.....................................................................................................................89 DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
LIST OF FIGURES Figure 1-1. Block Diagram.......................................................................................................................6
Figure 2-1. Application Example: 12-Port Unchannelized DS3/E3 Card..................................................6
Figure 5-1. Transmit Formatter Timing..................................................................................................11
Figure 5-2. Receive Framer Timing.......................................................................................................13
Figure 6-1. Status Register Interrupt Flow.............................................................................................17
Figure 7-1. Transmit Data Block Diagram..............................................................................................18
Figure 7-2. Transmit Clock Block Diagram............................................................................................19
Figure 7-3. Receiver Block Diagram......................................................................................................19
Figure 7-4. MSR Status Bit Interrupt Signal Flow...................................................................................32
Figure 7-5. T3E3SR Status Bit Interrupt Signal Flow.............................................................................40
Figure 7-6. BERT Status Bit Interrupt Signal Flow.................................................................................51
Figure 7-7. HDLC Status Bit Interrupt Signal Flow.................................................................................60
Figure 7-8. FEAC Status Bit Interrupt Signal Flow.................................................................................66
Figure 9-1. JTAG Block Diagram...........................................................................................................70
Figure 9-2. JTAG TAP Controller State Machine...................................................................................71
Figure 11-1. Data Path Timing Diagram................................................................................................76
Figure 11-2. TCCLK Data Path Timing Diagram....................................................................................76
Figure 11-3. Line Loopback Timing Diagram.........................................................................................77
Figure 11-4. SCLK Clock Timing...........................................................................................................78
Figure 11-5. Microprocessor Interface Timing Diagram (Nonmultiplexed)..............................................79
Figure 11-6. Microprocessor Interface Timing Diagram (Multiplexed)....................................................81
Figure 11-7. JTAG Interface Timing Diagram........................................................................................83
Figure 12-1. DS3146 Pin Configuration.................................................................................................85
Figure 12-2. DS3148 Pin Configuration.................................................................................................86
Figure 12-3. DS31412 Pin Configuration...............................................................................................87
DS3146/DS3146/DS31412 6-/8-/12-Channel DS3/E3 Framers
LIST OF TABLES Table 4-A. Applicable Telecommunications Standards............................................................................8
Table 6-A. Register Map........................................................................................................................15
Table 6-B. Status Register Set Example................................................................................................17
Table 7-A. BERT/Loopback InteractionPayload Bits..........................................................................20
Table 7-B. BERT/Loopback InteractionOverhead Bits........................................................................21
Table 7-C. Common Line Interface Register Map..................................................................................22
Table 7-D. DS3/E3 Framer Register Map..............................................................................................33
Table 7-E. DS3 Alarm Criteria...............................................................................................................41
Table 7-F. E3 Alarm Criteria..................................................................................................................41
Table 7-G. BERT Register Map.............................................................................................................46
Table 7-H. HDLC Register Map.............................................................................................................55
Table 7-I. FEAC Register Map...............................................................................................................64
Table 9-A. JTAG Instruction Codes.......................................................................................................72
Table 9-B. JTAG ID Code......................................................................................................................73
Table 10-A. Recommended DC Operating Conditions...........................................................................74
Table 10-B. DC Electrical Characteristics..............................................................................................74
Table 11-A. Data Path Timing...............................................................................................................75
Table 11-B. TCCLK Data Path Timing...................................................................................................75
Table 11-C. Line Loopback Timing........................................................................................................77
Table 11-D. Microprocessor Interface Timing........................................................................................78
Table 11-E. JTAG Interface Timing.......................................................................................................83
Table 12-A. Global Pin Assignments (Sorted by Signal Name)..............................................................84
Table 12-B. Per-Framer Pin Assignments (Sorted by Signal Name)......................................................84
Table 13-A. Thermal Properties, Natural Convection.............................................................................89
Table 13-B. Theta-JA (�JA) vs. Airflow....................................................................................................89
