DS3134 Fast Delivery |IC PHOENIX CO.,LIMITED

DS3134 ,CHATEAUFEATURES• 256 Channel HDLC Controller that Supports • BERT function can be assigned to anyup to 64 ..
DS3141 ,Single/Dual/Triple/Quad DS3/E3 FramersAPPLICATIONS Line, Diagnostic, and Payload Loopbacks SONET/SDH Muxes Externally Controlled Tran ..
DS3141+ ,Single/Dual/Triple/Quad DS3/E3 FramersAPPLICATIONS Line, Diagnostic, and Payload Loopbacks SONET/SDH Muxes Externally Controlled Tran ..
DS31412 ,6-/8-/12-Channel DS3/E3 FramersFUNCTIONAL DESCRIPTION ... 18 7.1 PIN INVERSIONS AND FORCE HIGH/LOW ..... 18 7.2 TRANSMITTER LOGIC ..
DS3146N ,6-/8-/12-Channel DS3/E3 FramersAPPLICATIONS Large Performance-Monitoring Counters SONET/SDH Muxes Line, Diagnostic, and Payloa ..
DS3148 ,6-/8-/12-Channel DS3/E3 FramersAPPLICATIONS Large Performance-Monitoring Counters SONET/SDH Muxes Line, Diagnostic, and Payloa ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..

DS3134
CHATEAU
FEATURES256 Channel HDLC Controller that Supports
up to 64 T1 or E1 Lines or Two T3 Lines256 Independent bi-directional HDLC
channels16 physical ports (16 Tx & 16 Rx) that can
be configured as either channelized or
unchannelizedTwo fast (52 Mbps) ports/other ports capable
of speeds up to 10 Mbps (unchannelized)Channelized Ports 0 to 15 handle one, two or
four T1 or E1 linesSupports up to 64 T1 or E1 data streamsPer channel DS0 loopbacks in both directionSupport transparent ModeV.54 loopback code detectorOnboard Bit Error Rate Tester (BERT) with
auto error insertion capabilityBERT function can be assigned to any
HDLC channel or any port104 Mbps full duplex throughputLarge 16 kbits FIFO in both receive and
transmit directionsEfficient scatter / gather DMAReceive data packets are Time stampedTransmit packet priority settingLocal bus allows for PCI bridging or local
accessIntel or Motorola bus signals supported25 MHz to 33 MHz 32-bit PCI (V2.1)
backplane interface3.3V low power CMOS with 5V tolerant I/OJTAG support IEEE 1149.1256 Lead Plastic BGA (27 mm x 27 mm)
DESCRIPTION
The DS3134 Chateau device is a 256-channel HDLC controller. The DS3134 is capable of handling up to
64 T1 or E1 data streams or 2 T3 data streams. Each of the 16 physical ports can handle one, two or four
T1 or E1 data streams. The Chateau consists of the following blocks:Layer BlockHDLC BlockFIFO BlockDMA BlockPCI BusLocal Bus
DS3134
Chateau – Channelized T1 And
E1 And HDLC Controller
DS3134
There are 16 HDLC Engines (one for each port) that are capable of operating at speeds up to 8.192 Mbps
in channelized mode and up to 10 Mbps in unchannelized mode. There are also two Fast HDLC Engines,
which only reside on Ports 0 and 1 and they are capable of operating at speeds up to 52 Mbps.
Applications/Markets include:Channelized T1/E1Clear channel (unchannelized) T1/E1Channelized T3/E3Dual clear channel (unchannelized) T3/E3High density Frame Relay accessxDSL (each port can support up to 10 Mbps)Dual HSSIV.35SONET/SDH EOC/ECC TerminationAny applications require large number of HDLC channels
The device fully meets the following specifications: ANSI (American National Standards Institute)
T1.403-1995 Network-to-Customer Installation DS1 Metallic Interface March 21, 1995 and PCI Local
Bus Specification V2.1 June 1, 1995. ITU Q.921 March 1993 and ISO Standard 3309-1979 Data
Communications – HDLC Procedures – Frame Structure.
DS3134
REVISION HISTORY
Version 1 (1/30/98)
Original release.
Version 2 (4/4/98)
1. Assigned signals to leads (Section 2.1).
2. Added more information to Sections 1, 5, 7, and 10.
3. Removed the P3VEN signal pin (Section 2.1 and 2.5).
4. Added FIFO Priority Control bits to the MC register (Section 4.2).
5. Added Abort and Bit Stuffing Control bits to the RHCD and THCD registers (Section 6.2).
6. Changed the Absolute Maximum Voltage Rating and IOH numbers (Section 12).
7. Changed the Low Water Mark definition (Section 7.1).
8. Added Section 14 on Applications.
Version 3 (6/22/98)
1. Corrected JTRST* lead from V19 to U19 (Section 2.1).
2. Added TEST lead at C3 (Section 2.1).
3. Added the Valid Receive Done Queue Descriptor bit (Section 8.1.4).
4. Corrected JTAG Device Code from 0000614Ch to 00006143h (Section 11.3).
5. Changed the order of the TABTE & TZSD bits in the THCD Register (Section 6.2).
6. Added JTAG Scan Control Information into Table 11.4A (Section 11.4).
7. Added Minimum Grant & Maximum Latency Settings to PINTL0 (Section 9.2).
8. Remove the HDLC channel restriction that required channels 1 to 128 to be assigned to ports 0 to 7
and HDLC channels 129 to 256 to be assigned to port 8 to 15 (Sections 1, 5.1, 5.3 and 6.1).
Version 4 (11/18/98)
1. Added information about queues full and empty states (Sections 8.1.3, 8.1.4, 8.2.3, and 8.2.4).
2. Changed BERT ones and zeros detector from 32 consecutive to 31 consecutive (Section 5.6).
3. Changed BERT Bit and Error Counters to count during loss of receive synchronization (Section 5.6).
4. Corrected Table 1E (Section 1).
5. Added bit numbers to register descriptions.
6. Changed Local Bus Configuration Mode AC Timing Parameter A7 from 5ns to 40ns. (Section 12).
Version 5 (09/01/99)
1. Typos corrections and add clarifications.(Section 2.5, 3.5, 4.4, 5.3, 5.5, 5.6, 6.2, 7.1, 8.1.1, 8.2.3)
2. Change the number of T1/E1 support from 64 to 56 due to design over sight (Section 1)
3. Added clarifications for Receive High Water Mark and corrected Transmit Low Water Mark to a
value from 1 to smaller or equal to N –2, where N = the number of linked blocks.
4. Removed bit 1 of the RDMAQ register, this function is automatically implemented. Please refer to
section 8.1.3 (page 90)
5. Figure 10.3A signal LRD* is moved back one LCLK cycle to align with the rising edge of LCLK #1.
6. Figure 103B signal LWR* is moved back one LCLK cycle to align with the rising edge of LCLC #1.
DS3134
Version 6 (05/01/00) Rev B1/B2 silicon release
1. Typo correction on the following pages: 7, 53, 61, 80, 107, 114 and 115
2. Add (notes) clarifications on the following pages: 60, 63, 73, 76, 87, 88, 90, 93, 95, 110, 111 and 117
3. Update Layer 1 configuration restrictions for silicon Rev B1/B2 release, on page 10.
4. Update reset wait cycles on page 11.
5. Remove bit 1 form register RDMAQ on page 97.
6. Local Bus timing update, corrected t3 and t6 on page 169.
7. Change the number of T1/E1 support from 56 back to 64 (Section 1), this will be supported in the
next rev of silicon.
8. Added a product preview page.
Version 7 (09/15/00)
1. Update figure 9.1C.
2. Update figure 14C in Section 14.
3. Typo correction.
DS3134
TABLE OF CONTENTS
Section 1: Introduction……………………………………………………………………………………..7
Section 2: Signal Description……………………………………………………………………………16
2.1 Overview / Signal Lead List…………………………………………………………………16
2.2 Serial Port Interface Signal Description……………………………………………………22
2.3 Local Bus Signal Description……………………………………………………………….24
2.4 JTAG Signal Description……………………………………………………………………27
2.5 PCI Bus Signal Description…………………………………………………………………28
2.6 Supply & Test Signal Description…………………...……………………………………..31
Section 3: Memory Map…………………………………………………………………………………32
3.0 Introduction…………………………………………………………………………………..32
3.1 General Configuration Registers…………………………………………………………..32
3.2 Receive Port Registers……………………………………………………………………..33
3.3 Transmit Port Registers…………………………………………………………………….33
3.4 Channelized Port Registers………………………………………………………………..34
3.5 HDLC Registers…………………………………………………………………………….35
3.6 BERT Registers……………………………………………………………………………..35
3.7 Receive DMA Registers…………………………………………………………………….35
3.8 Transmit DMA Registers……………………………………………………………………36
3.9 FIFO Registers………………………………………………………………………………36
3.10 PCI Configuration Registers for Function 0…………………………………………….36
3.11 PCI Configuration Registers for Function 1…………………………………………….37
Section 4: General Device Configuration & Status/Interrupt…………………………………………..37
4.1 Master Reset & ID Register Description………………………………………………….37
4.2 Master Configuration Register Description……………………………………………….38
4.3 Status & Interrupt……………………………………………………………………………40
4.3.1 Status & Interrupt General Description………………………………………40
4.3.2 Status & Interrupt Register Description………………………………………43
4.4 Test Register Description…………………………………………………………………..50
Section 5: Layer One……………………………………………………………………………………51
5.1 General Description…………………………………………………………………………51
5.2 Port Register Description…………………………………………………………………..55
5.3 Layer One Configuration Register Description…………………………………………..59
5.4 Receive V.54 Detector……………………………………………………………………..65
5.5 BERT…………………………………………………………………………………………69
5.6 BERT Register Description………………………………………………………………..70
Section 6: HDLC…………………………………………………………………………………………77
6.1 General Description………………………………………………………………………..77
6.2 HDLC Register Description……………………………………………………………….79
DS3134
Section 7: FIFO…………………………………………………………………………………………85
7.1 General Description & Example………………………………………………………….85
7.2 FIFO Register Description………………………………………………………………..87
Section 8: DMA…………………………………………………………………………………………96
8.0 Introduction…………………………………………………………………………………96
8.1 Receive Side……………………………………………………………………………….97
8.1.1 Overview……………………………………………………………………….97
8.1.2 Packet Descriptors…………………………………………………………….103
8.1.3 Free Queue…………………………………………………………………….105
8.1.4 Done Queue……………………………………………………………………110
8.1.5 DMA Configuration RAM……………………………………………………..116
8.2 Transmit Side……………………………………………………………………………….120
8.2.1 Overview………………………………………………………………………..120
8.2.2 Packet Descriptors…………………………………………………………….129
8.2.3 Pending Queue…………………………………………………………………132
8.2.4 Done Queue…………………………………………………………………….136
8.2.5 DMA Configuration RAM………………………………………………………142
Section 9: PCI Bus………………………………………………………………………………………147
9.1 PCI General Description……………………………………………………………………147
9.2 PCI Configuration Register Description…………………………………………………..153
Section 10: Local Bus…………………………………………………………………………………165
10.1 Local Bus General Description…………………………………………………………..165
10.2 Local Bus Bridge Mode Control Register Description…………………………………171
10.3 Examples of Bus Timing for Local Bus PCI Bridge Mode Operation………………..173
Section 11: JTAG………………………………………………………………………………………181
11.1 JTAG Operation……………………………………………………………………………181
11.2 TAP Controller State Machine Description……………………………………………..181
11.3 Instruction Register and Instructions……………………………………………………184
11.4 Test Registers……………………………………………………………………………..185
Section 12: AC Characteristics………………………………………………………………………….191
Section 13: Mechanical Dimensions…………………………………………………………………….173
Section 14: Applications………………………………………………………………………………174
DS3134
SECTION 1: INTRODUCTION
The DS3134 Chateau device is a 256 channels HDLC controller. The primary features of the device are
listed in Table 1A. This data sheet is split in Sections along the major the blocks of the device as shown
in Figure 1A. Throughout the data sheet, certain terms will be used and these terms are defined in Table
1B. The DS3134 device is designed to meet certain specifications and a listing of these governing
specifications is shown in Table 1C.
DS3134 BLOCK DIAGRAM Figure 1A
RC2
RD2
RS2
TC2
TD2
TS2
JTDO
PCLK
PAD[31:0]
PRST*
PCBE[3:0]*
PPAR
PFRAME*
PIRDY*
PTRDY*
PSTOP*
PIDSEL
PDEVSEL*
PREQ*
PGNT*
PPERR*
PSERR*
RC15
RD15
RS15
TC15
TD15
TS15
RC0RD0
RS0TC0
TD0TS0
RC1
RD1RS1
TC1TD1
TS1
PXAS*
PXDS*
PXBLAST*
JTRST*
JTDIJTMS
JTCLK
LA[19:0]
LD[15:0]
LWR*(LR/W*)
LRD*(LDS*)
LIM
LINT*
LRDY*
LMS
LCS*
LHOLD(LBR*)
LHLDA(LBG*)
LBGACK*
LCLK
the device is in
the MOT mode
LBHE*
DS3134
DS3134 FEATURE LIST Table 1A
LayerCan Support Up to 64 T1 or E1 Data Streams or Two T3 Data Streams
One16 Independent Physical Ports all Capable of Speeds Up to 10 MHz
Two of These Ports are also Capable of Speeds Up to 52 MHz
Each Port can be Independently Configured for Either Channelized or Unchannelized Operation
Each Physical Channelized Port can Handle One, Two, or Four T1 or E1 Data Streams
Supports N x 64 kbps and N x 56 kbps
Onboard V.54 Loopback Detector
Onboard BERT Generation and Detection
Per DS0 Channel Loopback in Both Directions
Unchannelized Loopbacks in Both Directions
HDLC256 Independent Channels
104 Mbps throughput in both the Receive and Transmit Directions
Transparent Mode
Two Fast HDLC Controllers Capable of Operating Up to 52 MHz
Automatic Flag Detection and Generation
Shared Opening and Closing Flag
Interfame Fill
Zero Stuffing and Destuffing
CRC16/32 Checking and Generation
Abort Detection and Generation
CRC Error and Long/Short Frame Error Detection
Bit Flip
Invert Data
FIFOLarge 16 kB Receive and 16 kB Transmit Buffers Maximize PCI Bus Efficiency
Small Block Size of 16 Bytes Allows Maximum Flexibility
Programmable Low and High Water Marks
Programmable HDLC Channel Priority Setting
DMAEfficient Scatter-Gather DMA Minimizes PCI Bus Accesses
Programmable Small and Large Buffer Sizes Up to 8191 Bytes & Algorithm Select
Descriptor Bursting to Conserve PCI Bus Bandwidth
Programmable Packet Storage Address Offset
Identical Receive & Transmit Descriptors Minimize Host Processing in Store-and-Forward
Automatic Channel Disabling and Enabling on Transmit Errors
Receive Packets are Timestamped
Transmit Packet Priority Setting
PCI32-Bit 33 MHz
BusVersion 2.1 Compliant
Contains Extension Signals that Allow Adoption to Custom Buses
Can Burst Up to 256 32-Bit Words to Maximize Bus Efficiency
DS3134
LocalCan Operate as a Bridge from the PCI Bus or a Configuration Bus
BusIn Bridge Mode; can arbitrate for the Bus
8 or 16 Bits Wide
In Bridge Mode, Supports a 1M Byte Address Space
Supports both Intel and Motorola Bus Timing
JTAG TEST ACCESS
3.3V LOW POWER CMOS WITH 5V TOLERANT INPUTS AND OUTPUTS
256 LEAD PLASTIC BGA PACKAGE (27 MM X 27 MM)
DS3134
DATA SHEET DEFINITIONS Table 1B
Acronym
Or TermDefinition
BERTBit Error Rate Tester.
DescriptorA message passed back and forth between the DMA and the Host.
DwordDouble Word. A 32-bit data entity.
DMADirect Memory Access.
FIFOFirst In First Out. Temporary memory storage scheme.
HDLCHigh level Data Link Control.
HostThe main controller that resides on the PCI Bus.
n/aNot Assigned.
V.54A pseudorandom pattern used to control loopbacks (see ANSI T1.403)
GOVERNING SPECIFICATIONS Table 1C
ANSI (American National Standards Institute) T1.403-1995 Network-to-Customer Installation DS1
Metallic Interface March 21, 1995.
PCI Local Bus Specification V2.1 June 1, 1995.
GENERAL DESCRIPTION
The Layer One Block handles the physical input and output of serial data to and from the DS3134. The
DS3134 is capable of handling up to 64 T1 or E1 data streams or 2 T3 data streams. Each of the 16
physical ports can handle up to two or four T1 or E1 data streams. Section 14 contains some examples of
how this is performed. The Layer One Block prepares the incoming data for the HDLC Block and grooms
data from the HDLC Block for transmission. The block has the ability to perform both channelized and
unchannelized loopbacks as well as search for V.54 loop patterns. It is in the Layer One Block that the
Host will enable HDLC channels and assign them to a particular port and/or DS0 channel(s). The Host
assigns HDLC channels via the R[n]CFG[j] and T[n]CFG[j] registers, which are described in Section 5.3.
The Layer One Block interfaces directly to the Bit Error Rate Tester (BERT) Block. The BERT Block
can generate and detect both pseudorandom and repeating bit patterns and it is used to test and stress data
communication links.
The HDLC Block consists of two types of HDLC controllers. There are 16 Slow HDLC Engines (one for
each port) that are capable of operating at speeds up to 8.192 Mbps in channelized mode and up to
10 Mbps in unchannelized mode. There are also two Fast HDLC Engines, which only reside on Ports 0
and 1 and they are capable of operating at speeds up to 52 Mbps. Via the RP[n]CR and TP[n]CR
registers in the Layer One Block, the Host will configure Port 0 and 1 to use either the Slow or the Fast
HDLC engine. The HDLC Engines perform all of the Layer 2 processing which include, zero stuffing
and destuffing, flag generation and detection, CRC generation and checking, abort generation and
checking.
DS3134
In the receive path, the following process occurs. The HDLC Engines collect the incoming data into
32-bit dwords and then signal the FIFO that the engine has data to transfer to the FIFO. The 16 ports are
priority decoded (Port 0 gets the highest priority) for the transfer of data from the HDLC Engines to the
FIFO Block. Please note that in a channelized application, a single port may contain up to 128 HDLC
channels and since HDLC channel numbers can be assigned randomly, the HDLC channel number has no
bearing on the priority of this data transfer. This situation is of no real concern however since the
DS3134 has been designed to handle up to 104 Mbps in both the receive and transmit directions without
any potential loss of data due to priority conflicts in the transfer of data from the HDLC Engines to the
FIFO and vice versa.
The FIFO transfers data from the HDLC Engines into the FIFO and checks to see if the FIFO has filled to
beyond the programmable High Water Mark. If it has, then the FIFO signals to the DMA that data is
ready to be burst read from the FIFO to the PCI Bus. The FIFO Block controls the DMA Block and it
tells the DMA when to transfer data from the FIFO to the PCI Bus. Since the DS3134 can handle
multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need to
have data transferred from the FIFO to the PCI Bus. The FIFO determines which HDLC channel the
DMA will handle next via a Host configurable algorithm, which allows the selection to be either round
robin or priority, decoded (with HDLC Channel 1 getting the highest priority). Depending on the
application, the selection of this algorithm can be quite important. The DS3134 cannot control when it
will be granted PCI Bus access and if bus access is restricted, then the Host may wish to prioritize which
HDLC channels get top priority access to the PCI Bus when it is granted to the DS3134.
When the DMA transfers data from the FIFO to the PCI Bus, it burst reads all available data in the FIFO
(even if the FIFO contains multiple HDLC packets) and tries to empty the FIFO. If an incoming HDLC
packet is not large enough to fill the FIFO to the High Water Mark, then the FIFO will not wait for more
data to enter the FIFO, it will signal the DMA that a End Of Frame (EOF) was detected and that data is
ready to be transferred from the FIFO to the PCI Bus by the DMA.
In the transmit path, a very similar process occurs. As soon as a HDLC channel is enabled, the HDLC
(Layer 2) Engines begin requesting data from the FIFO. Like the receive side, the 16 ports are priority
decoded with Port 0 getting the highest priority. Hence, if multiple ports are requesting packet data, the
FIFO will first satisfy the requirements on all the enabled HDLC channels in the lower numbered ports
before moving on to the higher numbered ports. Again there is no potential loss of data as long as the
transmit throughput maximum of 104 Mbps is not exceeded. When the FIFO detects that a HDLC Engine
needs data, it then transfers the data from the FIFO to the HDLC Engines in 8-bit chunks. If the FIFO
detects that the FIFO is below the Low Water Mark, it then checks with the DMA to see if there is any
data available for that HDLC Channel. The DMA will know if any data is available because the Host on
the PCI Bus will have informed it of such via the Pending Queue Descriptor. When the DMA detects that
data is available, it informs the FIFO and then the FIFO decides which HDLC channel gets the highest
priority to the DMA to transfer data from the PCI Bus into the FIFO. Again, since the DS3134 can handle
multiple HDLC channels, it is quite possible that at any one time, several HDLC channels will need the
DMA to burst data from the PCI Bus into the FIFO. The FIFO determines which HDLC channel the
DMA will handle next via a Host configurable algorithm, which allows the selection to be either round
robin or priority, decoded (with HDLC Channel 1 getting the highest priority).
DS3134
When the DMA begins burst writing data into the FIFO, it will try to completely fill the FIFO with HDLC
packet data even if it that means writing multiple packets. Once the FIFO detects that the DMA has filled
it to beyond the Low Water Mark (or an EOF is reached), the FIFO will begin transferring 32-bit dwords
to the HDLC Engine.
One of the unique attributes of the DS3134 is the structure of the DMA. The DMA has been optimized to
maintain maximum flexibility yet reduce the number of bus cycles required to transfer packet data. The
DMA uses a flexible scatter/gather technique, which allows that packet data to be place anywhere within
the 32-bit address space. The user has the option on the receive side of two different buffer sizes which
are called “large” and “small” but that can be set to any size up to 8191 bytes. The user has the option to
store the incoming data either, only in the large buffers, only in the small buffers, or fill a small buffer
first and then fill large buffers as needed. The varying buffer storage options allow the user to make the
best use of the available memory and to be able to balance the tradeoff between latency and bus
utilization.
The DMA uses a set of descriptors to know where to store the incoming HDLC packet data and where to
obtain HDLC packet data that is ready to be transmitted. The descriptors are fixed size messages that are
handed back and forth from the DMA to the Host. Since this descriptor transfer utilizes bus cycles, the
DMA has been structured to minimize the number of transfers required. For example on the receive side,
the DMA obtains descriptors from the Host to know where in the 32-bit address space to place the
incoming packet data. These descriptors are known as Free Queue Descriptors. When the DMA reads
these descriptors off of the PCI Bus, they contain all the information that the DMA needs to know where
to store the incoming data. Unlike other existing scatter/gather DMA architectures, the DS3134 DMA
does not need to use any more bus cycles to determine where to place the data. Other DMA architectures
tend to use pointers, which require them to go back onto the bus to obtain more information and hence
use more bus cycles.
Another technique that the DMA uses to maximize bus utilization is the ability to burst read and writes
the descriptors. The device can be enabled to read and write the descriptors in bursts of 8 or 16 instead of
one at a time. Since there is fixed overhead associated with each bus transaction, the ability to burst read
and write descriptors allows the device to share the bus overhead among 8 or 16 descriptor transactions
which reduces the total number of bus cycles needed.
The DMA can also burst up to 256 dwords (1024 bytes) onto the PCI Bus. This helps to minimize bus
cycles by allowing the device to burst large amounts of data in a smaller number of bus transactions
which reduces bus cycles by reducing the amount of fixed overhead that is placed on the bus.
The Local Bus Block has two modes of operation. It can be used as either a Bridge from the PCI Bus in
which case it is a bus master or it can be used as a Configuration Bus in which case it is a bus slave. The
Bridge Mode allows the Host on the PCI Bus to access the local bus. The DS3134 will map data from the
PCI Bus to the local bus. In the Configuration Mode, the local bus is used only to control and monitor the
DS3134 while the HDLC packet data will still be transferred to the Host via the PCI Bus.
Restrictions
In creating the overall system architecture, the user must balance the port, throughput, and HDLC channel
restrictions of the DS3134. Table 1D lists all of the upper bound maximum restrictions on the DS3134.
DS3134
DS3134 RESTRICTIONS FOR REV B1/B2 SILICON Table 1D
Portmaximum of 16 channelized and unchannelized physical ports
Unchannelizedports 0 & 1: maximum data rate of 52 Mbps
port 2 to 15: maximum data rate of 10 Mbps
ChannelizedChannelized and with frame interleave interfaces or a minimum of
two/multiple of two consecutive DS0 time slot assigned to one
HDLC channel:
40 T1/E1 channels
ChannelizedChannelized and with byte interleave interfaces:
32 T1/E1 channels
Throughputmaximum receive: 104 Mbps
maximum transmit: 104 Mbps
HDLCmaximum of 256 channels
if the Fast HDLC Engine on Port 0 is being used, then it must be
HDLC Channel 1*
if the Fast HDLC Engine on Port 1 is being used, then it must be
HDLC Channel 2*
* The 256 HDLC channels within the device are numbered from 1 to 256.
INTERNAL DEVICE CONFIGURATION REGISTERS
All of the internal device configuration registers (with the exception of the PCI Configuration Registers
which are 32-bit registers) are 16 bits wide and they are not byte addressable. When the Host on the PCI
Bus accesses these registers, the particular combination of byte enables (i.e. PCBE* signals) is not
important but at least one of the byte enables must be asserted for a transaction to occur. All the registers
are read/write registers unless otherwise noted. Not assigned bits (identified as n/a in the data sheet)
should be set to zero when written to allow for future upgrades to the device. These bits have no meaning
and could be either zero or one when read.
DS3134
INITIALIZATION
On a system reset (which can be invoked by either hardware action via the PRST* signal or software
action via the RST control bit in the Master Reset and ID register), all of the internal device configuration
register are set to zero (0000h). Please note that the Local Bus Bridge Mode Control register (LBBMC) is
not affected by software invoked system reset, it will be forced to all zeros only by hardware reset. The
internal registers within that are accessed indirectly (these are listed as "indirect registers" in the data
sheet and consist of the Channelized Port registers in the Layer One Block, the DMA Configuration
RAMs, the HDLC Configuration registers, and the FIFO registers) are not affected by a system reset and
they must be configured on power-up by the Host to a proper state. Figure 1B lists the ordered steps to
initialize the DS3134.
Note:
After device power up and reset, it takes 0.625 mS to get a port up and operating. In other words, the
ports must have wait a minimum of 0.625 mS before packet data can be processed.
INITIALIZATION STEPS Figure 1B
Initialization StepComments
1. Initialize the PCI Configuration
Registers
Achieved by asserting the PIDSEL signal.
2. Initialize All Indirect RegistersIt is recommended that all of the indirect
registers be set to 0000h. See Table 1E.
3. Configure the Device for OperationProgram all the necessary registers, which
includes the Layer One, HDLC, FIFO, and
DMA registers.
4. Enable the HDLC ChannelsDone via the RCHEN and TCHEN bits in
the R[n]CFG[j] and T[n]CFG[j] registers.
5. Load the DMA DescriptorsIndicate to the DMA where packet data can
be written and where pending data (if any)
resides
6. Enable the DMAsDone via the RDE and TDE control bits in
the Master Configuration (MC) register.
7. Enable DMA for each HDLC ChannelDone via the Channel Enable bit in the
Receive & Transmit Configuration RAM
DS3134
INDIRECT REGISTERS Table 1E
Register Name (Acronym)Number of Indirect Registers
Channelized Port registers (CP0RD to CP15RD)6144 (16 Ports x 128 DS0 Channels x 3
Registers for each DS0 Channel)
Receive HDLC Channel Definition register (RHCD)256 (one for each HDLC Channel)
Transmit HDLC Channel Definition register (THCD)256 (one for each HDLC Channel)
Receive DMA Configuration register (RDMAC)1536 (one for each HDLC Channel)
Transmit DMA Configuration register (TDMAC)3072 (one for each HDLC Channel)
Receive FIFO Staring Block Pointer register (RFSBP)256 (one for each HDLC Channel)
Receive FIFO Block Pointer register (RFBP)1024 (one for each FIFO Block)
Receive FIFO High Water Mark register (RFHWM)256 (one for each HDLC Channel)
Transmit FIFO Staring Block Pointer register (TFSBP)256 (one for each HDLC Channel)
Transmit FIFO Block Pointer register (TFBP)1024 (one for each FIFO Block)
Transmit FIFO Low Water Mark register (TFLWM)256 (one for each HDLC Channel)
DS3134
SECTION 2: SIGNAL DESCRIPTION
2.1 OVERVIEW / SIGNAL LEAD LIST
This section describes the input and output signals on the DS3134. Signal names follow a convention that
is shown in Table 2.1A. Table 2.1B lists all of the signals, their signal type, description, and lead
location.
Signal Naming Convention Table 2.1A
Signal Description / Lead List (sorted by symbol) Table 2.1B
DS3134
DS3134
DS3134
DS3134
DS3134
DS3134
2.2 SERIAL PORT INTERFACE SIGNAL DESCRIPTION
Signal Name:RC0 / RC1 / RC2 / RC3 / RC4 / RC5 / RC6 / RC7 / RC8 / RC9 / RC10 / RC11 /
RC12 / RC13 / RC14 / RC15
Signal Description:Receive Serial Clock
Signal Type:Input
Data can be clocked into the device either on falling edges (normal clock mode) or rising edges (inverted
clock mode) of RC. This is programmable on a per port basis. RC0 & RC1 can operate at speeds up to
52 MHz. RC2 to RC15 can operate at speeds up to 10 MHz. If not used, should be tied low.
Signal Name:RD0 / RD1 / RD2 / RD3 / RD4 / RD5 / RD6 / RD7 / RD8 / RD9 / RD10 / RD11 /
RD12 / RD13 / RD14 / RD15
Signal Description:Receive Serial Data
Signal Type:Input
Can be sampled either on the falling edge of RC (normal clock mode) or the rising edge of RC (inverted
clock mode). If not used, should be tied low.
Signal Name:RS0 / RS1 / RS2 / RS3 / RS4 / RS5 / RS6 / RS7 / RS8 / RS9 / RS10 / RS11 /
RS12 / RS13 / RS14 / RS15
Signal Description:Receive Serial Data Synchronization Pulse
Signal Type:Input
A one RC clock wide synchronization pulse that can be applied to the Chateau to force byte/frame
alignment. The applied sync signal pulse can be either active high (normal sync mode) or active low
(inverted sync mode). The RS signal can be sampled either on the falling edge or on rising edge of RC
(see Table 2.2A below for details). The applied sync pulse can be during the first RC clock period of a
193/256/512/1024 bit frame or it can be applied 1/2, 1, or 2 RC clocks early. This input sync signal resets
a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096 MHz mode)
or 1024 (8.192 MHz mode) RC clocks. It is acceptable to only pulse the RS signal once to establish byte
boundaries and allow Chateau to keep track of the byte/frame boundaries by counting RC clocks. If the
incoming data does not require alignment to byte/frame boundaries, then this signal should be tied low.
DS3134
RS SAMPLED EDGE Table 2.2A
Signal Name:TC0 / TC1 / TC2 / TC3 / TC4 / TC5 / TC6 / TC7 / TC8 / TC9 / TC10 / TC11 /
TC12 / TC13 / TC14 / TC15
Signal Description:Transmit Serial Clock
Signal Type:Input
Data can be clocked out of the device either on rising edges (normal clock mode) or falling edges
(inverted clock mode) of TC. This is programmable on a per port basis. TC0 & TC1 can operate at
speeds up to 52 MHz. TC2 to TC15 can operate at speeds up to 10 MHz. If not used, should be tied low.
Signal Name:TD0 / TD1 / TD2 / TD3 / TD4 / TD5 / TD6 / TD7 / TD8 / TD9 / TD10 / TD11 /
TD12 / TD13 / TD14 / TD15
Signal Description:Transmit Serial Data
Signal Type:Output
Can be updated either on the rising edge of TC (normal clock mode) or the falling edge of TC (inverted
clock mode). Data can be forced high.
Signal Name:TS0 / TS1 / TS2 / TS3 / TS4 / TS5 / TS6 / TS7 / TS8 / TS9 / TS10 / TS11 /
TS12 / TS13 / TS14 / TS15
Signal Description:Transmit Serial Data Synchronization Pulse
Signal Type:Inputone TC clock wide synchronization pulse that can be applied to the Chateau to force byte/frame
alignment. The applied sync signal pulse can be either active high (normal sync mode) or active low
(inverted sync mode). The TS signal can be sampled either on the falling edge or on rising edge of TC
(see Table 2.2B below for details). The applied sync pulse can be during the first TC clock period of a
193/256/512/1024 bit frame or it can be applied 1/2, 1, or 2 TC clocks early. This input sync signal resets
a counter that rolls over at a count of either 193 (T1 mode) or 256 (E1 mode) or 512 (4.096 MHz mode)
or 1024 (8.192 MHz mode) TC clocks. It is acceptable to only pulse the TS signal once to establish byte
boundaries and allow Chateau to keep track of the byte/frame boundaries by counting TC clocks. If the
incoming data does not require alignment to byte/frame boundaries, then this signal should be tied low.
TS SAMPLED EDGE Table 2.2B
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2.3 LOCAL BUS SIGNAL DESCRIPTION
Signal Name:LMS
Signal Description:Local Bus Mode Select
Signal Type:Input
This signal should be tied low when the device is to be operated either with no Local Bus access or if the
Local Bus will be used to act as a bridge from the PCI bus. This signal should be tied high if the Local
Bus is to be used by an external host to configure the device.
0 = Local Bus is in the PCI Bridge Mode (master)
1 = Local Bus is in the Configuration Mode (slave)
Signal Name:LIM
Signal Description:Local Bus Intel/Motorola Bus Select
Signal Type:Input
The signal determines whether the Local Bus will operate in the Intel Mode (LIM = 0) or the Motorola
Mode (LIM = 1). The signal names in parenthesis are operational when the device is in the Motorola
Mode.
0 = Local Bus is in the Intel Mode
1 = Local Bus is in the Motorola Mode
Signal Name:LD0 to LD15
Signal Description:Local Bus Non-Multiplexed Data Bus
Signal Type:Input / Output (tri-state capable)
In PCI Bridge Mode (LMS = 0), data from/to the PCI bus can be transferred to/from these signals. When
writing data to the Local Bus, these signals will be outputs and updated on the rising edge of LCLK.
When reading data from the Local Bus, these signals will be inputs, which will be sampled on the rising
edge of LCLK. Depending on the assertion of the PCI Byte Enables (PCBE0 to PCBE3) and the Local
Bus Width (LBW) control bit in the Local Bus Bridge Mode Control Register (LBBMC), this data bus
will utilize all 16-bits (LD[15:0]) or just the lower 8-bits (LD[7:0]) or the upper 8-bits (LD[15:8]). If the
upper LD bits (LD[15:8]) are used, then the Local Bus High Enable signal (LBHE*) will be asserted
during the bus transaction. If the Local Bus is not currently involved in a bus transaction, then all 16
signals will be tri-stated. In the Configuration Mode (LMS = 1), the external host will configure the
device and obtain real time status information about the device via these signals. When reading data from
the Local Bus, these signals will be outputs that are updated on the rising edge of LCLK. When writing
data to the Local Bus, these signals will become inputs which will be sampled on the rising edge of
LCLK. In the Configuration Mode, only the 16-bit bus width is allowed (i.e. byte addressing is not
available).
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Signal Name:LA0 to LA19
Signal Description:Local Bus Non-Multiplexed Address Bus
Signal Type:Input / Output (tri-state capable)
In the PCI Bridge Mode (LMS = 0), these signals are outputs that will be asserted on the rising edge of
LCLK to indicate which address to be written to or read from. These signals will be tri-stated when the
Local Bus is not currently involved in a bus transaction and driven when a bus transaction is active. In the
Configuration Mode (LMS = 1), these signals are inputs and only the bottom 16 (LA[15:0]) are active, the
upper four (LA[19:16]) are ignored and should be tied low. These signals will be sampled on the rising
edge of LCLK to determine the internal device configuration register that the external host wishes to
access.
Signal Name:LWR* (LR/W*)
Signal Description:Local Bus Write Enable (Local Bus Read/Write Select)
Signal Type:Input / Output (tri-state capable)
In the PCI Bridge Mode (LMS = 0), this output signal is asserted on the rising edge of LCLK. In Intel
Mode (LIM = 0) it will be asserted when data is to be written to the Local Bus. In Motorola Mode (LIM
= 1), this signal will determine whether a read or write is to occur. If bus arbitration is enabled via the
Local Bus Arbitration (LARBE) control bit in the Local Bus Bridge Mode Control Register (LBBMC),
then this signal will be tri-stated when the Local Bus is not currently involved in a bus transaction and
driven when a bus transaction is active. When bus arbitration is disabled, this signal is always driven. In
the Configuration Mode (LMS = 1), this signal is sampled on the rising edge of LCLK. In Intel Mode
(LIM = 0) it will determine when data is to be written to the device. In Motorola Mode (LIM = 1), this
signal will be used to determine whether a read or write is to occur.
Signal Name:LRD* (LDS*)
Signal Description:Local Bus Read Enable (Local Bus Data Strobe)
Signal Type:Input / Output (tri-state capable)
In the PCI Bridge Mode (LMS = 0), this active low output signal is asserted on the rising edge of LCLK.
In Intel Mode (LIM = 0) it will be asserted when data is to be read from the Local Bus. In Motorola Mode
(LIM = 1), the rising edge will be used to write data into the slave device. If bus arbitration is enabled via
the Local Bus Arbitration (LARBE) control bit in the Local Bus Bridge Mode Control Register
(LBBMC), then this signal will be tri-stated when the Local Bus is not currently involved in a bus
transaction and driven when a bus transaction is active. When bus arbitration is disabled, this signal is
always driven. In the Configuration Mode (LMS = 1), this signal is an active low input which is sampled
on the rising edge of LCLK. In Intel Mode (LIM = 0) it will determine when data is to be read from the
device. In Motorola Mode (LIM = 1), the rising edge will be used to write data into the device.
Signal Name:LINT*
Signal Description:Local Bus Interrupt
Signal Type:Input / Output (open drain)
In the PCI Bridge Mode (LMS = 0), this active low signal is an input which sampled on the rising edge of
LCLK. If asserted and unmasked, this signal will cause an interrupt at the PCI bus via the PINTA*
signal. If not used in the PCI Bridge Mode, this signal should be tied high. In the Configuration Mode
(LMS = 1) this signal is an open drain output which will be forced low if one or more unmasked interrupt
sources within the device is active. The signal will remain low until the interrupt is either serviced or
masked.
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Signal Name:LRDY*
Signal Description:Local Bus PCI Bridge Ready [PCI Bridge Mode Only]
Signal Type:Input
This active low signal is sampled on the rising edge of LCLK to determine when a bus transaction is
complete. This signal is only examined when a bus transaction is taking place. This signal is ignored
when the Local Bus is in the Configuration Mode (LMS = 1) and should be tied high.
Signal Name:LHLDA (LBG*)
Signal Description:Local Bus Hold Acknowledge (Local Bus Grant) [PCI Bridge Mode Only]
Signal Type:Input
This input signal is sampled on the rising edge of LCLK to determine when the device has been granted
access to the bus. In Intel Mode (LIM = 0) this is an active high signal and in Motorola Mode (LIM = 1)
this is an active low signal. This signal is ignored and should be tied high when the Local Bus is in the
Configuration Mode (LMS = 1). Also, in the PCI Bridge Mode (LMS = 0), this signal should be tied
deasserted when the Local Bus Arbitration is disabled via the Local Bus Bridge Mode Control Register.
Signal Name:LHOLD (LBR*)
Signal Description:Local Bus Hold (Local Bus Request) [PCI Bridge Mode Only]
Signal Type:Output
This active low signal will be asserted when the Local Bus is attempting to take control of the bus. It will
be deasserted in the Intel Mode (LIM = 0) when the bus access is complete. It will be deasserted in the
Motorola Mode (LIM = 1) when the Local Bus Hold Acknowledge/Grant signal (LHLDA/LBG*) has
been detected. This signal is tri-stated when the Local Bus is in the Configuration Mode (LMS = 1) and
in the PCI Bridge Mode (LMS = 0) when the Local Bus Arbitration is disabled via the Local Bus Bridge
Mode Control Register.
Signal Name:LBGACK*
Signal Description:Local Bus Grant Acknowledge [PCI Bridge Mode Only]
Signal Type:Output (tri-state capable)
This active low signal is asserted when the Local Bus Hold Acknowledge/Bus Grant signal
(LHLDA/LBG*) has been detected and it continues it's assertion for a programmable (32 to 1048576)
number of LCLKs based upon the Local Bus Arbitration Timer setting in the Local Bus Bridge Mode
Control Register (LBBMC) register. This signal is tri-stated when the Local Bus is in the Configuration
Mode (LMS = 1).
Signal Name:LBHE*
Signal Description:Local Bus Byte High Enable [PCI Bridge Mode Only]
Signal Type:Output (tri-state capable)
This active low output signal is asserted when all 16-bits of the data bus (LD[15:0]) are active. It will
remain high if only the lower 8-bits (LD[7:0)] is active. If bus arbitration is enabled via the Local Bus
Arbitration (LARBE) control bit in the Local Bus Bridge Mode Control Register (LBBMC), then this
signal will be tri-stated when the Local Bus is not currently involved in a bus transaction and driven when
a bus transaction is active. When bus arbitration is disabled, this signal is always driven. This signal will
remain in tri-state when the Local Bus is not currently involved in a bus transaction and when the Local
Bus is in the Configuration Mode (LMS = 1).
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Signal Name:LCLK
Signal Description:Local Bus Clock [PCI Bridge Mode Only]
Signal Type:Output (tri-state capable)
This signal outputs a buffered version of the clock applied at the PCLK input. All Local Bus signals are
generated and sampled from this clock. This output is tri-stated when the Local Bus is in the
Configuration Mode (LMS = 1). It can be disabled in the PCI Bridge Mode via the Local Bus Bridge
Mode Control Register (LBBMC).
Signal Name:LCS*
Signal Description:Local Bus Chip Select [Configuration Mode Only]
Signal Type:Input
This active low signal must be asserted for the device to accept a read or write command from an external
host. This signal is ignored in the PCI Bridge Mode (LMS = 0) and should be tied high.
2.4 JTAG SIGNAL DESCRIPTION
Signal Name:JTCLK
Signal Description:JTAG IEEE 1149.1 Test Serial Clock
Signal Type:Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not
used, this signal should be pulled high.
Signal Name:JTDI
Signal Description:JTAG IEEE 1149.1 Test Serial Data Input
Signal Type:Input (with internal 10k pull up)
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this signal
should be pulled high. This signal has an internal pull-up.
Signal Name:JTDO
Signal Description:JTAG IEEE 1149.1 Test Serial Data Output
Signal Type:Output
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this signal
should be left open circuited.
Signal Name:JTRST*
Signal Description:JTAG IEEE 1149.1 Test Reset
Signal Type:Input (with internal 10k pull up)
This signal is used to asynchronously reset the test access port controller. At power up, JTRST must be
set low and then high. This action will set the device into the boundary scan bypass mode allowing
normal device operation. If boundary scan is not used, this signal should be held low. This signal has an
internal pull-up.
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Signal Name:JTMS
Signal Description:JTAG IEEE 1149.1 Test Mode Select
Signal Type:Input (with internal 10k pull up)
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various
defined IEEE 1149.1 states. If not used, this signal should be pulled high. This signal has an internal pull-
up.
2.5 PCI BUS SIGNAL DESCRIPTION
Signal Name:PCLK
Signal Description:PCI & System Clock
Signal Type:Input (Schmitt triggered)
This clock input is used to provide timing for the PCI bus and to the internal logic of the device. A 25
MHz to 33 MHz clock with a nominal 50% duty cycle should be applied here.
Signal Name:PRST*
Signal Description:PCI Reset
Signal Type:Input
This active low input is used to force an asynchronous reset to both the PCI bus and the internal logic of
the device. When forced low, this input forced all the internal logic of the device into its default state and
it forces the PCI outputs into tri-state and the TD[15:0] output port data signals high.
Signal Name:PAD0 to PAD31
Signal Description:PCI Address & Data Multiplexed Bus
Signal Type:Input / Output (tri-state capable)
Both Address and Data information are multiplexed onto these signals. Each bus transaction consists of
an address phase followed by one or more data phases. Data can be either read or written in bursts.
During the first clock cycle of a bus transaction, the address is transferred. When the Little-Endian format
is selected, PAD[31:24] is the msb of the DWORD, when Big-Endian is selected, PAD[7:0] contain the
msb. When the device is an initiator, these signals are always outputs during the address phase. They
remain outputs for the data phase(s) in a write transaction and become inputs for a read transaction.
When the device is a target, these signals are always inputs during the address phase. They remain inputs
for the data phase(s) in a read transaction and become outputs for a write transaction. When the device is
not involved in a bus transaction, these signals remain tri-stated. These signals are always updated and
sampled on the rising edge of PCLK.
Signal Name:PCBE0* / PCBE1* / PCBE2* / PCBE3*
Signal Description:PCI Bus Command and Byte Enable
Signal Type:Input / Output (tri-state capable)
Bus Command and Byte Enables are multiplexed onto the same PCI signals. During an address phase,
these signals define the Bus Command. During the data phase, these signals as used as Bus Enables.
During data phases, PCBE0 refers to the PAD[7:0] and PCBE3 refers to PAD[31:24]. When this signal is
high, the associated byte is invalid, when low; the associated byte is valid. When the device is an
initiator, this signal is an output and is updated on the rising edge of PCLK. When the device is a target,
this signal is input and is sampled on the rising edge of PCLK. When the device is not involved in a bus
transaction, these signals are tri-stated.
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Signal Description:PCI Bus Parity
Signal Type:Input / Output (tri-state capable)
This signal provides information on even parity across both the PAD address/data bus and the PCBE bus
command/byte enable bus. When the device is an initiator, this signal is an output for writes and input for
reads and is updated on the rising edge of PCLK. When the device is a target, this signal is input for
writes and an output for reads and is sampled on the rising edge of PCLK. When the device is not
involved in a bus transaction, PPAR is tri-stated.
Signal Name:PFRAME*
Signal Description:PCI Cycle Frame
Signal Type:Input / Output (tri-state capable)
This active low signal is created by the bus initiator and is used to indicate the beginning and duration of a
bus transaction. PFRAME* is asserted by the initiator during the first clock cycle of a bus transaction and
it will remain asserted until the last data phase of a bus transaction. When the device is an initiator, this
signal is an output and is updated on the rising edge of PCLK. When the device is a target, this signal is
input and is sampled on the rising edge of PCLK. When the device is not involved in a bus transaction,
PFRAME* is tri-stated.
Signal Name:PIRDY*
Signal Description:PCI Initiator Ready
Signal Type:Input / Output (tri-state capable)
This active low signal is created by the initiator to signal the target that it is ready to send/accept or to
continue sending/accepting data. This signal handshakes with the PTRDY* signal during a bus
transaction to control the rate at which data transfers across the bus. During a bus transaction, PIRDY* is
deasserted when the initiator cannot temporarily accept or send data and a wait state is invoked. When the
device is an initiator, this signal is an output and is updated on the rising edge of PCLK. When the device
is a target, this signal is input and is sampled on the rising edge of PCLK. When the device is not
involved in a bus transaction, PIRDY* is tri-stated.
Signal Name:PTRDY*
Signal Description:PCI Target Ready
Signal Type:Input / Output (tri-state capable)
This active low signal is created by the target to signal the initiator that it is ready to send/accept or to
continue sending/accepting data. This signal handshakes with the PIRDY* signal during a bus transaction
to control the rate at which data transfers across the bus. During a bus transaction, PTRDY* is deasserted
when the target cannot temporarily accept or send data and a wait state is invoked. When the device is a
target, this signal is an output and is updated on the rising edge of PCLK. When the device is an initiator,
this signal is input and is sampled on the rising edge of PCLK. When the device is not involved in a bus
transaction, PTRDY* is tri-stated.
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Signal Name:PSTOP*
Signal Description:PCI Stop
Signal Type:Input / Output (tri-state capable)
This active low signal is created by the target to signal to the initiator that it requests the initiator stop the
current bus transaction. When the device is a target, this signal is an output and is updated on the rising
edge of PCLK. When the device is an initiator, this signal is input and is sampled on the rising edge of
PCLK. When the device is not involved in a bus transaction, PSTOP* is tri-stated.
Signal Name:PIDSEL
Signal Description:PCI Initialization Device Select
Signal Type:Input
This input signal is used as a chip select during configuration read and writes transactions. This signal is
disabled when the Local Bus is set in the Configuration Mode (LMS = 1). When PIDSEL is set high
during the address phase of a bus transaction and the Bus Command signals (PCBE0 to PCBE3) indicateregister read or write, then the device allows access to the PCI configuration registers and the
PDEVSEL* signal is asserted during the PCLK cycle. PIDSEL is sampled on the rising edge of PCLK.
Signal Name:PDEVSEL*
Signal Description:PCI Device Select
Signal Type:Input / Output (tri-state capable)
This active low signal is created by the target when it has decoded the address sent to it by the initiator, as
it's own to indicate that that the address is valid. If the device is an initiator and does not see the signal
asserted within six PCLK cycles, then the bus transaction is aborted and the PCI Host is alerted. When the
device is a target, this signal is an output and is updated on the rising edge of PCLK. When the device is
an initiator, this signal is input and is sampled on the rising edge of PCLK. When the device is not
involved in a bus transaction, PDEVSEL* is tri-stated.
Signal Name:PREQ*
Signal Description:PCI Bus Request
Signal Type:Output (tri-state capable)
This active low signal is asserted by the initiator to request that the PCI bus arbiter allow it access to the
bus. PREQ* is updated on the rising edge of PCLK.
Signal Name:PGNT*
Signal Description:PCI Bus Grant
Signal Type:Input
This active low signal is asserted by the PCI bus arbiter to indicate to the PCI requesting agent that access
to the PCI bus has been granted. The device samples PGNT* on the rising edge of PCLK and if detected,
will initiate a bus transaction when it has sensed that the PFRAME* signal has been deasserted.
Signal Name:PPERR*
Signal Description:PCI Parity Error
Signal Type:Input / Output (tri-state capable)
This active low signal reports parity errors that occur. PPERR* can be enabled and disabled via the PCI
Configuration Registers. This signal is updated on the rising edge of PCLK.
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Signal Name:PSERR*
Signal Description:PCI System Error
Signal Type:Output (open drain)
This active low signal reports any parity errors that occur during the address phase. PSERR* can be
enabled and disabled via the PCI Configuration Registers. This signal is updated on the rising edge of
PCLK.
Signal Name:PINTA*
Signal Description:PCI Interrupt
Signal Type:Output (open drain)
This active low (open drain) signal is asserted low asynchronously when the device is requesting attention
from the device driver. PINTA will be deasserted when the device interrupting source has been service or
masked. This signal is updated on the rising edge of PCLK.
PCI Extension Signals
These signals are not part of the normal PCI Bus signal set. There are additional signals that are asserted
when Chateau is an Initiator on the PCI Bus to help users interpret the normal PCI Bus signal set and
connect them to a non-PCI environment like an Intel i960 type bus. The timing for these signals is shown
below.
Signal Name:PXAS*
Signal Description:PCI Extension Address Strobe
Signal Type:Output
This active low signal is asserted low on the same clock edge as PFRAME* and is deasserted after one
clock period. This signal will only be asserted when the device is an initiator. This signal is an output
and is updated on the rising edge of PCLK.
Signal Name:PXDS*
Signal Description:PCI Extension Data Strobe
Signal Type:Output
This active low signal is asserted when the PCI bus either contains valid data to be read from the device
or can accept valid data that is written into the device. This signal will only be asserted when the device
is an initiator. This signal is an output and is updated on the rising edge of PCLK.
Signal Name:PXBLAST*
Signal Description:PCI Extension Burst Last
Signal Type:Output
This active low signal is asserted on the same clock edge as PFRAME* is deasserted and is deasserted on
the same clock edge as PIRDY* is deasserted. This signal will only be asserted when the device is an
initiator. This signal is an output and is updated on the rising edge of PCLK.
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2.6 SUPPLY & TEST SIGNAL DESCRIPTION
Signal Name:TEST
Signal Description:Factory Test Input
Signal Type:Input (with internal 10k pull up).
This input should be left open circuited by the user.
Signal Name:VDD
Signal Description:Positive Supply
Signal Type:n/a
3.3V (+/- 10%). All VDD signals should be tied together.
Signal Name:VSS
Signal Description:Ground Reference
Signal Type:n/a
All VSS signals should be tied to the local ground plane.
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SECTION 3: MEMORY MAP
3.0 INTRODUCTION
All addresses within the memory map on dword boundaries even though all of the internal device
configuration registers are only one word (16 bits) wide. The memory map consumes an address range of
4 kB (12 bits). When the PCI Bus is the Host (i.e. the Local Bus is in the Bridge Mode), the actual 32-bit
PCI Bus addresses of the internal device configuration registers is obtained by adding the DC Base
Address value in the PCI Device Configuration Memory Base Address Register (see Section 9.2 for
details) to the offset listed in Sections 3.1 to 3.11. When an external host is configuring the device via the
Local Bus (i.e. the Local Bus is in the Configuration Mode), the offset is 0h and the Host on the Local
Bus will use the 16-bit addresses listed in Sections 3.1 to 3.11.
MEMORY MAP ORGANIZATION Table 3.0A
3.1 GENERAL CONFIGURATION REGISTERS (0XX)
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3.2 RECEIVE PORT REGISTERS (1XX)
3.3 TRANSMIT PORT REGISTERS (2XX)
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3.4 CHANNELIZED PORT REGISTERS (3XX)
3.5 HDLC REGISTERS (4XX)
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3.6 BERT REGISTERS (5XX)
3.7 RECEIVE DMA REGISTERS (7XX)
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3.8 TRANSMIT DMA REGISTERS (8XX)
3.9 FIFO REGISTERS (9XX)
3.10 PCI CONFIGURATION REGISTERS FOR FUNCTION 0 (PIDSEL/AXX)
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3.11 PCI CONFIGURATION REGISTERS FOR FUNCTION 1 (PIDSEL/BXX)
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SECTION 4: GENERAL DEVICE CONFIGURATION & STATUS/INTERRUPT
4.1 MASTER RESET & ID REGISTER DESCRIPTION
The Master Reset & ID (MRID) register can be used to globally reset the device. When the RST bit is set
to one, all of the internal registers (except the PCI configuration registers) will be placed into their default
state, which is 0000h. The Host must set the RST bit back to zero before the device can be programmed
for normal operation. The RST bit does not force the PCI outputs to tri-state as does the hardware reset
which is invoked via the PRST* pin. A reset invoked by the PRST* pin will force the RST bit to zero as
well as the rest of the internal configuration registers. See Section 1 for more details on device
initialization.
The upper byte of the MRID register is read only and it can be read by the Host to determine the chip
revision. Contact the factory for specifics on the meaning of the value read from the ID0 to ID7 bits.
Register Name:MRID
Register Description:Master Reset and ID Register
Register Address:0000h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Master Software Reset (RST).
0 = normal operation
1 = force all internal registers (except LBBMC) to their default value of 0000h
Bits 8 to 15 / Chip Revision ID Bit 0 to 7 (ID0 to ID7). Read only. Contact the factory for details on
the meaning of the ID bits.
4.2 MASTER CONFIGURATION REGISTER DESCRIPTION
The Master Configuration (MC) register is used by the Host to enable the receive and transmit DMAs as
well as to control their PCI Bus bursting attributes and to select which port the BERT is to be dedicated
to.
Register Name:MC
Register Description:Master Configuration Register
Register Address:0010h543210141312111098
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Bit 0 / Receive DMA Enable (RDE). This bit is used to enable the receive DMA. When it is set to zero,
the receive DMA will not pass any data from the receive FIFO to the PCI Bus even if there is one or more
HDLC channels enabled. On device initialization, the Host should fully configure the receive DMA
before enabling it via this bit.
0 = receive DMA is disabled
1 = receive DMA is enabled
Bit 1 / Receive DMA Throttle Select Bit 0 (RDT0).
Bit 2 / Receive DMA Throttle Select Bit 1 (RDT1).
These two bits select the maximum burst length that the receive DMA is allowed on the PCI Bus. The
DMA can be restricted to a maximum burst length of just 32 dwords (128 bytes) or it can be
incrementally adjusted up to 256 dwords (1024 bytes). The Host will select the optimal length based on a
number of factors including the system environment for the PCI Bus, the number of HDLC channels
being used, and the trade off between channel latency and bus efficiency.
00 = burst length maximum is 32 dwords
01 = burst length maximum is 64 dwords
10 = burst length maximum is 128 dwords
11 = burst length maximum is 256 dwords
Bit 3 / Transmit DMA Enable (TDE). This bit is used to enable the transmit DMA. When it is set to
zero, the transmit DMA will not pass any data from the PCI Bus to the transmit FIFO even if there is one
or more HDLC channels enabled. On device initialization, the Host should fully configure the transmit
DMA before enabling it via this bit.
0 = transmit DMA is disabled
1 = transmit DMA is enabled
Bit 4 / Transmit DMA Throttle Select Bit 0 (TDT0).
Bit 5 / Transmit DMA Throttle Select Bit 1 (TDT1).These two bits select the maximum burst length that the transmit DMA is allowed on the PCI Bus. The
DMA can be restricted to a maximum burst length of just 32 dwords (128 bytes) or it can be
incrementally adjusted up to 256 dwords (1024 bytes). The Host will select the optimal length based on a
number of factors including the system environment for the PCI Bus, the number of HDLC channels
being used, and the trade off between channel latency and bus efficiency.
00 = burst length maximum is 32 dwords
01 = burst length maximum is 64 dwords
10 = burst length maximum is 128 dwords
11 = burst length maximum is 256 dwords
Bit 6 / PCI Bus Orientation (PBO).
This bit selects whether HDLC packet data on the PCI Bus will operate in either Little Endian format or
Big Endian format. Little Endian byte ordering places the least significant byte at the lowest address
while Big Endian places the least significant byte at the highest address. This bit setting only affects
HDLC data on the PCI Bus. All other PCI Bus transactions to the internal device configuration registers,
PCI configuration registers, and Local Bus, are always in Little Endian format.
0 = HDLC Packet Data on the PCI Bus is in Little Endian format
DS3134
Bits 7 to 11 / BERT Port Select Bits 0 to 4 (BPS0 to BPS4). These 5 bits select which port has the
dedicated resources of the BERT.
00000 = Port 001000 = Port 810000 = Port 0 (hi speed)11000 = n/a
00001 = Port 101001 = Port 910001 = Port 1 (hi speed)11001 = n/a
00010 = Port 201010 = Port 1010010 = n/a11010 = n/a
00011 = Port 301011 = Port 1110011 = n/a11011 = n/a
00100 = Port 401100 = Port 1210100 = n/a11100 = n/a
00101 = Port 501101 = Port 1310101 = n/a11101 = n/a
00110 = Port 601110 = Port 1410110 = n/a11110 = n/a
00111 = Port 701111 = Port 1510111 = n/a11111 = n/a
Bit 12 / Receive FIFO Priority Control Bit 0 (RFPC0).
Bit 13 / Receive FIFO Priority Control Bit 1 (RFPC1).
These 2 bits select the algorithm the FIFO will use to determine which HDLC Channel gets the highest
priority to the DMA to transfer data from the FIFO to the PCI Bus. In the priority decoded scheme, the
lower the HDLC channel numbers, the higher the priority.
00 = all HDLC channels are serviced Round Robin
01 = HDLC Channels 1 & 2 are Priority Decoded; other HDLC Channels are Round Robin
10 = HDLC Channels 1 to 16 are Priority Decoded; other HDLC Channels are Round Robin
11 = HDLC Channels 1 to 64 are Priority Decoded; other HDLC Channels are Round Robin
Bit 14 / Transmit FIFO Priority Control Bit 0 (TFPC0).
Bit 15 / Transmit FIFO Priority Control Bit 1 (TFPC1).
These 2 bits select the algorithm the FIFO will use to determine which HDLC Channel gets the highest
priority to the DMA to transfer data from the PCI Bus to the FIFO. In the priority decoded scheme, the
lower the HDLC channel numbers, the higher the priority.
00 = all HDLC channels are serviced Round Robin
01 = HDLC Channels 1 & 2 are Priority Decoded; other HDLC Channels are Round Robin
10 = HDLC Channels 1 to 16 are Priority Decoded; other HDLC Channels are Round Robin
11 = HDLC Channels 1 to 64 are Priority Decoded; other HDLC Channels are Round Robin
4.3 STATUS & INTERRUPT
4.3.1 Status & Interrupt General Description of Operation
There are three status register in the device, Status Master (SM), Status for the Receive V54 Loopback
Detector (SV54), and Status for DMA (SDMA). All three registers report events in real time as they
occur by setting a bit within the register to a one. All bits that have been set within the register are cleared
when the register is read and the bit will not be set again until the event has occurred again. Each bit has
the ability to generate an interrupt at the PCI Bus via the PINTA* output signal pin and if the Local Bus is
in the Configuration Mode, then an interrupt will also be created at the LINT* output signal pin. Each
status register has an associated Interrupt Mask Register, which can allow/deny interrupts from being
generated on a bit-by-bit basis. All status remains active even if the associated Interrupt is disabled.
DS3134
SM Register
The Status Master (SM) register reports events that occur at the Port Interface, at the BERT receiver, at
the PCI Bus and at the Local Bus. See Figure 4.3.1A for details.
The Port Interface reports Change Of Frame Alignment (COFA) events. If the software detects that one
of these bits as being set, the software must then begin polling the RP[n]CR or TP[n]CR registers of each
active port (a maximum of 16 reads) to determine which port or ports has incurred a COFA. Also via the
Interrupt Enable for Receive COFA (IERC) and Interrupt Enable for Transmit COFA (IETC) control bits
in the RP[n]CR and TP[n]CR registers respectively, the Host can allow/deny the COFA indications to be
passed on to the SRCOFA and STCOFA status bits.
The BERT receiver will report three events, a change in the receive synchronizer status, a bit error being
detected, and if either the Bit Counter or the Error Counter overflows. Each of these events can be
masked within the BERT function via the BERT Control Register (BERTC0). If the software detects that
the BERT has reported an event has occurred, then the software must read the BERT Status Register
(BERTEC0) to determine which event(s) has occurred.
The SM register also reports events as they occur in the PCI Bus and the Local Bus. There are no control
bits to stop these events from being reported in the SM register. When the Local Bus is operated in the
PCI Bridge Mode, SM reports any interrupts detected via the Local Bus LINT* input signal pin and if any
timing errors occur because of the use of the external timing signal LRDY*. When the Local Bus is
operated in the Configuration Mode, the LBINT and LBE bits are meaningless and should be ignored.
SV54 Register
The Status for Receive V.54 Detector (SV54) register reports if the V.54 loopback detector has either
timed out in its search for the V.54 loop up pattern or if the detector has found and verified the loop
up/down pattern. There is a separate status bit (SLBP) for each port. When set, the Host must read the
VTO and VLB status bits in the RP[n]CR register of the corresponding port to find the exact state of the
V.54 detector. When the V.54 detector experiences a time out in it's search for the loop up code (VTO =
1), then the SLBP status bit will be continuously set until the V.54 detector is reset by the Host toggling
the VRST bit in RP[n]CR register. There are no control bits to stop these events from being reported in
the SV54 register. See Figure 4.3.1A for details on the status bits and Section 5 for details on the
operation of the V.54 loopback detector.
SDMA Register
The Status for DMA (SDMA) register reports events that occur regarding the Receive and Transmit DMA
blocks as well as the receive HDLC controller and FIFO. The SDMA will report when the DMA reads
from either the Receive Free Queue or Transmit Pending Queue or writes to the Receive or Transmit
Done Queues. Also reported are error conditions that might occur in the access of one of these queues.
The SDMA will report if any of the HDLC channels experiences a FIFO overflow/underflow condition
and if the receive HDLC controller encounters a CRC error, abort signal, or octet length problem on any
of the HDLC channels. The Host can determine which specific HDLC channel incurred a FIFO
overflow/underflow, CRC error, octet length error or abort by reading the status bits as reported in Done
Queues which are created by the DMA. There are no control bits to stop these events from being reported
in the SDMA register.
DS3134
STATUS REGISTER BLOCK DIAGRAM FOR SM & SV54 Figure 4.3.1A
Transmit
SM: Status Master Register
SV54: Status for V54 Detector
DS3134
4.3.2 STATUS & INTERRUPT REGISTER DESCRIPTION
Register Name:SM
Register Description:Status Master Register
Register Address:0020h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Status Bit for Receive Change Of Frame Alignment (SRCOFA). This status bit will be set to a
one if one or more of the receive ports has experienced a Change Of Frame Alignment (COFA) event.
The host must read the RCOFA bit in the Receive Port Control Registers (RP[n]CR) of each active port to
determine which port or ports has seen the COFA. The SRCOFA bit will be cleared when read and will
not be set again, until one or more receive ports has experienced another COFA. If enabled via the
SRCOFA bit in the Interrupt Mask for SM (ISM), the setting of this bit will cause a hardware interrupt at
the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration
Mode.
Bit 1 / Status Bit for Transmit Change Of Frame Alignment (STCOFA). This status bit will be set to
a one if one or more of the transmit ports has experienced a Change Of Frame Alignment (COFA) event.
The host must read the TCOFA bit in the Transmit Port Control Registers (TP[n]CR) of each active port
to determine which port or ports has seen the COFA. The STCOFA bit will be cleared when read and
will not be set again, until one or more transmit ports has experienced another COFA. If enabled via the
STCOFA bit in the Interrupt Mask for SM (ISM), the setting of this bit will cause a hardware interrupt at
the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration
Mode.
Bit 2 / Status Bit for Change of State in BERT (SBERT). This status bit will be set to a one if there is
a major change of state in the BERT receiver. A major change of state is defined as either a change in the
receive synchronization (i.e. the BERT has gone into or out of receive synchronization), a bit error has
been detected, or an overflow has occurred in either the Bit Counter or the Error Counter. The Host must
read the status bits of the BERT in the BERT Status Register (BERTEC0) to determine the change of
state. The SBERT bit will be cleared when read and will not be set again until the BERT has experienced
another change of state. If enabled via the SBERT bit in the Interrupt Mask for SM (ISM), the setting of
this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if
the Local Bus is in the Configuration Mode.
Bit 3 / Status Bit for PCI System Error (PSERR). This status bit is a software version of the PCI Bus
hardware pin PSERR. It will be set to a one if the PCI Bus detects an address parity error or other PCI
Bus error. The PSERR bit will be cleared when read and will not be set again until another PCI Bus error
has occurred. If enabled via the PSERR bit in the Interrupt Mask for SM (ISM), the setting of this bit will
cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local
Bus is in the Configuration Mode. This status bit is also reported in the Control/Status register in the PCI
DS3134
Bit 4 / Status Bit for PCI System Error (PPERR). This status bit is a software version of the PCI Bus
hardware pin PPERR. It will be set to a one if the PCI Bus detects parity errors on the PAD and PCBE*
buses as experienced or reported by a target. The PPERR bit will be cleared when read and will not be set
again until another parity error has been detected. If enabled via the PPERR bit in the Interrupt Mask for
SM (ISM), the setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin
and also at the LINT* if the Local Bus is in the Configuration Mode. This status bit is also reported in the
Control/Status register in the PCI Configuration registers, see Section 9 for more details.
Bit 14 / Status Bit for Local Bus Error (LBE). This status bit applies to the Local Bus when it is
operate d in the PCI Bridge Mode. It will be set to a one when the Local Bus LRDY* signal is not
detected within nine LCLK periods. This indicates to the Host that an aborted Local Bus access has
occurred. If enabled via the LBE bit in the Interrupt Mask for SM (ISM), the setting of this bit will cause a
hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in
the Configuration Mode. The LBE bit is meaningless when the Local Bus is operated in the configuration
mode and should be ignored.
Bit 15 / Status Bit for Local Bus Interrupt (LBINT). This status bit will be set to a one if the Local
Bus LINT* signal has been detected as asserted. This status bit is only valid when the Local Bus is
operated in the PCI Bridge Mode. The LBINT bit will be cleared when read and will not be set again
until once again the LINT* signal pin has been detected as asserted. If enabled via the LBINT bit in the
Interrupt Mask for SM (ISM), the setting of this bit will cause a hardware interrupt at the PCI Bus via the
PINTA* signal pin. The LBINT bit is meaningless when the Local Bus is operated in the configuration
mode and should be ignored.
Register Name:ISM
Register Description:Interrupt Mask Register for SM
Register Address:0024h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Status Bit for Receive Change Of Frame Alignment (SRCOFA).0 = interrupt masked
1 = interrupt unmasked
Bit 1 / Status Bit for Transmit Change Of Frame Alignment (STCOFA).
0 = interrupt masked
1 = interrupt unmasked
Bit 2 / Status Bit for Change of State in BERT (SBERT).
0 = interrupt masked
1 = interrupt unmasked
DS3134
Bit 3 / Status Bit for PCI System Error (PSERR).
0 = interrupt masked
1 = interrupt unmasked
Bit 4 / Status Bit for PCI System Error (PPERR).
0 = interrupt masked
1 = interrupt unmasked
Bit 14 / Status Bit for Local Bus Error (LBE).
0 = interrupt masked
1 = interrupt unmasked
Bit 15 / Status Bit for Local Bus Interrupt (LBINT).0 = interrupt masked
1 = interrupt unmasked
Register Name:SV54
Register Description:Status Register for the Receive V.54 Detector
Register Address:0030h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 15 / Status Bit for Change of State in Receive V.54 Loopback Detector (SLBP0 to
SLBP15). These status bits will be set to a one when the V.54 loopback detector within the port has
either timed out in its search for the loop up pattern or it has detected and validated the loop up or down
pattern. There is one status bit per port. The Host must read the VTO and VLB status bits in RP[n]CR
register of the corresponding port to determine the exact status of the V.54 detector. If the V.54 detector
has timed out in it's search for the loop up code (VTO = 1), then SLBP will be continuously set until the
Host resets the V.54 detector by toggling the VRST bit in RP[n]CR. If enabled via the SLBP[n] bit in the
Interrupt Mask for SV54 (ISV54), the setting of these bits will cause a hardware interrupt at the PCI Bus
via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode. See
Section 5 for specific details on the operation of the V.54 loopback detector.
DS3134
Register Name:ISV54
Register Description:Interrupt Mask Register for SV54
Register Address:0034h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 15 / Status Bit for Change of State in Receive V.54 Loopback Detector (SLBP0 to
SLBP15).
0 = interrupt masked
1 = interrupt unmasked
Register Name:SDMA
Register Description:Status Register for DMA
Register Address:0028h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 2 / Status Bit for Receive HDLC CRC Error (RCRCE). This status bit will be set to a one if any
of the receive HDLC channels experiences a CRC check sum error. The RCRCE bit will be cleared when
read and will not be set again until another CRC check sum error has occurred. If enabled via the RCRCE
bit in the Interrupt Mask for SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the
PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.
Bit 3 / Status Bit for Receive HDLC Abort Detected (RABRT). This status bit will be set to a one if
any of the receive HDLC channels detects an abort. The RABRT bit will be cleared when read and will
not be set again until another abort has been detected. If enabled via the RABRT bit in the Interrupt Mask
for SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA*
signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.
Bit 4 / Status Bit for Receive HDLC Length Check (RLENC). This status bit will be set to a one if
any of the HDLC channels:
- Exceeds the octet length count (if so enabled to check for octet length)
- Receives a HDLC packet that does not meet the minimum length criteria of either 4 or 6 bytes
- Experiences a non-integral number of octets in between opening and closing flags.
The RLENC bit will be cleared when read and will not be set again until another length violation has
DS3134
will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the
Local Bus is in the Configuration Mode.
Bit 5 / Status Bit for Receive FIFO Overflow (ROVFL). This status bit will be set to a one if any of
the HDLC channels experiences an overflow in the receive FIFO. The ROVFL bit will be cleared when
read and will not be set again until another overflow has occurred. If enabled via the ROVFL bit in the
Interrupt Mask for SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI Bus
via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.
Bit 6 / Status Bit for Receive DMA Large Buffer Read (RLBR). This status bit will be set to a one
each time the Receive DMA completes a single read or a burst read of the Large Buffer Free Queue. The
RLBR bit will be cleared when read and will not be set again, until another read of the Large Buffer Free
Queue has occurred. If enabled via the RLBR bit in the Interrupt Mask for SDMA (ISDMA), the setting
of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT*
if the Local Bus is in the Configuration Mode.
Bit 7 / Status Bit for Receive DMA Large Buffer Read Error (RLBRE). This status bit will be set to
a one each time the Receive DMA tries to read the Large Buffer Free Queue and it is empty. The RLBRE
bit will be cleared when read and will not be set again, until another read of the Large Buffer Free Queue
detects that it is empty. If enabled via the RLBRE bit in the Interrupt Mask for SDMA (ISDMA), the
setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the
LINT* if the Local Bus is in the Configuration Mode.
Bit 8 / Status Bit for Receive DMA Small Buffer Read (RSBR). This status bit will be set to a one
each time the Receive DMA completes a single read or a burst read of the Small Buffer Free Queue. The
RSBR bit will be cleared when read and will not be set again, until another read of the Small Buffer Free
Queue has occurred. If enabled via the RSBR bit in the Interrupt Mask for SDMA (ISDMA), the setting
of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT*
if the Local Bus is in the Configuration Mode.
Bit 9 / Status Bit for Receive DMA Small Buffer Read Error (RSBRE). This status bit will be set to a
one each time the Receive DMA tries to read the Small Buffer Free Queue and it is empty. The RSBRE
bit will be cleared when read and will not be set again, until another read of the Small Buffer Free Queue
detects that it is empty. If enabled via the RSBRE bit in the Interrupt Mask for SDMA (ISDMA), the
setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the
LINT* if the Local Bus is in the Configuration Mode.
Bit 10 / Status Bit for Receive DMA Done Queue Write (RDQW). This status bit will be set to a one
when the Receive DMA writes to the Done Queue. Based of the setting of the Receive Done Queue
Threshold Setting (RDQT0 to RDQT2) bits in the Receive DMA Queues Control (RDMAQ) register, this
bit will be set either after each write or after a programmable number of writes from 2 to 128. See
Section 8.1.4 for more details. The RDQW bit will be cleared when read and will not be set again until
another write to the Done Queue has occurred. If enabled via the RDQW bit in the Interrupt Mask for
SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA*
signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.
DS3134
Bit 11 / Status Bit for Receive DMA Done Queue Write Error (RDQWE). This status bit will be set
to a one each time the Receive DMA tries to write to the Done Queue and it is full. The RDQWE bit will
be cleared when read and will not be set again until another write to the Done Queue detects that it is full.
If enabled via the RDQWE bit in the Interrupt Mask for SDMA (ISDMA), the setting of this bit will
cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local
Bus is in the Configuration Mode.
Bit 12 / Status Bit for Transmit FIFO Underflow (TUDFL). This status bit will be set to a one if any
of the HDLC channels experiences an underflow in the transmit FIFO. The TUDFL bit will be cleared
when read and will not be set again until another underflow has occurred. If enabled via the TUDFL bit
in the Interrupt Mask for SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the
PCI Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.
Bit 13 / Status Bit for Transmit DMA Pending Queue Read (TPQR). This status bit will be set to a
one each time the Transmit DMA reads the Pending Queue. The TPQR bit will be cleared when read and
will not be set again until another read of the Pending Queue has occurred. If enabled via the TPQR bit in
the Interrupt Mask for SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI
Bus via the PINTA* signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.
Bit 14 / Status Bit for Transmit DMA Done Queue Write (TDQW). This status bit will be set to a one
when the Transmit DMA writes to the Done Queue. Based of the setting of the Transmit Done Queue
Threshold Setting (TDQT0 to TDQT2) bits in the Transmit DMA Queues Control (TDMAQ) register,
this bit will be set either after each write or after a programmable number of writes from 2 to 128. See
Section 8.2.4 for more details. The TDQW bit will be cleared when read and will not be set again until
another write to the Done Queue has occurred. If enabled via the TDQW bit in the Interrupt Mask for
SDMA (ISDMA), the setting of this bit will cause a hardware interrupt at the PCI Bus via the PINTA*
signal pin and also at the LINT* if the Local Bus is in the Configuration Mode.
Bit 15 / Status Bit for Transmit DMA Done Queue Write Error (TDQWE). This status bit will be set
to a one each time the Transmit DMA tries to write to the Done Queue and it is full. The TDQWE bit
will be cleared when read and will not be set again until another write to the Done Queue detects that it is
full. If enabled via the TDQWE bit in the Interrupt Mask for SDMA (ISDMA), the setting of this bit will
cause a hardware interrupt at the PCI Bus via the PINTA* signal pin and also at the LINT* if the Local
Bus is in the Configuration Mode.
DS3134
Register Name:ISDMA
Register Description:Interrupt Mask Register for SDMA
Register Address:002Ch543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 2 / Status Bit for Receive HDLC CRC Error (RCRCE).
0 = interrupt masked
1 = interrupt unmasked
Bit 3 / Status Bit for Receive HDLC Abort Detected (RABRT).
0 = interrupt masked
1 = interrupt unmasked
Bit 4 / Status Bit for Receive HDLC Length Check (RLENC).
0 = interrupt masked
1 = interrupt unmasked
Bit 5 / Status Bit for Receive FIFO Overflow (ROVFL).
0 = interrupt masked
1 = interrupt unmasked
Bit 6 / Status Bit for Receive DMA Large Buffer Read (RLBR).
0 = interrupt masked
1 = interrupt unmasked
Bit 7 / Status Bit for Receive DMA Large Buffer Read Error (RLBRE).
0 = interrupt masked
1 = interrupt unmasked
Bit 8 / Status Bit for Receive DMA Small Buffer Read (RSBR).
0 = interrupt masked
1 = interrupt unmasked
Bit 9 / Status Bit for Receive DMA Small Buffer Read Error (RSBRE).
0 = interrupt masked
1 = interrupt unmasked
Bit 10 / Status Bit for Receive DMA Done Queue Write (RDQW).
0 = interrupt masked
1 = interrupt unmasked
DS3134
Bit 11 / Status Bit for Receive DMA Done Queue Write Error (RDQWE).
0 = interrupt masked
1 = interrupt unmasked
Bit 12 / Status Bit for Transmit FIFO Underflow (TUDFL).
0 = interrupt masked
1 = interrupt unmasked
Bit 13 / Status Bit for Transmit DMA Pending Queue Read (TPQR).
0 = interrupt masked
1 = interrupt unmasked
Bit 14 / Status Bit for Transmit DMA Done Queue Write (TDQW).
0 = interrupt masked
1 = interrupt unmasked
Bit 15 / Status Bit for Transmit DMA Done Queue Write Error (TDQWE).
0 = interrupt masked
1 = interrupt unmasked
4.4 TEST REGISTER DESCRIPTION
Register Name:TEST
Register Description:Test Register
Register Address:0050h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Factory Test (FT).
This bit is used by the factory to place the DS3134 into the test mode. For normal device operation, this
bit should be set to zero whenever this register is written to. Setting this bit places the RAMs into a low
power standby mode.
Bit 1 to 15 / Device internal test bits. Bits 1 to 15 shown in the above table is for CHATEAU internal
(Dallas Semiconductor) tests use, not user test mode controls. Values of these bits should always be “0”.
If any of these bits are set to “1” device will not function properly.
DS3134
SECTION 5: LAYER ONE
5.1 GENERAL DESCRIPTION
The Layer One Block is shown in Figure 5.1A. Each of the 16 Layer One ports on the DS3134 can be
configured to support either a channelized application or an unchannelized application. Users can mix the
applications on the ports as needed. Some or all of the ports can be channelized while the others can be
configured as unchannelized. A channelized application is defined as one that requires a 8 kHz
synchronization pulse to subdivide the serial data stream into a set of 8-bit DS0 channels (also called
timeslots) which are Time Division Multiplexed (TDM) one after another. Ports running a channelized
application require an 8 kHz pulse at the RS and TS signals. An unchannelized application is defined as a
synchronous clock and data interface. No synchronization pulse is required and the RS and TS signals are
forced low in this application. Section 14 contains examples of some various configurations.
In channelized applications, the Layer One ports can be configured to operate in one of four modes as
shown in Table 5.1A below. Each port is capable of handling one, two, or four T1/E1 data streams.
When more than one T1/E1 data stream is applied to the port, the individual T1/E1 data streams must be
TDM into a single data stream at either a 4.096 MHz or 8.192 MHz data rate. Since the DS3134 can map
any HDLC channel to any DS0 channel, it can support any form (byte interleaved, frame interleaved, etc.)
of TDM that the application may require. On a DS0 by DS0 basis, the DS3134 can be configured to
process all 8 bits (64 kbps), the seven most significant bits (56 kbps), or no data.
CHANNELIZED PORT MODES Table 5.1A
ModeDescription
T1 (1.544 MHz)N x 64 kbps or N x 56 kbps; where N = 1 to 24 (one T1 data stream)
E1 (2.048 MHz)N x 64 kbps or N x 56 kbps; where N = 1 to 32 (one T1 or E1 data stream)
4.096 MHzN x 64 kbps or N x 56 kbps; where N = 1 to 64 (two T1 or E1 data streams)
8.192 MHzN x 64 kbps or N x 56 kbps; where N = 1 to 128. (four T1 or E1 data streams)
Each port in the Layer One Block is connected to a Slow HDLC Engine. The Slow HDLC Engine is
capable of handling channelized applications at speeds up to 8.192 Mbps and unchannelized applications
at speeds of up to 10 Mbps. Ports 0 and 1 have the added capability of Fast HDLC Engines that are
capable of only handling unchannelized applications but at speeds of up to 52 MHz.
Each port has an associated Receive Port Control Register (RP[n]CR where n = 0 to 15) and a Transmit
Port Control Register (TP[n]CR where n = 0 to 15). These control registers are defined in detail in
Section 5.2 and they control all of the circuitry in the Layer One Block with the exception of the Layer
One State Machine which is shown in the center of the Block Diagram in Figure 5.1A.
DS3134
Each port contains a Layer One State Machine, which connects directly to the Slow HDLC Engine. The
Layer One State Machine prepares the raw incoming data for the Slow HDLC Engine and grooms the
outgoing data from the Slow HDLC Engine. The Layer One State Machine performs a number of tasks,
which include:
- Assigning the HDLC channel number to the incoming & outgoing data
- Channelized Local and Network loopbacks
- Channelized selection of 64 kbps, 56 kbps, or no data
- Channelized transmits DS0 channel fill of all onesRouting data to and from the BERT functionRouting data to the V.54 loop pattern detector.
The DS3134 has a set of three registers per DS0 channel for each port, which determine how each DS0
channel will be configured. These three registers are defined in Section 5.3. If the Fast (52 Mbps) HDLC
Engine is enabled on Port 0, then HDLC Channel 1 is assigned to it and likewise HDLC Channel 2 will
be assigned to the Fast HDLC Engine on Port 2 if it is enabled.
The DS3134 contains an onboard full-featured Bit Error Rate Tester (BERT) function, which is capable
of generating and detecting both pseudorandom and repeating serial bit patterns. The BERT function is
a shared resource among the 16 ports on the DS3134 and it can only be assigned to one port at a time.
The BERT function can be used in both channelized and unchannelized applications and at speeds up to
52 MHz. In channelized applications, data can be routed to and from any combination of DS0 channels
that are being used on the port. The details on the BERT function are covered in Section 5.5.
The Layer 1 Block also contains a V.54 detector. Each of the 16 ports within the DS3134 contains a V.54
loop pattern detector on the receive side. The device can search for the V.54 loop up and down patterns
in both channelized and unchannelized applications at speeds up to 10 MHz. In channelized applications,
the device can be configured to search for the patterns in any combination of DS0 channels. Section 5.4
describes all of the details on the V.54 detector.
DS3134
LAYER ONE BLOCK DIAGRAM Figure 5.1A
DS3134
PORT TIMING (FOR CHANNELIZED AND UNCHANNELIZED APPLICATIONS)
Figure 5.1B
RC[n] / TC[n]
Normal Mode
RD[n]
TD[n]
RS[n] / TS[n]
0 Clock Early &
Not Inverted
RS[n] / TS[n]
1/2 Clock Early &
Inverted
RS[n] / TS[n]
1 Clock Early &
Not Inverted
RS[n] / TS[n]
2 Clocks Early &
Not Inverted
RC[n] / TC[n]
Inverted Mode
tdm_tim
DS3134
5.2 PORT REGISTER DESCRIPTIONS
Receive Side Control Bits (one each for all 16 ports)
Register Name:RP[n]CR where n = 0 to 15 for each Port
Register Description:Receive Port [n] Control Register
Register Address:See the Register Map in Section 3543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Invert Clock Enable (RICE).
0 = do not invert clock (normal mode)
1 = invert clock (inverted clock mode)
Bit 1 / Invert Data Enable (RIDE).
0 = do not invert data (normal mode)
1 = invert data (inverted data mode)
Bit 2 / Invert Sync Enable (RISE).
0 = do not invert sync pulse (normal mode)
1 = invert sync pulse (inverted sync pulse mode)
Bit 3 / V.54 Detector Reset (VRST). Toggling this bit from a 0 to a 1 and then back to a 0 causes the
internal V.54 detector to be reset and begin searching for the V.54 loop up pattern. See Section 5.4 for
more details on the operation of the V.54 detector.
Bit 4 / Sync Delay Bit 0 (RSD0).
Bit 5 / Sync Delay Bit 1 (RSD1).
These two bits define the format of the sync signal that will be applied to the RS[n] input. These bits are
ignored if the port has been configured to operate in an unchannelized fashion (RUEN = 1).
00 = sync pulse is 0 clocks early
01 = sync pulse is 1/2 clock early
10 = sync pulse is 1 clock early
11 = sync pulse is 2 clocks early
DS3134
Bit 6 / Sync Select Bit 0 (RSS0).
Bit 7 / Sync Select Bit 1 (RSS1).
These 2 bits select the mode in which each port is to be operated. Each port can be configured to accept
24, 32, 64, or 128 DS0 channels at an 8 kHz rate. These bits are ignored if the port has been configured
to operate in an unchannelized fashion (RUEN = 1).
00 = T1 Mode (24 DS0 channels & 193 RC clocks in between RS sync signals)
01 = E1 Mode (32 DS0 channels & 256 RC clocks in between RS sync signals)
10 = 4.096 MHz Mode (64 DS0 channels & 512 RC clocks in between RS sync signals)
11 = 8.192 MHz Mode (128 DS0 channels & 1024 RC clocks in between RS sync signals)
Bit 8 / Port 0 High Speed Mode (RP0(1)HS). If enabled, the Port 0(1) Layer State Machine logic is
defeated and RC0(1) and RD0(1) are routed to some dedicated high speed HDLC processing logic. Only
present in RP0CR and RP1CR. Bit 8 is not assigned in Ports 2 through 15.
0 = disabled
1 = enabled
Bit 9 / Unchannelized Enable (RUEN). When enabled, this bit forces the port to operate in an
unchannelized fashion. When disabled, the port will operate in a channelized mode.
0 = channelized mode
1 = unchannelized mode
Bit 10 / Local Loopback Enable (LLB). This loopback routes transmit data back to the receive port. It
can be used in both channelized and unchannelized port operating modes, even on ports 0 & 1 operating
at speeds up to 52 MHz. See Figure 5.1A. In channelized applications, a per-channel loopback can be
realized by using the Channelized Local LoopBack (CLLB) function. See Section 5.3 for details on
CLLB.
0 = loopback disabled
1 = loopback enabled
Bit 12 / V.54 Time Out (VTO). This read only bit reports the real time status of the V.54 detector. It
will be set to a one when the V.54 detector has finished searching for the V.54 loop up pattern and has not
detected it. This indicates to the Host that the V.54 detector can now be used to search for the V.54 loop
up pattern on other HDLC channels and the Host can initiate this by configuring the RV54 bits in the
RP[n]CR register and then toggling the VRST control bit. See Section 5.4 for more details on how the
V.54 detector operates.
Bit 13 / V.54 Loopback (VLB). This read only bit reports the real time status of the V.54 detector. It
will be set to a one when the V.54 detector has verified that a V.54 loop up pattern has been seen. When
set, it will remain set until either the V.54 loop down pattern is seen or the V.54 detector is reset by the
Host (i.e. by toggling VRST). See Section 5.4 for more details on how the V.54 detector operates.
Bit 14 / Interrupt Enable for RCOFA (IERC).
0 = interrupt masked
1 = interrupt enabled
DS3134
Bit 15 / COFA Status Bit (RCOFA). This latched read only status bit will be set if a Change Of Frame
Alignment is detected. The COFA is detected by sensing that a sync pulse has occurred during a clock
period that was not the first bit of the 193/256/512/1024 bit frame. This bit will be reset when read and it
will not be set again until another COFA has occurred.
Transmit Side Control Bits (one each for all 16 ports)
Register Name:TP[n]CR where n = 0 to 15 for each Port
Register Description:Transmit Port [n] Control Register
Register Address:See the Register Map in Section 3543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Invert Clock Enable (TICE).
0 = do not invert clock (normal mode)
1 = invert clock (inverted clock mode)
Bit 1 / Invert Data Enable (TIDE).
0 = do not invert data (normal mode)
1 = invert data (inverted data mode)
Bit 2 / Invert Sync Enable (TISE).
0 = do not invert sync pulse (normal mode)
1 = invert sync pulse (inverted sync pulse mode)
Bit 3 / Force Data All 1's (TFDA1*).
0 = force all data at TD to be one
1 = allow data to be transmitted normally
Bit 4 / Sync Delay Bit 0 (TSD0).
Bit 5 / Sync Delay Bit 1 (TSD1).
These 2 bits define the format of the sync signal that will be applied to the TS[n] input. These bits are
ignored if the port has been configured to operate in an unchannelized fashion (TUEN = 1).
00 = sync pulse is 0 clocks early
01 = sync pulse is 1/2 clock early
10 = sync pulse is 1 clock early
11 = sync pulse is 2 clocks early
DS3134
Bit 6 / Sync Select Bit 0 (TSS0).
Bit 7 / Sync Select Bit 1 (TSS1).
These 2 bits select the mode in which each port is to be operated. Each port can be configured to accept
24, 32, 64, or 128 DS0 channels at an 8 kHz rate. These bits are ignored if the port has been configured
to operate in an unchannelized fashion (TUEN = 1).
00 = T1 Mode (24 DS0 channels & 193 RC clocks in between TS sync signals)
01 = E1 Mode (32 DS0 channels & 256 RC clocks in between TS sync signals)
10 = 4.096 MHz Mode (64 DS0 channels & 512 RC clocks in between TS sync signals)
11 = 8.192 MHz Mode (128 DS0 channels & 1024 RC clocks in between TS sync signals)
Bit 8 / Port 0 High Speed Mode (TP0(1)HS). If enabled, the Port 0(1) Layer 1 State Machine logic is
defeated and TC0(1) and TD0(1) are routed to some dedicated high speed HDLC processing logic. Only
present in TP0CR and TP1CR. Bit 8 is not assigned in Ports 2 through 15.
0 = disabled
1 = enabled
Bit 9 / Unchannelized Enable (TUEN). When enabled, this bit forces the port to operate in an
unchannelized fashion. When disabled, the port will operate in a channelized mode. This bit overrides
the Transmit Channel Enable (TCHEN) bit in the Transmit Layer 1 Configuration (T[n]CFG[j]) registers
which are described in Section 5.3.
0 = channelized mode
1 = unchannelized mode
Bit 10 / Unchannelized Network Loopback Enable (UNLB). See Figure 5.1A for details. This
loopback cannot be used for ports 0 & 1 when they are being operated at speeds greater than 10 MHz.
0 = loopback disabled
1 = loopback enabled
Bit 11 / Unchannelized BERT Select (TUBS). This bit is ignored if TUEN = 0. This bit overrides the
Transmit BERT (TBERT) bit in the Transmit Layer 1 Configuration (T[n]CFG[j]) registers which are
described in Section 5.3.
0 = source transmit data from the HDLC controller
1 = source transmit data from the BERT block
Bit 14 / Interrupt Enable for TCOFA (IETC).
0 = interrupt masked
1 = interrupt enabled
Bit 15 / COFA Status Bit (TCOFA). This latched read only status bit will be set if a Change Of Frame
Alignment is detected. A COFA is detected by sensing that a sync pulse has occurred during a clock
period that was not the first bit of the 193/256/512/1024 bit frame. This bit will be reset when read and it
will not be set again until another COFA has occurred.
DS3134
5.3 LAYER ONE CONFIGURATION REGISTER DESCRIPTION
There are three configuration registers for each DS0 channel on each port. These three registers are
shown in Figure 5.3A. As shown in Figure 5.1A, each of the 16 ports contains a PORT RAM, this
controls the Layer One State Machine. These 384 registers (three registers x 128 DS0 channels per port)
make up the PORT RAM for each port and they control and provide access to the Layer One State
Machine. These registers are accessed indirectly via the Channelized Port Register Data (CP[n]RD)
register. The Host must first write to the Channelized Port Register Data Indirect Select (CP[n]RDIS)
register to chose which DS0 channel and which channelized PORT RAM that it wishes to configure or
read. On power-up, the Host must write to all of the used R[n]CFG[j] and T[n]CFG[j] locations to make
sure that they are set into a known state.
LAYER ONE REGISTER SET Figure 5.3A
C[n]DAT[j]: Channelized DS0 Datalsb
msb
R[n]CFG[j]: Receive Configurationlsb
msb
T[n]CFG[j]: Transmit Configurationlsb
msb
Register Name:CP[n]RDIS where n = 0 to 15 for each Port
Register Description:Channelized Port [n] Register Data Indirect Select
Register Address:See the Register Map in Section 3543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 6 / DS0 Channel ID (CHID0 to CHID6). The number of DS0 channels used depends on
whether the port has been configured for an unchannelized application or for a channelized application
and if set for a channelized application, then whether the port has been configured in the T1, E1, 4.096
MHz, or 8.192 MHz mode.
DS3134
Port ModeDS0 Channels
Available
Unchannelized Mode (RUEN/TUEN = 1)0
Channelized T1 Mode (RUEN/TUEN = 0 & RSS0/TSS0 = 0 & RSS1/TSS1 = 0)0 to 23
Channelized E1 Mode (RUEN/TUEN = 0 & RSS0/TSS0 = 1 & RSS1/TSS1 = 0)0 to 31
Channelized 4.096 MHz Mode (RUEN/TUEN = 0 & RSS0/TSS0 = 0 &
RSS1/TSS1 = 1)
0 to 63
Channelized 8.192 MHz Mode (RUEN/TUEN = 0 & RSS0/TSS0 = 1 &
RSS1/TSS1 = 1)
0 to 127
Bit 8 / Channelized PORT RAM Select Bit 0 (CPRS0).
Bit 9 / Channelized PORT RAM Select Bit 1 (CPRS1).
00 = Channelized DS0 Data (C[n]DAT[j])
01 = Receive Configuration (R[n]CFG[j])
10 = Transmit Configuration (T[n]CFG[j])
11 = illegal selection
Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal
Channelized PORT RAM, this bit should be written to a one by the host. This causes the device to begin
obtaining the data from the DS0 channel location indicated by the CHID bits and the PORT RAM
indicated by the CPRS0 and CPRS1 bits. During the read access, the IAB bit will be set to one. Once the
data is ready to be read from the CP[n]RD register, the IAB bit will be set to zero. When the host wishes
to write data to the internal Channelized PORT RAM, this bit should be written to a zero by the host.
This causes the device to take the data that is currently present in the CP[n]RD register and write it to the
PORT RAM indicated by the CPRS0 and CPRS1 bits and the DS0 channel indicated by the CHID bits.
When the device has completed the write, the IAB will be set to zero.
Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only
bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be
read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set
to a one while the write is taking place. It will be set to zero once the write operation has completed.
DS3134
Register Name:CP[n]RD where n = 0 to 15 for each Port
Register Description:Channelized Port [n] Register Data
Register Address:See the Register Map in Section 3543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 15 / DS0 Channel Data (CHD0 to CHD15). The 16-bit data that is to either be written into or
read from the PORT RAM specified by the CP[n]RDIS register.
Port RAM Indirect Access Figure 5.3B
Port RAM (one each for all 16 Ports; n = 0 to 15)
DS3134
Register Name:C[n]DAT[j] where n = 0 to 15 for each Port & j = 0 to 127 for each DS0
Register Description:Channelized Layer 1 DS0 Data Register
Register Address:Indirect Access Via CP[n]RD543210
RDATA(8): Receive DS0 Data141312111098
Note: Bits that are underlined are read only, all other bits are read-write.
Note: In normal device operation, the Host must never write to the C[n]DAT[j] registers.
Bits 0 to 7 / Receive DS0 Data (RDATA). This register holds the most current DS0 byte received. It is
used by the transmit side Layer One State Machine when Channelized Network LoopBack (CNLB) is
enabled.
Bits 8 to 15 / Transmit DS0 Data (TDATA). This register holds the most current DS0 byte transmitted.
It is used by the receive side Layer One State Machine when Channelized Local LoopBack (CLLB) is
enabled.
Register Name:R[n]CFG[j] where n = 0 to 15 for each Port & j = 0 to 127 for each DS0
Register Description:Receive Layer 1 Configuration Register
Register Address:Indirect Access via CP[n]RD543210
RCH#(8): Receive HDLC Channel Number141312111098
Note: Bits that are underlined are read only, all other bits are read-write.
Bits 0 to 7 / Receive Channel Number (RCH#). The CPU will load the number of the HDLC channel
associated with this particular DS0 channel. If the port is running in an unchannelized mode (RUEN = 1),
then the HDLC Channel Number only needs to be loaded into R[n]CFG0. If the Fast (52 Mbps) HDLC
Engine is enabled on Port 0, then HDLC Channel 1 is assigned to it and likewise HDLC Channel 2 will
be assigned to the Fast HDLC Engine on Port 2 if it is enabled. Hence, these HDLC channel numbers
should not be used if the Fast HDLC Engines are enabled.
00000000 (00h) = HDLC Channel Number 1 (also used for the Fast HDLC Engine on Port 0)
00000001 (01h) = HDLC Channel Number 2 (also used for the Fast HDLC Engine on Port 1)
00000010 (02h) = HDLC Channel Number 3
11111111 (FFh) = HDLC Channel Number 256
DS3134
Bit 8 / Receive 56 kbps (R56). If the Port is running a channelized application, this bit determines
whether the LSB of each DS0 should be processed or not. If this bit is set, then the LSB of each DS0
channel will not be routed to the HDLC controller (or the BERT if it has been enabled via the RBERT
bit). This bit does not affect the operation of the V.54 detector (it always searches on all 8 bits in the
DS0).
0 = 64 kbps (use all 8 bits in the DS0)
1 = 56 kbps (use only the first seven bits received in the DS0)
Bit 10 / Channelized Local LoopBack Enable (CLLB). Enabling this loopback forces the transmit data
to replace the receive data. This bit must be set for each and every DS0 channel that is to be looped back.
In order for the loopback to become active, the DS0 channel must be enabled (RCHEN = 1) and the DS0
channel must be set into the 64 kbps mode (R56 = 0).
0 = loopback disabled
1 = loopback enabled
Bit 12 / Receive V.54 Enable (RV54E). If this bit is cleared, this DS0 channel will not be examined to
see if the V.54 loop pattern is present. If set, the DS0 will be examined for the V.54 loop pattern. When
searching for the V.54 pattern within a DS0 channel, all 8 bits of the DS0 channel are examined
regardless of how the DS0 channel is configured (i.e. 64k or 56k).
0 = do not examine this DS0 channel for the V.54 loop pattern
1 = examine this DS0 channel for the V.54 loop pattern
Bit 14 / Route Data Into BERT (RBERT). Setting this bit will route the DS0 data into the BERT
function. If the DS0 channel has been configured for 56 kbps operation (R56 = 1), then the LSB of each
DS0 channel is not routed to the BERT block. In order for the data to make it to the BERT block, the
Host must also configure the BERT for the proper port via the Master Control register (see Section 4).
0 = do not route data to BERT
1 = route data to BERT
Bit 15 / Receive DS0 Channel Enable (RCHEN). This bit must be set for each active DS0 channel in a
channelized application. In a channelized application, although a DS0 channel is deactivated, the channel
can still be set up to route data to the V.54 detector and/or the BERT block. In addition, although a DS0
channel is active, the loopback function (CLLB = 1) overrides this activation and will route transmit data
back to the HDLC controller instead of the data coming in via the RD pin. In an unchannelized mode
(RUEN = 1), only the RCHEN bit in R[n]CFG0 needs to be configured.
0 = deactivated DS0 channel
1 = active DS0 channel
Register Name:T[n]CFG[j] where n = 0 to 15 for each Port & j = 0 to 127 for each DS0
Register Description:Transmit Layer 1 Configuration Register
Register Address:Indirect Access via CP[n]RD543210
TCH#(8): Transmit HDLC Channel Number141312111098
DS3134
Bits 0 to 7 / Transmit Channel Number (TCH#). The CPU will load the number of the HDLC channel
associated with this particular DS0 channel. If the port is running in an unchannelized mode (TUEN = 1),
then the HDLC Channel Number only needs to be loaded into T[n]CFG0. If the Fast (52 Mbps) HDLC
Engine is enabled on Port 0, then HDLC Channel 1 is assigned to it and likewise HDLC Channel 2 will
be assigned to the Fast HDLC Engine on Port 2 if it is enabled. Hence, these HDLC channel numbers
should not be used if the Fast HDLC Engines are enabled.
00000000 (00h) = HDLC Channel Number 1 (also used for the Fast HDLC Engine on Port 0)
00000001 (01h) = HDLC Channel Number 2 (also used for the Fast HDLC Engine on Port 1)
00000010 (02h) = HDLC Channel Number 3
11111111 (FFh) = HDLC Channel Number 256
Bit 8 / Transmit 56 kbps (T56). If the port is running a channelized application, this bit determines
whether the LSB of each DS0 should be processed or not. If this bit is set, then the LSB of each DS0
channel will not be routed from the HDLC controller (or the BERT if it has been enabled via the RBERT
bit) and the LSB bit position will be forced to a one.
0 = 64 kbps (use all 8 bits in the DS0)
1 = 56 kbps (use only the first 7 bits transmitted in the DS0; force the LSB to one)
Bit 9 / Transmit Force All Ones (TFAO). If this bit is set, then eight ones will be placed into the DS0
channel for transmission instead of the data that is being sourced from the HDLC controller. If this bit is
cleared, then the data from the HDLC controller will be transmitted. This bit is useful in instances when
Channelized Local LoopBack (CLLB) is being activated to keep the looped back data from being sent out
onto the network. This bit overrides TCHEN.
0 = transmit data from the HDLC controller
1 = force transmit data to all ones
Bit 11 / Channelized Network LoopBack Enable (CNLB). Enabling this loopback forces the receive
data to replace the transmit data. This bit must be set for each and every DS0 channel that is to be looped
back. This bit overrides TBERT, TFAO, and TCHEN.
0 = loopback disabled
1 = loopback enabled
Bit 14 / Route Data from BERT (TBERT). Setting this bit will route DS0 data to the TD pin from the
BERT block instead of from the HDLC controller. If the DS0 channel has been configured for 56 kbps
operation (T56 = 1), then the LSB of each DS0 channel will not be routed from the BERT block but will
be forced to a one instead. In order for the data to make it from the BERT block, the Host must also
configure the BERT for the proper port via the Master Control register (see Section 4). This bit overrides
TFAO and TCHEN.
0 = do not route data from BERT
1 = route data from BERT (override the data from the HDLC controller)
DS3134
Bit 15 / Transmit DS0 Channel Enable (TCHEN). This bit must be set for each active DS0 channel inchannelized application. In a channelized application, although a DS0 channel is deactivated, the
channel can still be set up to route data from the BERT block. In addition, although a DS0 channel is
active, the loopback function (CNLB = 1) overrides this activation and will route receive data to the TD
pin instead of from the HDLC. In an unchannelized mode (TUEN = 1), only the TCHEN bit in T[n]CFG0
needs to be configured.
0 = deactivated DS0 channel
1 = active DS0 channel
5.4 RECEIVE V.54 DETECTOR
Each port within the device contains a V.54 loop pattern detector. V.54 is a pseudorandom pattern that
will be sent for at least 2 seconds followed immediately by an all ones pattern for at least two seconds if
the channel is to be placed into loopback. The exact pattern and sequence is defined in Annex B of ANSI
T1.403-1995.
When a port is configured for unchannelized operation (RUEN = 1), all of the data entering the port via
RD is routed to the V.54 detector. If the Host wishes not to utilize the V.54 detector, then the SLBP
status bits in the Status V.54 (SV54) register should be ignored and their corresponding interrupt mask
bits in ISV54 should be set to 0 to keep from disturbing the Host. Details on the status and interrupt bits
can be found in Section 4.
When the port is configured for channelized operation (RUEN = 0), then it is the Host's responsibility to
determine which DS0 channels should be searched for the V.54 pattern. In channelized applications, it
may be that there will be multiple HDLC channels that the Host wishes to look for the V.54 pattern in. If
this is true, then the Host will perform the routine shown in Table 5.4A. A flowchart of the same routine
is shown in Figure 5.4A
DS3134
Receive V.54 Search Routine Table 5.4A
DS3134
Receive V.54 Host Algorithm Figure 5.4A
Set Up the
DS0 Channel
Search
Toggle VRST
Wait for
SLBP = 1
VTO = 1
Place DS0
Channels into
Loopback
Wait for
SLBP = 1
Take DS0
Channels out
of Loopback
v54host
SLBP is a status bit that is reported
in the SV54 register (see Section 4.3)
VRST is a control bit that is in the Receive
Port Control Register (see Section 5.2)
VTO is a status bit that is in the Receive
Port Control Register (see Section 5.2)
SLBP is a status bit that is reported
in the SV54 register (see Section 4.3)
DS0 channels can be configured to search
for the V.54 loop pattern via the Receive
Layer 1 Configuration Register (see Section 5.3)
NOTESALGORITHM
DS0 channels can be placed into loopback
via the Receive Layer 1 Configuration Register
(see Section 5.3)
DS0 channels can be taken out of loopback
via the Receive Layer 1 Configuration Register
(see Section 5.3)
DS3134
Receive V.54 State Machine Figure 5.4B
VRST = 1
VLB = 0
VTO = 0
SLBP = 0
Search for
Loop Up
Pattern for
32 VCLKs
Reset 4 second timer;
wait for Loss of Sync or
All 1s (64 in a Row)
or for the 4 second
timer to expire
Search for
Loop Down
Pattern
VLB = 1
Sync = 0
VLB = 0
Sync = 1
VTO = 1
Sync = 0
Sync = 0 or
4 Second Timer
Has Expired
Sync = 1
Time Out (VTO)
Loopback (VLB);
both in RP[n]CR
CLK
Data
VRST (in RP[n]CR)
v54sm
SYSCLK
Sysclk is used only to time
a 4 second timer. It is run into
a 2E27 counter which provides
a 4.03 second time out with a
33MHz clock and a 5.37 second
time out with a 25MHz clock
wait for Loss of Sync or
All 1s (64 in a Row)
Sync = 0
Change of
State in Status
(SLBP); in SV54
SLBP = 1
SLBP = 1
DS3134
5.5 BERT
The BERT Block is capable of generating and detecting the following patterns:
- The pseudorandom patterns 2E7, 2E11, 2E15, and QRSS
- A repetitive pattern from 1 to 32 bits in length
- Alternating (16-bit) words which flip every 1 to 256 words
The BERT receiver has a 32-bit Bit Counter and a 24-bit Error Counter. It can generate interrupts on
detecting a bit error, a change in synchronization, or if an overflow occurs in the Bit and Error Counters.
See Section 4 for details on status bits and interrupts from the BERT Block. To activate the BERT Block,
the Host must configure the BERT mux (see Figure 5.5A) and in channelized applications, the Host must
also configure the Layer One State Machine to send/obtain data to/from the BERT Block via the Layer
One Configuration Registers (see Section 5.3).
BERT Mux Diagram Figure 5.5A
Port 0 (slow)
Port 1 (slow)
Port 2 (slow)
Port 3 (slow)
Port 4 (slow)
Port 5 (slow)
bertbd
SBERT Status Bit
in SM
Internal Control &
Configuration Bus
Port 13 (slow)
Port 14 (slow)
Port 15 (slow)
Port 0 (fast)
Port 1 (fast)
DS3134
5.6 BERT REGISTER DESCRIPTION
BERT Register Set Figure 5.6A
BERTC0: BERT Control 0lsb
msb
BERTC1: BERT Control 1lsb
msb
BERTRP0: BERT Repetitive Pattern Set 0 (lower word)lsb
msb
BERTRP1: BERT Repetitive Pattern Set 1 (upper word)lsb
msb
BERTBC0: BERT Bit Counter 0 (lower word)lsb
msb
BERTBC1: BERT Bit Counter 0 (upper word)lsb
msb
BERTEC0: BERT Error Counter 0 / Statuslsb
msb
BERTEC1: BERT Error Counter 1 (upper word)lsb
msb
DS3134
Register Name:BERTC0
Register Description:BERT Control Register 0
Register Address:0500h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Force Resynchronization (RESYNC). A low to high transition will force the receive BERT
synchronizer to resynchronize to the incoming data stream. This bit should be toggled from low to high
whenever the host wishes to acquire synchronization on a new pattern. Must be cleared and set again for
a subsequent resynchronization. Note: Bit 2, 3 & 4 must be set, minimum of 64 system clock cycles,
before toggle the Resync bit (bit 0).
Bit 1 / Load Bit and Error Counters (LC). A low to high transition latches the current bit and error
counts into the host accessible registers BERTBC and BERTEC and clears the internal count. This bit
should be toggled from low to high whenever the host wishes to begin a new acquisition period. Must be
cleared and set again for a subsequent loads.
Bit 2 / Pattern Select Bit 0 (PS0).
Bit 3 / Pattern Select Bit 0 (PS1).
Bit 4 / Pattern Select Bit 1 (PS2).
000 = Pseudorandom Pattern 2E7 - 1
001 = Pseudorandom Pattern 2E11 - 1
010 = Pseudorandom Pattern 2E15 - 1
011 = Pseudorandom Pattern QRSS (2E20 - 1 with a one forced if the next 14 positions are zero)
100 = Repetitive Pattern
101 = Alternating Word Pattern
110 = illegal state
111 = illegal state
Bit 5 / Receive Invert Data Enable (RINV).
0 = do not invert the incoming data stream
1 = invert the incoming data stream
Bit 6 / Transmit Invert Data Enable (TINV).
0 = do not invert the outgoing data stream
1 = invert the outgoing data stream
Bit 8 / Repetitive Pattern Length Bit 0 (RPL0).
Bit 9 / Repetitive Pattern Length Bit 1 (RPL1).
Bit 10 / Repetitive Pattern Length Bit 2 (RPL2).
DS3134
Bit 11 / Repetitive Pattern Length Bit 3 (RPL3).
RPL0 is the LSB and RPL3 is the MSB of a nibble that describes the how long the repetitive pattern is.
The valid range is 17 (0000) to 32 (1111). These bits are ignored if the receive BERT is programmed for
a pseudorandom pattern. To create repetitive patterns less than 17 bits in length, the user must set the
length to an integer number of the desired length that is less than or equal to 32. For example, to create a
6 bit pattern, the user can set the length to 18 (0001) or to 24 (0111) or to 30 (1101).
Repetitive Pattern Length Map
LengthCodeLengthCodeLengthCodeLengthCode
17 Bits000018 Bits000119 Bits001020 Bits0011
21 Bits010022 Bits010123 Bits011024 Bits0111
25 Bits100026 Bits100127 Bits101028 Bits1011
29 Bits110030 Bits110131 Bits111032 Bits1111
Bit 13 / Interrupt Enable for Counter Overflow (IEOF). Allows the receive BERT to cause an
interrupt if either the Bit Counter or the Error Counter overflows.
0 = interrupt masked
1 = interrupt enabled
Bit 14 / Interrupt Enable for Bit Error Detected (IEBED). Allows the receive BERT to cause an
interrupt if a bit error is detected.
0 = interrupt masked
1 = interrupt enabled
Bit 15 / Interrupt Enable for Change of Synchronization Status (IESYNC). Allows the receive
BERT to cause an interrupt if there is a change of state in the synchronization status (i.e. the receive
BERT either goes into or out of synchronization).
0 = interrupt masked
1 = interrupt enabled
Register Name:BERTC1
Register Description:BERT Control Register 1
Register Address:0504h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Transmit Pattern Load (TC). A low to high transition loads the pattern generator with
Repetitive or pseudorandom pattern that is to be generated. This bit should be toggled from low to high
whenever the host wishes to load a new pattern. Must be cleared and set again for a subsequent loads.
DS3134
Bit 4 / Single Bit Error Insert (SBE). A low to high transition will create a single bit error. Must be
cleared and set again for a subsequent bit error to be inserted.
Bit 5 / Error Insert Bit 0 (EIB0).
Bit 6 / Error Insert Bit 1 (EIB1).
Bit 7 / Error Insert Bit 2 (EIB2).
Will automatically insert bit errors at the prescribed rate into the generated data pattern. Useful for
verifying error detection operation.
EIB
EIB
EIB
Error Rate Inserted00no errors automatically inserted
00110E-1
01010E-2
01110E-3
10010E-4
10110E-5
11010E-6
11110E-7
Bits 8 to 15 / Alternating Word Count Rate. When the BERT is programmed in the alternating word
mode, the words will repeat for the count loaded into this register then flip to the other word and again
repeat for the number of times loaded into this register. The valid count range is from 05h to FFh.
Register Name:BERTRP0
Register Description:BERT Repetitive Pattern Set 0
Register Address:0508h
Register Name:BERTRP1
Register Description:BERT Repetitive Pattern Set 1
Register Address:050Ch
BERTRP0: BERT Repetitive Pattern Set 0 (lower word)543210
BERT Repetitive Pattern Set (lower byte)141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
DS3134
BERTRP1: BERT Repetitive Pattern Set 1 (upper word)22212019181716
BERT Repetitive Pattern Set30292827262524
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 31 / BERT Repetitive Pattern Set (BERTRP0 and BERTRP1). These registers must be
properly loaded for the BERT to properly generate and synchronize to a repetitive pattern, a
pseudorandom pattern, or an alternating word pattern. For a repetitive pattern that is less than 32 bits,
then the pattern should be repeated so that all 32 bits are used to describe the pattern. For example if the
pattern was the repeating 5-bit pattern …01101… (Where right most bits are one sent first and received
first) then PBRP0 should be loaded with xB5AD and PBRP1 should be loaded with x5AD6. For a
pseudorandom pattern, both registers should be loaded with all ones (i.e. xFFFF). For an alternating word
pattern, one word should be placed into PBRP0 and the other word should be placed into PBRP1. For
example, if the DDS stress pattern "7E" is to be described, the user would place x0000 in PBRP0 and
x7E7E in PBRP1 and the alternating word counter would be set to 50 (decimal) to allow 100 bytes of 00h
followed by 100 bytes of 7Eh to be sent and received.
Register Name:BERTBC0
Register Description:BERT 32-Bit Bit Counter (lower word)
Register Address:0510h
Register Name:BERTBC1
Register Description:BERT 32-Bit Bit Counter (upper word)
Register Address:0514h
BERTBC0: BERT Bit Counter 0 (lower word)543210
BERT 32-Bit Bit Counter (lower byte)141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
BERTBC1: BERT Bit Counter 0 (upper word)22212019181716
BERT 32-Bit Bit Counter30292827262524
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
DS3134
Bits 0 to 31 / BERT 32-Bit Bit Counter (BERTBC0 and BERTBC1). This 32-bit counter will
increment for each data bit (i.e. clock) received. This counter is not disabled when the receive BERT
loses synchronization. This counter will be loaded with the current bit count value when the LC control
bit in the BERTC0 register is toggled from a low (0) to a high (1). When full, this counter will saturate
and set the BBCO status bit.
Register Name:BERTEC0
Register Description:BERT 24-Bit Error Counter (lower) & Status Information
Register Address:0518h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bit 0 / Real Time Synchronization Status (SYNC). Real time status of the synchronizer (this bit is not
latched). Will be set when the incoming pattern matches for 32 consecutive bit positions. Will be cleared
when 6 or more bits out of 64 are received in error.
Bit 1 / BERT Error Counter Overflow (BECO). A latched bit which is set when the 24-bit BERT
Error Counter (BEC) overflows. Cleared when read and will not be set again until another overflow
occurs.
Bit 2 / BERT Bit Counter Overflow (BBCO). A latched bit which is set when the 32-bit BERT Bit
Counter (BBC) overflows. Cleared when read and will not be set again until another overflow occurs.
Bit 3 / Bit Error Detected (BED). A latched bit which is set when a bit error is detected. The receive
BERT must be in synchronization for it detect bit errors. Cleared when read.
Bit 4 / Receive Loss Of Synchronization (RLOS). A latched bit which is set whenever the receive
BERT begins searching for a pattern. Once synchronization is achieved, this bit will remain set until
read.
Bit 5 / Receive All Zeros (RA0). A latched bit which is set when 31 consecutive zeros are received.
Allowed to be cleared once a one is received.
Bit 6 / Receive All Ones (RA1). A latched bit which is set when 31 consecutive ones are received.
Allowed to be cleared once a zero is received.
Bits 8 to 15 / BERT 24-Bit Error Counter (BEC). Lower word of the 24-bit error counter. See the
BERTEC1 register description for details.
DS3134
Register Name:BERTEC1
Register Description:BERT 24-Bit Error Counter (upper)
Register Address:051Ch543210
BERT 24-Bit Error Counter141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 15 / BERT 24-Bit Error Counter (BEC). Upper two words of the 24-bit error counter. This
24-bit counter will increment for each data bit received in error. This counter is not disabled when the
receive BERT loses synchronization. This counter will be loaded with the current bit count value when
the LC control bit in the BERTC0 register is toggled from a low (0) to a high (1). When full, this counter
will saturate and set the BECO status bit.
DS3134
SECTION 6: HDLC
6.1 GENERAL DESCRIPTION
The DS3134 contains two different types of HDLC controllers. Each port has a Slow HDLC Engine (type
#1) associated with it that can operate in either a channelized mode up to 8.192 Mbps or an unchannelized
mode at rates up to 10 Mbps. Ports 0 and 1 also have associated with them, an additional Fast HDLC
Engine (type #2) that is capable of operating in only an unchannelized fashion up to 52 Mbps. Via the
Layer One registers (see Section 5.2), the Host will determine which type of HDLC controller will be
used on a Port and if the HDLC controller is to be operated in either a channelized or unchannelized
mode. If the HDLC controller is to be operated in the channelized mode, then the Layer One registers
(see Section 5.3) will also determine which HDLC channels are associated with which DS0 channels. If
the Fast HDLC Engine is enabled on Port 0, then HDLC Channel 1 is assigned to it and likewise HDLC
Channel 2 will be assigned to the Fast HDLC Engine on Port 1 if it is enabled.
The HDLC controllers are capable of handling all the normal real-time tasks required. Table 6.1B lists all
of the functions supported by the Receive HDLC and Table 6.1C lists all of the functions supported by the
Transmit HDLC. Each of the 256 HDLC channels within Chateau are configured by the Host via the
Receive HDLC Channel Definition (RHCD) and Transmit Channel Definition (THCD) registers. There
is a separate RHCD and THCD register for each HDLC channel. The Host can access the RHCD and
THCD registers indirectly via the RHCDIS indirect select and THCDIS indirect select registers. See
Section 6.2 for details.
On the receive side, when the HDLC Block is processing a packet, one of the outcomes shown in
Table 6.1A will occur. For each packet, one of these outcomes will be reported in the Receive Done
Queue Descriptor (see Section 8.1.4 for details). On the transmit side, when the HDLC Block is
processing a packet, an error in the PCI Block (parity or target abort) or transmit FIFO underflow will
cause the HDLC Block to send an Abort sequence (8 ones in a row) followed continuously by the selected
Interfill (either 7Eh or FFh) until the HDLC channel is reset by the transmit DMA Block (see Section
8.2.1 for details). This same sequence of events will occur even if the transmit HDLC channel is being
operated in the transparent mode. In the transparent mode, when the FIFO empties the device will send
either 7Eh or FFh.
Receive HDLC Packet Processing Outcomes Table 6.1A
OutcomeCriteria
EOF / Normal
Packet
Integral number of packets > min. & < max. is received & CRC is okay
EOF / Bad FCSIntegral number of packets > min. & < max. is received & CRC is bad
Abort DetectedSeven or more ones in a row detected
EOF / Too Few
Bytes
Less than 4 or 6 bytes received
Too Many BytesGreater than the packet maximum is received (if detection enabled)
EOF / Bad # of BitsNot an integral number of bytes received
FIFO OverflowTried to write a byte into an already full FIFO
DS3134
If any of the 256 receive HDLC channels detects an abort sequence, a FCS checksum error, or if the
packet length was incorrect, then the appropriate status bit in the Status Register for DMA (SDMA) will
be set. If enabled, the setting of any of these statuses can cause a hardware interrupt to occur. See
Section 4.3.2 for details on the operation of these status bits.
Receive HDLC Functions Table 6.1B
DS3134
Transmit HDLC Functions Table 6.1C
6.2 HDLC REGISTER DESCRIPTION
Register Name:RHCDIS
Register Description:Receive HDLC Channel Definition Indirect Select
Register Address:0400h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).
00000000 (00h) = HDLC Channel Number 1 (also used for the Fast HDLC Engine on Port 0)
00000001 (01h) = HDLC Channel Number 2 (also used for the Fast HDLC Engine on Port 1)
00000010 (02h) = HDLC Channel Number 3
11111111 (FFh) = HDLC Channel Number 256
DS3134
Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal
Receive HDLC Definition RAM, this bit should be written to a one by the host. This causes the device to
begin obtaining the data from the channel location indicated by the HCID bits. During the read access,
the IAB bit will be set to one. Once the data is ready to be read from the RHCD register, the IAB bit will
be set to zero. When the host wishes to write data to the internal Receive HDLC Definition RAM, this bit
should be written to a zero by the host. This causes the device to take the data that is current present in
the RHCD register and write it to the channel location indicated by the HCID bits. When the device has
completed the write, the IAB will be set to zero.
Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only
bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be
read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set
to a one while the write is taking place. It will be set to zero once the write operation has completed.
Register Name:RHCD
Register Description:Receive HDLC Channel Definition
Register Address:0404h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write.
Bit 0 / Receive Transparent Enable (RTRANS). When this bit is set low, the HDLC engine performs
flag delineation, zero destuffing, abort detection, octet length checking (if enabled via ROLD), and FCS
checking (if enabled via RCRC0/1). When this bit is set high, the HDLC engine does not perform flag
delineation, zero destuffing, and abort detection, octet length checking, or FCS checking.
0 = transparent mode disabled
1 = transparent mode enabled
Bit 1 / Receive Octet Length Detection Enable (ROLD). When this bit is set low, the HDLC engine
does not check to see if the octet length of the received packets exceeds the count loaded into the Receive
HDLC Packet Length (RHPL) register. When this bit is set high, the HDLC engine checks to see if the
octet length of the received packets exceeds the count loaded into the RHPL register. When an incoming
packet exceeds the maximum length, then the packet is aborted and the remainder is discarded. This bit is
ignored if the HDLC channel is set into Transparent mode (RTRANS = 1).
0 = octet length detection disabled
1 = octet length detection enabled
DS3134
Bit 2 & Bit 3 / Receive CRC Selection (RCRC0/RCRC1). These 2 bits are ignored if the HDLC
channel is set into Transparent mode (RTRANS = 1).
RCRC1RCRC0Action0no CRC verification performed116-bit CRC (CCITT/ITU Q.921)032-bit CRC1illegal state
Bit 4 / Receive Invert Data Enable (RID). When this bit is set low, the incoming HDLC packets are not
inverted before processing. When this bit is set high, the HDLC engine inverts all the data (flags,
information fields, and FCS) before processing the data. The data is not re-inverted before passing to the
FIFO.
0 = do not invert data
1 = invert all data (including flags and FCS)
Bit 5 / Receive Bit Flip (RBF). When this bit is set low, the HDLC engine will place the first HDLC bit
received in the lowest bit position of the PCI Bus bytes (i.e. PAD[0] / PAD[8] / PAD[16] / PAD[24]).
When this bit is set high, the HDLC engine will place the first HDLC bit received in the highest bit
position of the PCI Bus bytes (i.e. PAD[7] / PAD[15] / PAD[23] / PAD[31]).
0 = the first HDLC bit received is placed in the lowest bit position of the bytes on the PCI Bus
1 = the first HDLC bit received is placed in the highest bit position of the bytes on the PCI Bus
Bit 6 / Receive CRC Strip Enable (RCS). When this bit is set high, the FCS is not transferred through
to the PCI Bus. When this bit is set low, the HDLC engine will include the two byte FCS (16-bit) or four
byte FCS (32-bit) in the data that it transfers to the PCI Bus. This bit is ignored if the HDLC channel is
set into Transparent mode (RTRANS = 1).
0 = send FCS to the PCI Bus
1 = do not send the FCS to the PCI Bus
Bit 7 / Receive Abort Disable (RABTD). When this bit is set low, the HDLC engine will examine the
incoming data stream for the Abort sequence, which are seven or more consecutive ones. When this bit is
set high, the incoming data stream is not examined for the Abort sequence and if an incoming Abort
sequence is received, no action will be taken. This bit is ignored when the HDLC engine is configured in
the Transparent Mode (RTRANS = 1).
Bit 8 / Receive Zero Destuffing Disable (RZDD). When this bit is set low, the HDLC engine will zero
destuff the incoming data stream. When this bit is set high, the HDLC engine will not zero destuff the
incoming data stream. This bit is ignored when the HDLC engine is configured in the Transparent Mode
(RTRANS = 1).
DS3134
Register Name:RHPL
Register Description:Receive HDLC Maximum Packet Length
Register Address:0410h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0s.
This is a globe control only one per device and it is not one for each individual HDLC channel.
Bits 0 to 15 / Receive HDLC Packet Length (RHPL0 to RHPL15). If the Receive Length Detection
Enable bit is set to one, then the HDLC engine will check the number of received octets in a packet to see
if they exceed the count in this register. If the length is exceeded, then the packet is aborted and the
remainder is discarded. The definition of "octet length" is everything in between the opening and closing
flags which includes the address field, control field, information field, and FCS.
Register Name:THCDIS
Register Description:Transmit HDLC Channel Definition Indirect Select
Register Address:0480h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).
00000000 (00h) = HDLC Channel Number 1 (also used for the Fast HDLC Engine on Port 0)
00000001 (01h) = HDLC Channel Number 2 (also used for the Fast HDLC Engine on Port 1)
00000010 (02h) = HDLC Channel Number 3
11111111 (FFh) = HDLC Channel Number 256
Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal
Transmit HDLC Definition RAM, this bit should be written to a one by the host. This causes the device
to begin obtaining the data from the channel location indicated by the HCID bits. During the read access,
the IAB bit will be set to one. Once the data is ready to be read from the THCD register, the IAB bit will
be set to zero. When the host wishes to write data to the internal Transmit HDLC Definition RAM, this
bit should be written to a zero by the host. This causes the device to take the data that is current present in
the THCD register and write it to the channel location indicated by the HCID bits. When the device has
completed the write, the IAB will be set to zero.
Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only
bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be
read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set
DS3134
Register Name:THCD
Register Description:Transmit HDLC Channel Definition
Register Address:0484h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write.
Bit 0 / Transmit Transparent Enable (TTRANS). When this bit is set low, the HDLC engine will
generate flags and the FCS (if enabled via TCRC0/1) and perform zero stuffing. When this bit is set high,
the HDLC engine does not generate flags or the FCS and does not perform zero stuffing.
0 = transparent mode disabled
1 = transparent mode enabled
Bit 1 / Transmit Interfill Select (TIFS).
0 = the interfill byte is 7Eh (01111110)
1 = the interfill byte is FFh (11111111)
Bit 2 & Bit 3 / Transmit CRC Selection (TCRC0/TCRC1). These 2 bits are ignored if the HDLC
channel is set into Transparent mode (TTRANS = 1).
TCRC1TCRC0Action0no CRC is generated116-bit CRC (CCITT/ITU Q.921)032-bit CRC1illegal state
Bit 4 / Transmit Invert Data Enable (TID). When this bit is set low, the outgoing HDLC packets are
not inverted after being generated. When this bit is set high, the HDLC engine inverts all the data (flags,
information fields, and FCS) after the packet has been generated.
0 = do not invert data
1 = invert all data (including flags and FCS)
Bit 5 / Transmit Bit Flip (TBF). When this bit is set low, the HDLC engine will obtain the first HDLC
bit to be transmitted from the lowest bit position of the PCI Bus bytes (i.e. PAD[0] / PAD[8] / PAD[16] /
PAD[24]). When this bit is set high, the HDLC engine will obtain the first HDLC bit to be transmitted
from the highest bit position of the PCI Bus bytes (i.e. PAD[7] / PAD[15] / PAD[23] / PAD[31]).
0 = the first HDLC bit transmitted is obtained from the lowest bit position of the bytes on the
PCI Bus
1 = the first HDLC bit transmitted is obtained from the highest bit position of the bytes on the
PCI Bus
DS3134
Bit 6 / Transmit Corrupt FCS (TCFCS). When this bit is set low, the HDLC engine will allow the
Frame Checksum Sequence (FCS) to be transmitted as generated. When this bit is set high, the HDLC
engine will invert all the bits of the FCS before transmission occurs. This is useful in debugging and
testing HDLC channels at the system level.
0 = generate FCS normally
1 = invert all FCS bits
Bit 7 / Transmit Abort Enable (TABTE). When this bit is set low, the HDLC engine will perform
normally only sending an Abort sequence (eight ones in a row) when an error occurs in the PCI Block or
the FIFO underflows. When this bit is set high, the HDLC engine will continuously transmit an all ones
pattern (i.e. an Abort sequence). This bit is still active when the HDLC engine is configured in the
Transparent Mode (TTRANS = 1).
Bits 8 to 11/ Transmit Flag Generation Bits 0 to 3 (TFG0/TFG1/TFG2/TFG3). These 4 bits
determine how many flags and interfill bytes will be sent in between consecutive packets.
TFG3TFG2TFG1TFG0Action000share closing and opening flag001closing flag / no interfill bytes / opening flag010closing flag / 1 interfill bytes / opening flag011closing flag / 2 interfill bytes / opening flag100closing flag / 3 interfill bytes / opening flag101closing flag / 4 interfill bytes / opening flag110closing flag / 5 interfill bytes / opening flag111closing flag / 6 interfill bytes / opening flag000closing flag / 7 interfill bytes / opening flag001closing flag / 8 interfill bytes / opening flag010closing flag / 9 interfill bytes / opening flag011closing flag / 10 interfill bytes / opening flag100closing flag / 11 interfill bytes / opening flag101closing flag / 12 interfill bytes / opening flag110closing flag / 13 interfill bytes / opening flag111closing flag / 14 interfill bytes / opening flag
Bit 12 / Transmit Zero Stuffing Disable (TZSD). When this bit is set low, the HDLC engine will
perform zero stuffing on the outgoing data stream. When this bit is set high, the outgoing data stream is
not zero stuffed. This bit is ignored when the HDLC engine is configured in the Transparent Mode
(TTRANS = 1).
DS3134
SECTION 7: FIFO
7.1 GENERAL DESCRIPTION & EXAMPLE
Chateau contains one 16k byte FIFO for the receive path and another 16k byte FIFO for the transmit path.
Both of these FIFOs are organized into Blocks. A Block is defined as four dwords (i.e. 16 bytes). Hence,
each FIFO is made up of 1024 Blocks. See the FIFO example in Figure 7.1A.
The FIFO contains a state machine that is constantly polling the 16 ports to determine if any data is ready
for transfer to/from the FIFO from/to the HDLC engines. The 16 ports are priority decoded with Port 0
getting the highest priority and Port 15 getting the lowest priority. Hence, all of the enabled HDLC
channels on the lower numbered ports are serviced before the higher numbered ports. As long as the
maximum throughput rate of 104 Mbps is not exceeded, the DS3134 has been designed to insure that
there is enough bandwidth in this transfer to prevent any loss of data in between the HDLC Engines and
the FIFO.
The FIFO also controls which HDLC channel the DMA should service to read data out of the FIFO on the
receive side and to write data into the FIFO on the transmit side. Which channel gets the highest priority
from the FIFO is configurable via some control bits in the Master Configuration (MC) register (see
Section 4.2). There are two control bits for the receive side (RFPC0 and RFPC1) and two control bits for
the transmit side (TFPC0 and TFPC1) that will determine the priority algorithm as shown in Table 7.1A.
When a HDLC channel is priority decoded the lower the number of the HDLC channel, the higher the
priority. Hence HDLC channel number 1 always has the highest priority in the priority decoded scheme.
FIFO Priority Algorithm Select Table 7.1A
To maintain maximum flexibility for channel reconfiguration, each Block within the FIFO can be
assigned to any of the 256 HDLC channels. In addition, Blocks are link-listed together to form a chain
whereby each Block points to the next Block in the chain. The minimum size of the link-listed chain is 4
Blocks (64 bytes) and the maximum is the full size of the FIFO which is 1024 Blocks.
To assign a set of Blocks to a particular HDLC channel, the Host must configure the Starting Block
Pointer and the Block Pointer RAM. The Starting Block Pointer assigns a particular HDLC channel to a
set of link-listed Blocks by pointing to one of the Blocks within the chain (it does not matter which Block
in the chain is pointed to). The Block Pointer RAM must be configured for each Block that is being used
within the FIFO. The Block Pointer RAM indicates the next Block in the link-listed chain.
Figure 7.1A shows an example of how to configure the Starting Block Pointer and the Block Pointer
RAM. In this example, only three HDLC channels are being used (channels 2, 6, and 16). The device
DS3134
Starting Block Pointer. The Block Pointer RAM tells the device how to link the eight Blocks together to
form a circular chain.
The Host must set the Water Marks for the receive and transmit paths. The receive path has a High Water
Mark and the transmit path has a Low Water Mark.
FIFO Example Figure 7.1A
CH 1
CH 2
CH 3
CH 4
CH 5
CH 6
CH 7
CH 8
CH 9
CH 10
CH 11
CH 12
CH 13
CH 14
CH 15
CH 16
CH 17
CH 18
CH 19
CH 20
CH 21
CH 255
CH 256
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 112
Block 113
Block 114
Block 115
Block 116
Block 117
Block 118
Block 119
Block 120
Block 121
Block 122
Block 123
Block 124
Block 125
Block 126
Block 127
Block 1022
Block 1023
Block 0
Block 1
Block 2
Block 3
Block 4
Block 5
Block 6
Block 1022
Block 1023
Block 121
Block 122
Block 123
Block 124
Block 125
Block 126
Block 127
Block 112
Block 113
Block 114
Block 115
Block 116
Block 117
Block 118
Block 119
Block 120
1024 Block FIFO
(1 Block = 4 dwords)
Block Pointer
RAM
Starting Block
Pointer
fifobd.drw
HDLC
Channel
Number
DS3134
Receive High Water Mark
The High Water Mark indicates to the device how many Blocks should be written into the receive FIFO
by the HDLC engines before the DMA will begin sending the data to the PCI Bus. Alternatively, in other
words, how full should the FIFO get before it should be emptied by the DMA. When the DMA begins
reading the data from the FIFO, it will read all available data and try to completely empty the FIFO even
if one or more EOF (End Of Frames) is detected. As an example, if four Blocks were link-listed together
and the Host programmed the High Water Mark to three Blocks, then the DMA would read the data out of
the FIFO and transfer it to the PCI Bus after the HDLC engine has written three complete Blocks in
succession into the FIFO and still had one Block left to fill. The DMA would not read the data out of the
FIFO again until another three complete Blocks had been written into the FIFO in succession by the
HDLC engine or until an EOF was detected. In this example of four Blocks being link-listed together, the
High Water Mark could also be set to 1 or 2 but no other values would be allowed. If an incoming packet
does not fill the FIFO enough to reach the High Water Mark before an EOF is detected, the DMA will
still request that the data be sent to the PCI Bus, it will not wait for additional data to be written into the
FIFO by the HDLC engines.
Transmit Low Water Mark
The Low Water Mark indicates to the device how many Blocks should be left in the FIFO before the
DMA should begin getting more data from the PCI Bus. In other words, how empty should the FIFO get
before it should be filled again by the DMA. When the DMA begins reading the data from the PCI Bus, it
will read all available data and try to completely fill the FIFO even if one or more EOF (i.e. HDLC
packets) is detected. As an example, if five Blocks were link-listed together and the Host programmed
the Low Water Mark to two Blocks, then the DMA would read the data from the PCI Bus and transfer it
to the FIFO after the HDLC engine has read three complete Blocks in succession from the FIFO and
hence still had two blocks left before the FIFO was empty. The DMA would not read the data from the
PCI Bus again until another three complete Blocks had been read from the FIFO in succession by the
HDLC engines. In this example of five Blocks being link-listed together, the Low Water Mark could also
be set to any value from 1 to 3 (inclusive) but no other values would be allowed. In another words the
Transmit Low Water Mark can be set to a value of 1 to N – 2, where N = number of blocks are linked
together. When a new packet is written into a completely empty FIFO by the DMA, the HDLC engines
will wait until the FIFO fills beyond the Low Water Mark or until an EOF is seen before reading the data
out of the FIFO.
7.2 FIFO REGISTER DESCRIPTION
Register Name:RFSBPIS
Register Description:Receive FIFO Starting Block Pointer Indirect Select
Register Address:0900h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
DS3134
Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).
00000000 (00h) = HDLC Channel Number 1
11111111 (FFh) = HDLC Channel Number 256
Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to write data to set the internal
Receive Starting Block Pointer, this bit should be written to a zero by the host. This causes the device to
take the data that is currently present in the RFSBP register and write it to the channel location indicated
by the HCID bits. When the device has completed the write, the IAB will be set to zero.
Note: The RFSBP is a write only register. Once this register has been written to and operation started,
DS3134 internal state machine will change the value in this register.
Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only
bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be
read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set
to a one while the write is taking place. It will be set to zero once the write operation has completed.
Register Name:RFSBP
Register Description:Receive FIFO Starting Block Pointer
Register Address:0904h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write.
Bits 0 to 9 / Starting Block Pointer (RSBP0 to RSBP9). These 10 bits determine which of the
1024 blocks within the receive FIFO, the host wants the device to configure as the starting block for a
particular HDLC channel. Any of the blocks within a chain of blocks for a HDLC channel can be
configured as the starting block. When these 10 bits are read, they will report the current Block Pointer
being used to write data into the Receive FIFO from the HDLC Layer 2 engines.
0000000000 (000h) = Use Block 0 as the Starting Block
0111111111 (1FFh) = Use Block 511 as the Starting Block
1111111111 (3FFh) = Use Block 1023 as the Starting Block
DS3134
Register Name:RFBPIS
Register Description:Receive FIFO Block Pointer Indirect Select
Register Address:0910h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 9 / Block ID (BLKID0 to BLKID9).
0000000000 (000h) = Block Number 0
0111111111 (1FFh) = Block Number 511
1111111111 (3FFh) = Block Number 1023
Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal
Receive Block Pointer RAM, this bit should be written to a one by the host. This causes the device to
begin obtaining the data from the block location indicated by the BLKID bits. During the read access, the
IAB bit will be set to one. Once the data is ready to be read from the RFBP register, the IAB bit will be
set to zero. When the host wishes to write data to the internal Receive Block Pointer RAM, this bit
should be written to a zero by the host. This causes the device to take the data that is current present in
the RFBP register and write it to the channel location indicated by the BLKID bits. When the device has
completed the write, the IAB will be set to zero.
Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only
bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be
read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set
to a one while the write is taking place. It will be set to zero once the write operation has completed.
Register Name:RFBP
Register Description:Receive FIFO Block Pointer
Register Address:0914h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write.
Bits 0 to 9 / Block Pointer (RBP0 to RBP9). These 10 bits indicate which of the 1024 blocks is the next
block in the link list chain. A block is not allowed to point to itself.
0000000000 (000h) = Block 0 is the Next Linked Block
0111111111 (1FFh) = Block 511 is the Next Linked Block
1111111111 (3FFh) = Block 1023 is the Next Linked Block
DS3134
Register Description:Receive FIFO High Water Mark Indirect Select
Register Address:0920h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).
00000000 (00h) = HDLC Channel Number 1
11111111 (FFh) = HDLC Channel Number 256
Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal
Receive High Water Mark RAM, this bit should be written to a one by the host. This causes the device to
begin obtaining the data from the channel location indicated by the HCID bits. During the read access,
the IAB bit will be set to one. Once the data is ready to be read from the RFHWM register, the IAB bit
will be set to zero. When the host wishes to write data to the internal Receive High Water Mark RAM,
this bit should be written to a zero by the host. This causes the device to take the data that is currently
present in the RFHWM register and write it to the channel location indicated by the HCID bits. When the
device has completed the write, the IAB will be set to zero.
Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only
bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be
read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set
to a one while the write is taking place. It will be set to zero once the write operation has completed.
Register Name:RFHWM
Register Description:Receive FIFO High Water Mark
Register Address:0924h6543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write.
Bits 0 to 9 / High Water Mark (RHWM0 to RHWM9). These 10 bits indicate the setting of the
Receive High Water Mark. The High Water Mark setting is the number of successive blocks that the
HDLC engine will write to the FIFO before the DMA will send the data to the PCI Bus. The High Water
Mark setting must be between (inclusive) one block and one less than the number of blocks in the link-list
chain for the particular channel involved. For example, if four blocks are linked together, then the High
Water Mark can be set to 1, 2 or 3. In another words the High Water Mark can be set to a value of 1 to N
– 1, where N = number of blocks are linked together. Any other numbers are illegal.
DS3134
0000000010 (002h) = High Water Mark is 2 Blocks
0111111111 (1FFh) = High Water Mark is 511 Blocks
1111111111 (3FFh) = High Water Mark is 1023 Blocks
Register Name:TFSBPIS
Register Description:Transmit FIFO Starting Block Pointer Indirect Select
Register Address:0980h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).
00000000 (00h) = HDLC Channel Number 1
11111111 (FFh) = HDLC Channel Number 256
Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to write data to the internal
Transmit Starting Block Pointer RAM, this bit should be written to a zero by the host. This causes the
device to take the data that is currently present in the TFSBP register and write it to the channel location
indicated by the HCID bits. When the device has completed the write, the IAB will be set to zero.
Note: The TFSBP is a write only register. Once this register has been written to and operation started,
DS3134 internal state machine will change the value in this register.
Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only
bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be
read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set
to a one while the write is taking place. It will be set to zero once the write operation has completed.
Register Name:TFSBP
Register Description:Transmit FIFO Starting Block Pointer
Register Address:0984h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write.
DS3134
Bits 0 to 9 / Starting Block Pointer (TSBP0 to TSBP9). These 10 bits determine which of the 1024
blocks within the transmit FIFO, the host wants the device to configure as the starting block for a
particular HDLC channel. Any of the blocks within a chain of blocks for a HDLC channel can be
configured as the starting block. When these 10 bits are read, they will report the current Block Pointer
being used to read data from the Transmit FIFO by the HDLC Layer 2 engines.
0000000000 (000h) = Use Block 0 as the Starting Block
0111111111 (1FFh) = Use Block 511 as the Starting Block
1111111111 (3FFh) = Use Block 1023 as the Starting Block
Register Name:TFBPIS
Register Description:Transmit FIFO Block Pointer Indirect Select
Register Address:0990h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 9 / Block ID (BLKID0 to BLKID9).
0000000000 (000h) = Block Number 0
0111111111 (1FFh) = Block Number 511
1111111111 (3FFh) = Block Number 1023
Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal
Transmit Block Pointer RAM, this bit should be written to a one by the host. This causes the device to
begin obtaining the data from the block location indicated by the BLKID bits. During the read access, the
IAB bit will be set to one. Once the data is ready to be read from the TFBP register, the IAB bit will be
set to zero. When the host wishes to write data to the internal Transmit Block Pointer RAM, this bit
should be written to a zero by the host. This causes the device to take the data that is currently present in
the TFBP register and write it to the channel location indicated by the BLKID bits. When the device has
completed the write, the IAB will be set to zero.
Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only
bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be
read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set
to a one while the write is taking place. It will be set to zero once the write operation has completed.
DS3134
Register Name:TFBP
Register Description:Transmit FIFO Block Pointer
Register Address:0994h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write.
Bits 0 to 9 / Block Pointer (TBP0 to TBP9). These 10 bits indicate which of the 1024 blocks is the next
block in the link list chain. A block is not allowed to point to itself.
0000000000 (000h) = Block 0 is the Next Linked Block
0111111111 (1FFh) = Block 511 is the Next Linked Block
1111111111 (3FFh) = Block 1023 is the Next Linked Block
Register Name:TFLWMIS
Register Description:Transmit FIFO Low Water Mark Indirect Select
Register Address:09A0h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 7 / HDLC Channel ID (HCID0 to HCID7).
00000000 (00h) = HDLC Channel Number 1
11111111 (FFh) = HDLC Channel Number 256
Bit 14 / Indirect Access Read/Write (IARW). When the host wishes to read data from the internal
Transmit Low Water Mark RAM, this bit should be written to a one by the host. This causes the device
to begin obtaining the data from the channel location indicated by the HCID bits. During the read access,
the IAB bit will be set to one. Once the data is ready to be read from the TFLWM register, the IAB bit
will be set to zero. When the host wishes to write data to the internal Transmit Low Water Mark RAM,
this bit should be written to a zero by the host. This causes the device to take the data that is currently
present in the TFLWM register and write it to the channel location indicated by the HCID bits. When the
device has completed the write, the IAB will be set to zero.
Bit 15 / Indirect Access Busy (IAB). When an indirect read or write access is in progress, this read only
bit will be set to a one. During a read operation, this bit will be set to a one until the data is ready to be
read. It will be set to zero when the data is ready to be read. During a write operation, this bit will be set
to a one while the write is taking place. It will be set to zero once the write operation has completed.
DS3134
Register Name:TFLWM
Register Description:Transmit FIFO Low Water Mark
Register Address:09A4h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write.
Bits 0 to 9 / Low Water Mark (TLWM0 to TLWM9). These 10 bits indicate the setting of the
Transmit Low Water Mark. The Low Water Mark setting is the number of Blocks left in the Transmit
FIFO before the DMA will get more data from the PCI Bus. The Low Water Mark setting must be
between (inclusive) 1 block and one less than the number of blocks in the link list chain for the particular
channel involved. For example, if five blocks are linked together, then the Low Water Mark can be set to
1, 2, or 3. In another words the Low Water Mark can be set at a value of 1 to N – 2, where N = number of
blocks are linked together. Any other numbers are illegal.
0000000000 (000h) = invalid setting
0000000001 (001h) = Low Water Mark is 1 Block
0000000010 (002h) = Low Water Mark is 2 Blocks
0111111111 (1FFh) = Low Water Mark is 511 Blocks
1111111111 (3FFh) = Low Water Mark is 1023 Blocks
DS3134
SECTION 8: DMA
8.0 INTRODUCTION
The DMA block (see Figure 1.1A) handles the transfer of packet data from the FIFO block to the PCI
block and vice versa. Throughout this Section, the terms Host and Descriptor will be used. Host is
defined as the CPU or intelligent controller that sits on the PCI Bus and instructs the device on how to
handle the incoming and outgoing packet data. Descriptor is defined as a pre-formatted message that is
passed from the Host to the DMA block or vice versa to indicate where packet data should be placed or
obtained from.
On power-up, the DMA will be disabled because the RDE and TDE control bits in the Master
Configuration register (see Section 4) will be set to zero. The Host must configure the DMA by writing
to all of the registers listed in Table 8.0A (which includes all 256 channel locations in the Receive and
Transmit Configuration RAMs) then enable the DMA by setting to the RDE and TDE control bits to one.
The structure of the DMA is such that the receive and transmit side descriptor address spaces can be
shared even among multiple chips on the same bus. Via the Master Control (MC) register, the Host will
determine how long the DMA will be allowed to burst onto the PCI bus. The default value is 32 dwords
(128 bytes) but via the RDT0/1 and TDT0/1 control bits, the Host can enable the receive or transmit
DMAs to burst either 64 dwords (256 bytes), 128 dwords (512 bytes), or 256 dwords (1024 bytes).
The receive and transmit Packet Descriptors have almost identical structures (see Sections 8.1.2 and
8.2.2) which provides a minimal amount of Host intervention in store-and-forward applications. In other
words, the receive descriptors created by the receive DMA can be used directly by the transmit DMA.
The receive and transmit portions of the DMA are completely independent and will be discussed
separately.
DS3134
DMA Registers that must be configured by the Host on Power-Up Table 8.0A
DS3134
8.1 RECEIVE SIDE
8.1.1 OVERVIEW
The receive DMA uses a scatter gather technique to write packet data into main memory. The Host will
keep track of and decide where the DMA should place the incoming packet data. There are a set of
descriptors that is handed back and forth between the DMA and the Host. Via these descriptors, the Host
can inform the DMA where to place the packet data and the DMA can tell the Host when the data is ready
to be processed.
The operation of the receive DMA has three main areas as shown in Figures 8.1.1A and 8.1.1B and
Table 8.1.1A. The Host will write to the Free Queue Descriptors informing the DMA where it can place
the incoming packet data. Associated with each free data buffer location is a free Packet Descriptor
where the DMA can write information to inform the Host about the attributes of the packet data (i.e.
status information, number of bytes, etc.) that it will output. To accommodate the various needs of packet
data, the Host can quantize the free data buffer space into two different buffer sizes. The Host will set the
size of the buffers via the Receive Large Buffer Size (RLBS) and the Receive Small Buffer Size (RSBS)
registers.
Register Name:RLBS
Register Description:Receive Large Buffer Size Select
Register Address:0790h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
Bits 0 to 12 / Large Buffer Select Bit (LBS0 to LBS12).
0000000000000 (0000h) = Buffer Size is 0 Bytes
1111111111111 (1FFFh) = Buffer Size is 8191 Bytes
Register Name:RSBS
Register Description:Receive Small Buffer Size Select
Register Address:0794h543210141312111098
Note: Bits that are underlined are read only, all other bits are read-write; default value for all bits is 0.
DS3134
Bits 0 to 12 / Small Buffer Select Bit (SBS0 to SBS12).
0000000000000 (0000h) = Buffer Size is 0 Bytes
1111111111111 (1FFFh) = Buffer Size is 8191 Bytes
On a HDLC channel basis in the Receive DMA Configuration RAM, the Host will instruct the DMA on
how to use the large and small buffers for the incoming packet data on that particular HDLC channel.
The Host has three options (1) only use Large Buffers, (2) only use Small Buffers, and (3) first fill a Small
Buffer then if the incoming packet requires more buffer space, use one or more Large Buffers for the
remainder of the packet. The Host selects which option via the Size field in the Receive Configuration
RAM (see Section 8.1.5). Large Buffers are best used for data intensive, time insensitive packets like
graphics files whereas small buffers are best used for time sensitive information like real-time voice.
Receive DMA Main Operational Areas Table 8.1.1A
NameSectionDescription
Packet
Descriptors
8.1.2A dedicated area of memory that describes the location
and attributes of the packet data.
Free Queue
Descriptors
8.1.3A dedicated area of memory that the Host will write to
inform the DMA where to store incoming packet data.
Done Queue
Descriptors
8.1.4A dedicated area of memory that the DMA will write to
inform the Host that the packet data is ready for
processing.
The Done Queue Descriptors contain information that the DMA wishes to pass to the Host. Via the Done
Queue Descriptors the DMA informs the Host about the incoming packet data and where to find the
Packet Descriptors that it has written into main memory. Each completed Descriptor contains the starting
address of the data buffer where the packet data is stored.
If enabled, the DMA can burst read the Free Queue Descriptors and burst writes the Done Queue
Descriptors. This helps minimize PCI Bus accesses, freeing the PCI Bus up to do more time critical
functions. See Sections 8.1.3 and 8.1.4 for more details on this feature.
DS3134
Receive DMA Actions
A typical scenario for the Receive DMA is as follows:The receive DMA gets a request from the Receive FIFO that it has packet data that needs to be sent to
the PCI Bus.The receive DMA determines whether the incoming packet data should be stored in a large buffer or a
small buffer.The receive DMA then reads a Free Queue Descriptor (either by reading a single descriptor or a burst
of descriptors) indicating where in main memory there exists some free data buffer space and where
the associated free Packet Descriptor resides.The receive DMA starts storing packet data in the previously free buffer data space by writing it out
through the PCI Bus.When the receive DMA realizes that the current data buffer is filled (by knowing the buffer size it can
calculate this), it then reads another Free Queue Descriptor to find another free data buffer and Packet
Descriptor location.The receive DMA then writes the previous Packet Descriptor and creates a linked list by placing the
current descriptor in the Next Descriptor Pointer field and then it starts filling the new buffer location.
Figure 8.1.1A provides an example of Packet Descriptors being link listed together (see Channel 2).This continues to all of the packet data is stored.The receive DMA will either wait until a packet has been completely received or until a
programmable number (from 1 to 7) of data buffers have been filled before writing the Done Queue
Descriptor which indicates to the Host that packet data is ready for processing.
Host Actions
The Host will typically handle the receive DMA as follows:
1. The Host is always trying to make available free data buffer space and hence it tries to fill the Free
Queue Descriptor.
2. The Host will either poll or be interrupted that some incoming packet data is ready for processing.
3. The Host then reads the Done Queue Descriptor circular queue to find out which channel has data
available, what the status is, and where the receive Packet Descriptor is located.
4. The Host then reads the receive Packet Descriptor and begins processing the data.
5. The Host then reads the Next Descriptor Pointer in the link listed chain and continues this process
until either a number (from 1 to 7) of descriptors have been processed or an end of packet has been
reached.
6. The Host then checks the Done Queue Descriptor circular queue to see if any more data buffers are
ready for processing.
DS3134
Receive DMA Operation Figure 8.1.1A00h
08h
10h
Free Queue Descriptors
(circular queue)
00h
04h
08h
Done Queue Descriptors
(circular queue)
0Ch
Free Packet Descriptors & Data Buffers
Used Packet Descriptors & Data Buffers
dmarbd
DS3134
Receive DMA Memory Organization Figure 8.1.1B
Free Queue Base Address (32)
Free Queue End Address (16)
Free Queue Small Buffer Start Address (16)
Free Queue Large Buffer Host Write Pointer (16)
Free Queue Large Buffer DMA Read Pointer (16)
Free Queue Small Buffer DMA Read Pointer (16)
Free Queue Small Buffer Host Write Pointer (16)
Done Queue Base Address (32)
Done Queue End Address (16)
Done Queue DMA Write Pointer (16)
Done Queue Host Read Pointer (16)
Descriptor Base Address (32)
Main Offboard Memory
(32-Bit Address Space)
Internal Chateau Registers
dmarbd

Partno	Mfg	Dc	Qty	Available	Descript
DS3134	DALLAS	N/a	29	avai	CHATEAU