DS3131DK ,Bit-SynchronouS (BoSS) HDLC Controller Demo KitAPPLICATIONS Routers ORDERING INFORMATION xDSL Access Multiplexers (DSLAMs) PART TEMP RANGE PIN-PA ..
DS3134 ,CHATEAUFEATURES• 256 Channel HDLC Controller that Supports • BERT function can be assigned to anyup to 64 ..
DS3141 ,Single/Dual/Triple/Quad DS3/E3 FramersAPPLICATIONS Line, Diagnostic, and Payload Loopbacks SONET/SDH Muxes Externally Controlled Tran ..
DS3141+ ,Single/Dual/Triple/Quad DS3/E3 FramersAPPLICATIONS Line, Diagnostic, and Payload Loopbacks SONET/SDH Muxes Externally Controlled Tran ..
DS31412 ,6-/8-/12-Channel DS3/E3 FramersFUNCTIONAL DESCRIPTION ... 18 7.1 PIN INVERSIONS AND FORCE HIGH/LOW ..... 18 7.2 TRANSMITTER LOGIC ..
DS3146N ,6-/8-/12-Channel DS3/E3 FramersAPPLICATIONS Large Performance-Monitoring Counters SONET/SDH Muxes Line, Diagnostic, and Payloa ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS3131DK
Bit-SynchronouS (BoSS) HDLC Controller Demo Kit
GENERAL DESCRIPTION The DS3131 bit-synchronous (BoSS) HDLC
controller can handle up to 40 channels of high-
speed, unchannelized, bit-synchronous HDLC.
The on-board DMA has been optimized for maximum flexibility and PCI bus efficiency to
minimize host processor intervention in the data
path. Diagnostic loopbacks and an on-board
BERT remove the need for external components.
APPLICATIONS Routers
xDSL Access Multiplexers (DSLAMs)
Clear-Channel (unchannelized) T1/E1 Clear-Channel (unchannelized) T3/E3
SONET/SDH Path Overhead Termination
High-Density V.35 Terminations
High-Speed Links such as HSSI
FEATURES ��40 Timing Independent Ports
��40 Bidirectional HDLC Channels
��Each Port Can Operate Up to 52Mbps
��Up to 132Mbps Full-Duplex Throughput
��On-Board Bit Error-Rate Tester (BERT)
��Diagnostic Loopbacks in Both Directions
��Local Bus Supports PCI Bridging
��33MHz 32-Bit PCI Interface
��Full Suite of Driver Code
ORDERING INFORMATION
FUNCTIONAL DIAGRAM Bit-SynchronouS (BoSS)
HDLC Controller Demo Kit
DS3131DK
TABLE OF CONTENTS
1. GENERAL OVERVIEW.................................................................................................................3 Figure 1-1. PCI Card Configuration.............................................................................................................4
Figure 1-2. Port PLD Schematic...................................................................................................................5
Table 1-A. Header A Definition...................................................................................................................6
Table 1-B. Header B Definition....................................................................................................................7
Table 1-C. Header C Definition....................................................................................................................8
2. SOFTWARE.....................................................................................................................................9 2.1 ARCHITECTURE................................................................................................................................9
Figure 2-1. Software Architecture................................................................................................................9
2.2 INTRODUCTION TO BOSS..................................................................................................................9
2.3 BOSS SOFTWARE GUI INTERFACE AND DESCRIPTION...................................................................11
2.3.1 Main GUI InterfaceConfiguration......................................................................................11
Figure 2-2. Software Main GUI..................................................................................................................11
2.3.2 Show Results...........................................................................................................................15
Figure 2-3. Show Results GUI (Driver Statistics)......................................................................................15
Figure 2-4. Show Results GUI (Application Statistics)..............................................................................16
Figure 2-5. Show Results GUI (BoSS Statistics).......................................................................................17
2.3.3 Memory Viewer.......................................................................................................................18
Figure 2-6. Memory Viewer GUI...............................................................................................................18
2.3.4 Register Access.......................................................................................................................19
Figure 2-7. Registers Access GUI..............................................................................................................19
2.3.5 DMA Configuration................................................................................................................20
Figure 2-8. DMA Configuration GUI.........................................................................................................20
2.4 DRIVER...........................................................................................................................................22
Table 2-A. Low-Level API Source Block Contents...................................................................................22
Figure 2-9. Low-Level API Source Block Relationships...........................................................................23
3. INSTALLATION AND GETTING STARTED..........................................................................24 3.1 CARD INSTALLATION......................................................................................................................24
3.1.1 Windows 95 Systems...............................................................................................................24
3.1.2 Windows 98 Systems...............................................................................................................25
3.1.3 Windows NT Systems..............................................................................................................25
3.2 SOFTWARE INSTALLATION.............................................................................................................26
3.3 OPERATIONAL TEST.......................................................................................................................26
4. PC BOARD LAYOUT...................................................................................................................27
5. APPENDIX A..................................................................................................................................28
DS3131DK
1. GENERAL OVERVIEW The DS3131DK is a demonstration and evaluation kit for the DS3131 BoSS bit-synchronous HDLC
controllers. The DS3131DK is intended to be used in a full-size PC platform, complete with PCI. The DS3131DK operates with a software suite that runs under Microsoft Windows®95/98/NT. The PC
platform must be at least a 200MHz+ Pentium II class CPU with 32MB of RAM. Figure 1-1 details an
outline of the PCI board for the DS3131DK.
The DS3131DK was designed to be as simple as possible but provides the flexibility to be used in a number of different configurations. The DS3131DK has all of the port pins and the local bus pins from
the DS3131 that are easily accessible through headers on top of the card. A second DS3131DK can also
be loaded into the PC in an adjacent PCI slot to add additional functions such as:
��Multiple T1/E1 framers
��T3 line interface
��HSSI interface
��V.35 interfaces An Altera 9000 series PLD device is connected to all of the port pins on the DS3131. The PLD is capable
of being loaded with various configurations through a programming port (J4) that resides on the
DS3131DK. This PLD generates clocks and frame syncs as well as routes data from one port to another
in a daisy-chain fashion to allow testing the device under worst-case loading (Figure 1-2). Two
oscillators provide the port timing.
The transmit side of a port is derived from one clock and the receive side from another, so that they can
be asynchronous to one another. If the PLD is not needed, it can be three-stated to remove it (electrically)
from the board. Signals can then be sent to the DS3131 by the pin headers. The board is intended to be a full-size PCI card that can only be plugged into a 5V PCI system
environment. There is a 256-pin plastic BGA socket on the board for the DS3131.
Only the DS3131 is operated at 3.3V. Since it cannot be guaranteed that a 3.3V supply exists in a 5V PCI
system environment, the DS3131DK has a linear regulator on it (U4: LT1086) to convert from 5V to 3.3V. All of the other logic, including the PLD and oscillators, operate at 5V. If 3.3V exists on the PCI
bus, the linear regulator can be removed and a 0Ω jumper can be installed at R97 (Figure 1-1).
The JTAG pins on the DS3131 are not active on the DS3131DK. Therefore, the JTCLK, JTDI, and JTMS
signals are wired to 3.3V and JTRST is wired low.
The DS3131DK was designed to use the devices 28-port mode rather than the 40-port mode, so the local
bus can be used.
Windows is a registered trademark of Microsoft Corp.
DS3131DK
Figure 1-1. PCI Card Configuration
DS3131DK
Figure 1-2. Port PLD Schematic
Clock/Sync Definitions
Note 1: Switch Open = Off = High (1)
Note 2: Switch Closed = On = Low (0)
DS3131DK
Table 1-A. Header A Definition
DS3131DK
Table 1-B. Header B Definition DS3131DK
Table 1-C. Header C Definition DS3131DK
2. SOFTWARE 2.1 Architecture The DS3131DK software consists of a high-level piece of reference software called BoSS that sits on
top of a driver. This driver itself is composed of two discrete layers. The upper layer of the driver consists
of various blocks of C code that are specific to the DS3131. These blocks contain an assortment of
portable functions designed to serve as a low-level API for the BoSS. At the bottom level of the driver is the commercially available WinDriver, which interfaces with the Windows operating system to the
DS3131DKs PCI hardware.
Figure 2-1. Software Architecture 2.2 Introduction to BoSS The DS3131DK software (BoSS program) is written to run under a PC loaded with a Windows 95/98/NT
operating system using the DS3131DK PCI card. The software includes two partsthe GUI interface
(Figure 2-2) and driver code. It is developed by Visual C++ and using WinDriver to create the driver. The software provides:
��a simple demonstration of the DS3131 with the ability to set the device into a number of
different configurations
��software drivers for the DS3131
��the ability to explore and load new data into the BoSS registers
��a utility to dump the internal BoSS registers to a file and to load BoSS from a file
��user-configurable DMA parameters
The software does not implement all of the functions available in the DS3131. The user controls the software through a main GUI interface, as shown in Figure 2-2. The software implements 28 ports,
coupled with 28 independent bidirectional HDLC channels. However, if a field in the main GUI is shaded
gray, the function is not available.
DS3131DK
HDLC Channel Assignment Table When a test is run, the BoSS transmits data that is looped back to either the same port (if local loopback
is used) or to an adjacent port (if the Altera PLD is used to loop the data). The software checks the receipt
of packets to ensure they are received without error (i.e., the CRC is correct). For each HDLC channel
that is enabled, the software also keeps track of the number of packets sent, number of packets received, number of packets received in error, and a variety of other statistics/counts.
DS3131DK
2.3 BoSS Software GUI Interface and Description
2.3.1 Main GUI InterfaceConfiguration
Figure 2-2. Software Main GUI
DS3131DK
General Configuration ��The 28 ports on BoSS are handled through a set of 28 check boxes. The port numbers box must be
checked to be enabled. If this box is not checked, the software does not configure any of the RP[n]CR
or TP[n]CR registers or any of the RH[n]CR] and TH[n]CR registers for that port.
��As a port is selected, the corresponding ports loopback check box is selected by default. ��All 28 ports and loopback are selected when this button is hit. ��All 28 ports and loopback are cleared (not selected) when this button is hit. ��The 28 ports on the BoSS are handled through a set of 28 check boxes. If the box is checked, then the
software sets the LLBA bit (bit 10) in the RP[n]CR register to a 1, configuring the port in loopback
mode. If this box is not checked, the software clears the LLBA bit. ��All 28 loopback check boxes are cleared when the button is hit. ��The user can input (in hex or decimal number) the desired packet size and packet count through the
Packet Size and Packet Count edit boxes for the test. Both edit boxes default to 0x100 if the user does not input any entry.
DS3131DK
Control Descriptions ��BoSS program sets the BoSS into a default state by issuing a software reset and then writing 0s into
all indirect registers. The software also runs a register diagnostic to ensure it can correctly write and
read all BoSS registers. The address of the buffer, descriptor, and queue are displayed in the message
box when the process is done. If the diagnostic fails, the software creates an error message and
displays it in the message box at the bottom of the main GUI interface. ��BoSS program loads the BoSS registers with the settings in the GUI interface when this button is hit.
Successfully configured port # is displayed in the message box if successful. ��The program transmits and receives packets based on the users selections. Test Done is displayed
in the message box when the test is done. ��The user can stop the test any time. Test stopped by user is displayed in the message box when the
user hits this button. ��This brings up a screen with detailed information about the packet results (Figure 2-3, Figure 2-4, and
Figure 2-5). ��This brings the Physical Memory Viewer screen up (Figure 2-6). The software prompts the user for an
address, then dumps the next 32 dwords to the screen. The user manually cancels the screen. This
button is only active when a test is not being run. ��This brings up the BoSS Registers screen (Figure 2-7) for the user to read from or write into the register by hex number. ��This brings up the DMA Configuration screen (Figure 2-8) for the user to configure the DMA by their
desired values. Otherwise, the software uses default values to configure the DMA. ��The message box at the bottom of the main GUI displays the status of the process.
DS3131DK
File Menu Descriptions DS3131DK
2.3.2 Show Results
Figure 2-3. Show Results GUI (Driver Statistics)
Descriptions of Driver Statistics DS3131DK
Figure 2-4. Show Results GUI (Application Statistics)
Descriptions of Application Statistics DS3131DK
Figure 2-5. Show Results GUI (BoSS Statistics) Descriptions of BoSS Statistics The following seven items are read from receive done-queue descriptor, dword0, bits 2729, reported at
the final status of an incoming packet:
The following four items are read from transmit done-queue descriptor, dword0, bits 2628, reported at the final status of an outgoing packet:
