DS3131 ,40-Port, Unchannelized Bit-Synchronous HDLCAPPLICATIONS Routers ORDERING INFORMATION xDSL Access Multiplexers (DSLAMs) Clear-Channel (unchan ..
DS3131DK ,Bit-SynchronouS (BoSS) HDLC Controller Demo KitAPPLICATIONS Routers ORDERING INFORMATION xDSL Access Multiplexers (DSLAMs) PART TEMP RANGE PIN-PA ..
DS3134 ,CHATEAUFEATURES• 256 Channel HDLC Controller that Supports • BERT function can be assigned to anyup to 64 ..
DS3141 ,Single/Dual/Triple/Quad DS3/E3 FramersAPPLICATIONS Line, Diagnostic, and Payload Loopbacks SONET/SDH Muxes Externally Controlled Tran ..
DS3141+ ,Single/Dual/Triple/Quad DS3/E3 FramersAPPLICATIONS Line, Diagnostic, and Payload Loopbacks SONET/SDH Muxes Externally Controlled Tran ..
DS31412 ,6-/8-/12-Channel DS3/E3 FramersFUNCTIONAL DESCRIPTION ... 18 7.1 PIN INVERSIONS AND FORCE HIGH/LOW ..... 18 7.2 TRANSMITTER LOGIC ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS3131
40-Port, Unchannelized Bit-Synchronous HDLC
GENERAL DESCRIPTION The DS3131 bit-synchronous (BoSS) HDLC controller can handle up to 40 channels of high-
speed, unchannelized, bit-synchronous HDLC.
The on-board DMA has been optimized for
maximum flexibility and PCI bus efficiency to
minimize host processor intervention in the data path. Diagnostic loopbacks and an on-board
BERT remove the need for external components.
APPLICATIONS Routers xDSL Access Multiplexers (DSLAMs)
Clear-Channel (unchannelized) T1/E1
Clear-Channel (unchannelized) T3/E3
SONET/SDH Path Overhead Termination
High-Density V.35 Terminations High-Speed Links such as HSSI
FEATURES ��40 Timing Independent Ports
��40 Bidirectional HDLC Channels
��Each Port Can Operate Up to 52Mbps
��Up to 132Mbps Full-Duplex Throughput
��On-Board Bit Error-Rate Tester (BERT)
��Diagnostic Loopbacks in Both Directions
��Local Bus Supports PCI Bridging
��33MHz 32-Bit PCI Interface
��Full Suite of Driver Code
Features continued on page 6.
ORDERING INFORMATION 0°C to +70°C
FUNCTIONAL DIAGRAM
DS3131 BoSS40-Port, Unchannelized
Bit-Synchronous HDLC
DS3131
TABLE OF CONTENTS 1. MAIN FEATURES..........................................................................................................................6
2. DETAILED DESCRIPTION..........................................................................................................7
3. SIGNAL DESCRIPTION..............................................................................................................14 3.1 OVERVIEW/SIGNAL LIST..........................................................................................................................14 3.2 SERIAL PORT INTERFACE SIGNAL DESCRIPTION.....................................................................................20
3.3 LOCAL BUS SIGNAL DESCRIPTION..........................................................................................................20
3.4 JTAG SIGNAL DESCRIPTION...................................................................................................................23 3.5 PCI BUS SIGNAL DESCRIPTION...............................................................................................................24
3.6 PCI EXTENSION SIGNALS........................................................................................................................26 3.7 SUPPLY AND TEST SIGNAL DESCRIPTION................................................................................................27
4. MEMORY MAP............................................................................................................................28 4.1 INTRODUCTION........................................................................................................................................28
4.2 GENERAL CONFIGURATION REGISTERS (0XX)........................................................................................28 4.3 RECEIVE PORT REGISTERS (1XX)............................................................................................................29
4.4 TRANSMIT PORT REGISTERS (2XX)..........................................................................................................30
4.5 RECEIVE HDLC CONTROL REGISTERS (3XX).........................................................................................31 4.6 TRANSMIT HDLC CONTROL REGISTERS (4XX).......................................................................................32
4.7 BERT REGISTERS (5XX)..........................................................................................................................33 4.8 RECEIVE DMA REGISTERS (7XX)............................................................................................................33
4.9 TRANSMIT DMA REGISTERS (8XX).........................................................................................................34
4.10 FIFO REGISTERS (9XX)...........................................................................................................................34 4.11 PCI CONFIGURATION REGISTERS FOR FUNCTION 0 (PIDSEL/AXX)......................................................35
4.12 PCI CONFIGURATION REGISTERS FOR FUNCTION 1 (PIDSEL/BXX).......................................................35
5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT...............................36 5.1 MASTER RESET AND ID REGISTER DESCRIPTION...................................................................................36
5.2 MASTER CONFIGURATION REGISTER DESCRIPTION................................................................................37
5.3 STATUS AND INTERRUPT.........................................................................................................................39 5.3.1 General Description of Operation......................................................................................................39
5.3.2 Status and Interrupt Register Description...........................................................................................41
5.4 TEST REGISTER DESCRIPTION.................................................................................................................46
6. LAYER 1.........................................................................................................................................47 6.1 GENERAL DESCRIPTION...........................................................................................................................47
6.2 PORT REGISTER DESCRIPTIONS...............................................................................................................49 6.3 BERT.......................................................................................................................................................51
6.4 BERT REGISTER DESCRIPTION...............................................................................................................52
7. HDLC..............................................................................................................................................59 7.1 GENERAL DESCRIPTION...........................................................................................................................59 7.2 HDLC OPERATION..................................................................................................................................59
7.3 BIT-SYNCHRONOUS HDLC REGISTER DESCRIPTION..............................................................................61
8. FIFO................................................................................................................................................65 8.1 GENERAL DESCRIPTION AND EXAMPLE..................................................................................................65
8.1.1 Receive High Watermark....................................................................................................................67
8.1.2 Transmit Low Watermark....................................................................................................................67 8.2 FIFO REGISTER DESCRIPTION.................................................................................................................68
9. DMA................................................................................................................................................74 9.1 INTRODUCTION........................................................................................................................................74 9.2 RECEIVE SIDE..........................................................................................................................................76
DS3131
9.2.4 Done Queue.........................................................................................................................................87
9.2.5 DMA Configuration RAM...................................................................................................................93 9.3 TRANSMIT SIDE........................................................................................................................................97
9.3.1 Overview.............................................................................................................................................97
9.3.2 Packet Descriptors............................................................................................................................105 9.3.3 Pending Queue..................................................................................................................................107
9.3.4 Done Queue.......................................................................................................................................111 9.3.5 DMA Configuration RAM.................................................................................................................116
10. PCI BUS........................................................................................................................................121 10.1 GENERAL DESCRIPTION OF OPERATION................................................................................................121
10.1.1 PCI Read Cycle.................................................................................................................................122 10.1.2 PCI Write Cycle................................................................................................................................123
10.1.3 PCI Bus Arbitration..........................................................................................................................124
10.1.4 PCI Initiator Abort............................................................................................................................124 10.1.5 PCI Target Retry...............................................................................................................................125
10.1.6 PCI Target Disconnect......................................................................................................................125 10.1.7 PCI Target Abort...............................................................................................................................126
10.1.8 PCI Fast Back-to-Back......................................................................................................................127
10.2 PCI CONFIGURATION REGISTER DESCRIPTION.....................................................................................128 10.2.1 Command Bits...................................................................................................................................129
10.2.2 Status Bits..........................................................................................................................................130
10.2.3 Command Bits...................................................................................................................................134 10.2.4 Status Bits..........................................................................................................................................135
11. LOCAL BUS.................................................................................................................................138 11.1 GENERAL DESCRIPTION.........................................................................................................................138
11.1.1 PCI Bridge Mode..............................................................................................................................141 11.1.2 Configuration Mode..........................................................................................................................143
11.2 LOCAL BUS BRIDGE MODE CONTROL REGISTER DESCRIPTION............................................................145 11.3 EXAMPLES OF BUS TIMING FOR LOCAL BUS PCI BRIDGE MODE OPERATION.....................................147
12. JTAG.............................................................................................................................................155 12.1 JTAG DESCRIPTION...............................................................................................................................155
12.2 TAP CONTROLLER STATE MACHINE DESCRIPTION..............................................................................156 12.3 INSTRUCTION REGISTER AND INSTRUCTIONS........................................................................................159
12.4 TEST REGISTERS....................................................................................................................................160
13. AC CHARACTERISTICS..........................................................................................................161 14. MECHANICAL DIMENSIONS.................................................................................................169 14.1 272 PBGA PACKAGE.............................................................................................................................169
15. APPLICATIONS.........................................................................................................................170 15.1 T1/E1 AND T3/E3 APPLICATIONS..........................................................................................................170
15.2 DSL AND CABLE MODEM APPLICATIONS.............................................................................................173
15.3 SONET/SDH APPLICATIONS................................................................................................................174
DS3131
LIST OF FIGURES Figure 2-1. Block Diagram........................................................................................................................10
Figure 2-2. Configuration Options.............................................................................................................11
Figure 3-1. Signal Floorplan......................................................................................................................19
Figure 5-1. Status Register Block Diagram for SM...................................................................................40
Figure 6-1. Layer 1 Port Interface Block Diagram....................................................................................48 Figure 6-2. BERT Mux Diagram...............................................................................................................51
Figure 6-3. BERT Register Set..................................................................................................................52
Figure 8-1. FIFO Example.........................................................................................................................66
Figure 9-1. Receive DMA Operation.........................................................................................................78
Figure 9-2. Receive DMA Memory Organization.....................................................................................79 Figure 9-3. Receive Descriptor Example...................................................................................................80
Figure 9-4. Receive Packet Descriptors.....................................................................................................81
Figure 9-5. Receive Free-Queue Descriptor..............................................................................................82
Figure 9-6. Receive Free-Queue Structure................................................................................................84
Figure 9-7. Receive Done-Queue Descriptor.............................................................................................87 Figure 9-8. Receive Done-Queue Structure...............................................................................................89
Figure 9-9. Receive DMA Configuration RAM........................................................................................93
Figure 9-10. Transmit DMA Operation.....................................................................................................99
Figure 9-11. Transmit DMA Memory Organization...............................................................................100
Figure 9-12. Transmit DMA Packet Handling.........................................................................................101 Figure 9-13. Transmit DMA Priority Packet Handling...........................................................................102
Figure 9-14. Transmit DMA Error Recovery Algorithm.........................................................................104
Figure 9-15. Transmit Descriptor Example.............................................................................................105
Figure 9-16. Transmit Packet Descriptors...............................................................................................106
Figure 9-17. Transmit Pending-Queue Descriptor...................................................................................107 Figure 9-18. Transmit Pending-Queue Structure.....................................................................................109
Figure 9-19. Transmit Done-Queue Descriptor.......................................................................................111
Figure 9-20. Transmit Done-Queue Structure.........................................................................................113
Figure 9-21. Transmit DMA Configuration RAM...................................................................................116
Figure 10-1. PCI Configuration Memory Map........................................................................................121 Figure 10-2. PCI Bus Read......................................................................................................................122
Figure 10-3. PCI Bus Write.....................................................................................................................123
Figure 10-4. PCI Bus Arbitration Signaling Protocol..............................................................................124
Figure 10-5. PCI Initiator Abort..............................................................................................................124
Figure 10-6. PCI Target Retry.................................................................................................................125 Figure 10-7. PCI Target Disconnect........................................................................................................125
Figure 10-8. PCI Target Abort.................................................................................................................126
Figure 10-9. PCI Fast Back-to-Back........................................................................................................127
Figure 11-1. Bridge Mode........................................................................................................................139
Figure 11-2. Bridge Mode with Arbitration Enabled...............................................................................139 Figure 11-3. Configuration Mode............................................................................................................140
Figure 11-4. Local Bus Access Flowchart...............................................................................................144
Figure 11-5. 8-Bit Read Cycle.................................................................................................................147
Figure 11-6. 16-Bit Write Cycle..............................................................................................................148
DS3131
Figure 11-9. 8-Bit Read Cycle.................................................................................................................151
Figure 11-10. 8-Bit Write Cycle..............................................................................................................152 Figure 11-11. 16-Bit Read Cycle.............................................................................................................153
Figure 11-12. 8-Bit Write Cycle..............................................................................................................154
Figure 12-1. Block Diagram....................................................................................................................155
Figure 12-2. TAP Controller State Machine............................................................................................156
Figure 13-1. Layer 1 Port AC Timing Diagram.......................................................................................162 Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram..................................................163
Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams.....................................165
Figure 13-4. PCI Bus Interface AC Timing Diagram..............................................................................167
Figure 13-5. JTAG Test Port Interface AC Timing Diagram..................................................................168
Figure 15-1. 28 T1 Lines Demuxed from a T3 Line................................................................................170 Figure 15-2. Multiport T1 or E1 Application..........................................................................................171
Figure 15-3. Unchannelized T3 or E3 Application..................................................................................172
Figure 15-4. DSLAM/Cable Modem Application...................................................................................173
Figure 15-5. SONET/SDH Overhead Termination Application..............................................................174
LIST OF TABLES Table 1-A. Data Sheet Definitions...............................................................................................................7 Table 2-A. Restrictions..............................................................................................................................12
Table 2-B. Initialization Steps...................................................................................................................13
Table 2-C. Indirect Registers.....................................................................................................................13
Table 3-A. Signal Description...................................................................................................................14
Table 4-A. Memory Map Organization.....................................................................................................28 Table 6-A. HDLC Channel Assignment....................................................................................................47
Table 6-B. Port Configuration Options......................................................................................................47
Table 7-A. HDLC Channel Assignment....................................................................................................59
Table 7-B. Receive Bit-Synchronous HDLC Packet Processing Outcomes.............................................60
Table 7-C. Receive Bit-Synchronous HDLC Functions............................................................................60 Table 7-D. Transmit Bit-Synchronous HDLC Functions..........................................................................61
Table 8-A. FIFO Priority Algorithm Select...............................................................................................65
Table 9-A. DMA Registers to be Configured by the Host on Power-Up..................................................75
Table 9-B. Receive DMA Main Operational Areas...................................................................................77
Table 9-C. Receive Descriptor Address Storage.......................................................................................80 Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation................................83
Table 9-E. Receive Free-Queue Internal Address Storage........................................................................83
Table 9-F. Receive Done-Queue Internal Address Storage.......................................................................88
Table 9-G. Transmit DMA Main Operational Areas.................................................................................97
Table 9-H. Done-Queue Error-Status Conditions....................................................................................103 Table 9-I. Transmit Descriptor Address Storage.....................................................................................105
Table 9-J. Transmit Pending-Queue Internal Address Storage................................................................108
Table 9-K. Transmit Done-Queue Internal Address Storage...................................................................112
Table 11-A. Local Bus Signals (LBPXS Floating or Connected High)..................................................138
Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting..................................................................141
Table 11-C. Local Bus 16-Bit Width Address, LD, LBHE Setting.........................................................142 Table 12-A. Instruction Codes.................................................................................................................159
