DS31256+ ,256-Channel, High-Throughput HDLC ControllerFEATURES6 2. DETAILED DESCRIPTION....7 3. SIGNAL DESCRIPTION ......13 3.1 OVERVIEW/SIGNAL LIST.13 3 ..
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DS31256+
256-Channel, High-Throughput HDLC Controller
GENERAL DESCRIPTION The DS31256 Envoy is a 256-channel HDLC
controller that can handle up to 60 T1 or 64 E1
data streams or two T3 data streams. Each of the
16 physical ports can handle one, two, or four
T1 or E1 data streams. The DS31256 is
composed of the following blocks: Layer 1,
HDLC processing, FIFO, DMA, PCI bus, and
local bus.
There are 16 HDLC engines (one for each port)
that are each capable of operating at speeds up
to 8.192Mbps in channelized mode and up to
10Mbps in unchannelized mode. The DS31256
Envoy also has three fast HDLC engines that
only reside on Ports 0, 1, and 2. They are
capable of operating at speeds up to 52Mbps.
APPLICATIONS Channelized and Clear-Channel
(Unchannelized) T1/E1 and T3/E3
Routers with Multilink PPP Support
High-Density Frame-Relay Access
xDSL Access Multiplexers (DSLAMs)
Triple HSSI
High-Density V.35
SONET/SDH EOC/ECC Termination
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS31256 0°C to +70°C 256 PBGA
DS31256+ 0°C to +70°C 256 PBGA
+Denotes lead-free/RoHS-compliant package.
FEATURES � 256 Independent, Bidirectional HDLC
Channels � Up to 132Mbps Full-Duplex Throughput � Supports Up to 60 T1 or 64 E1 Data Streams � 16 Physical Ports (16 Tx and 16 Rx) That
Can Be Independently Configured for
Channelized or Unchannelized Operation � Three Fast (52Mbps) Ports; Other Ports
Capable of Speeds Up to 10Mbps
(Unchannelized) � Channelized Ports Can Each Handle One,
Two, or Four T1 or E1 Lines � Per-Channel DS0 Loopbacks in Both
Directions � Over-Subscription at the Port Level � Transparent Mode Supported � On-Board Bit Error-Rate Tester (BERT)
with Automatic Error Insertion Capability � BERT Function Can Be Assigned to Any
HDLC Channel or Any Port � Large 16kB FIFO in Both Receive and
Transmit Directions � Efficient Scatter/Gather DMA Maximizes
Memory Efficiency � Receive Data Packets are Time-Stamped � Transmit Packet Priority Setting � V.54 Loopback Code Detector � Local Bus Allows for PCI Bridging or Local
Access � Intel or Motorola Bus Signals Supported � Backward Compatibility with DS3134 � 33MHz 32-Bit PCI (V2.1) Interface � 3.3V Low-Power CMOS with 5V Tolerant
I/O � JTAG Support IEEE 1149.1 � 256-Pin Plastic BGA (27mm x 27mm)
Features continued on page 6.
DS31256
256-Channel, High-Throughput
HDLC Controller
DEMO KIT AVAILABLE
DS31256 256-Channel, High-Throughput HDLC Controller
TABLE OF CONTENTS
1. MAIN FEATURES............................................................................................................6
2. DETAILED DESCRIPTION..............................................................................................7
3. SIGNAL DESCRIPTION................................................................................................13 3.1 OVERVIEW/SIGNAL LIST.............................................................................................................13
3.2 SERIAL PORT INTERFACE SIGNAL DESCRIPTION..........................................................................18
3.3 LOCAL BUS SIGNAL DESCRIPTION..............................................................................................19
3.4 JTAG SIGNAL DESCRIPTION......................................................................................................22
3.5 PCI BUS SIGNAL DESCRIPTION..................................................................................................22
3.6 PCI EXTENSION SIGNALS...........................................................................................................25
3.7 SUPPLY AND TEST SIGNAL DESCRIPTION....................................................................................25
4. MEMORY MAP..............................................................................................................26 4.1 INTRODUCTION..........................................................................................................................26
4.2 GENERAL CONFIGURATION REGISTERS (0XX).............................................................................26
4.3 RECEIVE PORT REGISTERS (1XX)...............................................................................................27
4.4 TRANSMIT PORT REGISTERS (2XX).............................................................................................27
4.5 CHANNELIZED PORT REGISTERS (3XX).......................................................................................28
4.6 HDLC REGISTERS (4XX)............................................................................................................29
4.7 BERT REGISTERS (5XX)............................................................................................................29
4.8 RECEIVE DMA REGISTERS (7XX)...............................................................................................29
4.9 TRANSMIT DMA REGISTERS (8XX).............................................................................................30
4.10 FIFO REGISTERS (9XX).............................................................................................................30
4.11 PCI CONFIGURATION REGISTERS FOR FUNCTION 0 (PIDSEL/AXX).............................................31
4.12 PCI CONFIGURATION REGISTERS FOR FUNCTION 1 (PIDSEL/BXX).............................................31
5. GENERAL DEVICE CONFIGURATION AND STATUS/INTERRUPT...........................32 5.1 MASTER RESET AND ID REGISTER DESCRIPTION........................................................................32
5.2 MASTER CONFIGURATION REGISTER DESCRIPTION....................................................................32
5.3 STATUS AND INTERRUPT............................................................................................................34
5.3.1 General Description of Operation.......................................................................................................34
5.3.2 Status and Interrupt Register Description...........................................................................................37
5.4 TEST REGISTER DESCRIPTION...................................................................................................43
6. LAYER 1........................................................................................................................44 6.1 GENERAL DESCRIPTION.............................................................................................................44
6.2 PORT REGISTER DESCRIPTIONS.................................................................................................48
6.3 LAYER 1 CONFIGURATION REGISTER DESCRIPTION....................................................................51
6.4 RECEIVE V.54 DETECTOR..........................................................................................................56
6.5 BERT.......................................................................................................................................60
6.6 BERT REGISTER DESCRIPTION.................................................................................................61
7. HDLC.............................................................................................................................67 7.1 GENERAL DESCRIPTION.............................................................................................................67
7.2 HDLC REGISTER DESCRIPTION.................................................................................................69
8. FIFO...............................................................................................................................74 8.1 GENERAL DESCRIPTION AND EXAMPLE.......................................................................................74
8.1.1 Receive High Watermark....................................................................................................................76
8.1.2 Transmit Low Watermark....................................................................................................................76
8.2 FIFO REGISTER DESCRIPTION...................................................................................................76
9. DMA...............................................................................................................................83 9.1 INTRODUCTION..........................................................................................................................83
9.2 RECEIVE SIDE...........................................................................................................................85
9.2.1 Overview.............................................................................................................................................85
9.2.2 Packet Descriptors..............................................................................................................................90
DS31256 256-Channel, High-Throughput HDLC Controller
9.2.5 DMA Channel Configuration RAM....................................................................................................102
9.3 TRANSMIT SIDE.......................................................................................................................105
9.3.1 Overview...........................................................................................................................................105
9.3.2 Packet Descriptors............................................................................................................................114
9.3.3 Pending Queue.................................................................................................................................116
9.3.4 Done Queue......................................................................................................................................120
9.3.5 DMA Configuration RAM...................................................................................................................125
10. PCI BUS.......................................................................................................................130 10.1 GENERAL DESCRIPTION OF OPERATION...................................................................................130
10.1.1 PCI Read Cycle.................................................................................................................................131
10.1.2 PCI Write Cycle.................................................................................................................................132
10.1.3 PCI Bus Arbitration............................................................................................................................133
10.1.4 PCI Initiator Abort..............................................................................................................................133
10.1.5 PCI Target Retry...............................................................................................................................134
10.1.6 PCI Target Disconnect......................................................................................................................134
10.1.7 PCI Target Abort...............................................................................................................................135
10.1.8 PCI Fast Back-to-Back......................................................................................................................136
10.2 PCI CONFIGURATION REGISTER DESCRIPTION.........................................................................137
10.2.1 Command Bits (PCMD0)...................................................................................................................138
10.2.2 Status Bits (PCMD0).........................................................................................................................139
10.2.3 Command Bits (PCMD1)...................................................................................................................143
10.2.4 Status Bits (PCMD1).........................................................................................................................144
11. LOCAL BUS................................................................................................................147 11.1 GENERAL DESCRIPTION...........................................................................................................147
11.1.1 PCI Bridge Mode...............................................................................................................................149
11.1.2 Configuration Mode...........................................................................................................................151
11.2 LOCAL BUS BRIDGE MODE CONTROL REGISTER DESCRIPTION..................................................153
11.3 EXAMPLES OF BUS TIMING FOR LOCAL BUS PCI BRIDGE MODE OPERATION.............................155
12. JTAG............................................................................................................................163 12.1 JTAG DESCRIPTION................................................................................................................163
12.2 TAP CONTROLLER STATE MACHINE DESCRIPTION...................................................................164
12.3 INSTRUCTION REGISTER AND INSTRUCTIONS............................................................................166
12.4 TEST REGISTERS.....................................................................................................................167
13. AC CHARACTERISTICS.............................................................................................168
14. REVISION HISTORY...................................................................................................176
15. PACKAGE INFORMATION.........................................................................................177 15.1 256-PIN PBGA (27MM X 27MM)...............................................................................................177
16. THERMAL CHARACTERISTICS.................................................................................178
17. APPLICATIONS...........................................................................................................179 17.1 16 PORT T1 OR E1 WITH 256 HDLC CHANNEL SUPPORT.........................................................180
17.2 DUAL T3 WITH 256 HDLC CHANNEL SUPPORT........................................................................181
17.3 SINGLE T3 WITH 512 HDLC CHANNEL SUPPORT......................................................................182
17.4 SINGLE T3 WITH 672 HDLC CHANNEL SUPPORT......................................................................183
DS31256 256-Channel, High-Throughput HDLC Controller
LIST OF FIGURES Figure 2-1. Block Diagram.......................................................................................................................10
Figure 5-1. Status Register Block Diagram for SM and SV54.................................................................36
Figure 6-1. Layer 1 Block Diagram..........................................................................................................46
Figure 6-2. Port Timing (Channelized and Unchannelized Applications)................................................47
Figure 6-3. Layer 1 Register Set.............................................................................................................51
Figure 6-4. Port RAM Indirect Access.....................................................................................................53
Figure 6-5. Receive V.54 Host Algorithm................................................................................................58
Figure 6-6. Receive V.54 State Machine.................................................................................................59
Figure 6-7. BERT Mux Diagram..............................................................................................................60
Figure 6-8. BERT Register Set................................................................................................................61
Figure 8-1. FIFO Example.......................................................................................................................75
Figure 9-1. Receive DMA Operation........................................................................................................88
Figure 9-2. Receive DMA Memory Organization.....................................................................................89
Figure 9-3. Receive Descriptor Example.................................................................................................90
Figure 9-4. Receive Packet Descriptors..................................................................................................91
Figure 9-5. Receive Free-Queue Descriptor............................................................................................92
Figure 9-6. Receive Free-Queue Structure.............................................................................................94
Figure 9-7. Receive Done-Queue Descriptor..........................................................................................97
Figure 9-8. Receive Done-Queue Structure............................................................................................99
Figure 9-9. Receive DMA Configuration RAM.......................................................................................102
Figure 9-10. Transmit DMA Operation...................................................................................................108
Figure 9-11. Transmit DMA Memory Organization................................................................................109
Figure 9-12. Transmit DMA Packet Handling........................................................................................110
Figure 9-13. Transmit DMA Priority Packet Handling............................................................................111
Figure 9-14. Transmit DMA Error Recovery Algorithm..........................................................................113
Figure 9-15. Transmit Descriptor Example............................................................................................114
Figure 9-16. Transmit Packet Descriptors.............................................................................................115
Figure 9-17. Transmit Pending-Queue Descriptor.................................................................................116
Figure 9-18. Transmit Pending-Queue Structure...................................................................................118
Figure 9-19. Transmit Done-Queue Descriptor.....................................................................................120
Figure 9-20. Transmit Done-Queue Structure.......................................................................................122
Figure 9-21. Transmit DMA Configuration RAM....................................................................................125
Figure 10-1. PCI Configuration Memory Map........................................................................................130
Figure 10-2. PCI Bus Read...................................................................................................................131
Figure 10-3. PCI Bus Write....................................................................................................................132
Figure 10-4. PCI Bus Arbitration Signaling Protocol..............................................................................133
Figure 10-5. PCI Initiator Abort..............................................................................................................133
Figure 10-6. PCI Target Retry...............................................................................................................134
Figure 10-7. PCI Target Disconnect......................................................................................................134
Figure 10-8. PCI Target Abort...............................................................................................................135
Figure 10-9. PCI Fast Back-To-Back.....................................................................................................136
Figure 11-1. Bridge Mode......................................................................................................................148
Figure 11-2. Bridge Mode with Arbitration Enabled...............................................................................148
Figure 11-3. Configuration Mode...........................................................................................................149
Figure 11-4. Local Bus Access Flowchart.............................................................................................152
Figure 11-5. 8-Bit Read Cycle...............................................................................................................155
Figure 11-6. 16-Bit Write Cycle..............................................................................................................156
Figure 11-7. 8-Bit Read Cycle...............................................................................................................157
Figure 11-8. 16-Bit Write (Only Upper 8 Bits Active) Cycle...................................................................158
DS31256 256-Channel, High-Throughput HDLC Controller
Figure 11-12. 8-Bit Write Cycle..............................................................................................................162
Figure 12-1. Block Diagram...................................................................................................................163
Figure 12-2. TAP Controller State Machine...........................................................................................164
Figure 13-1. Layer 1 Port AC Timing Diagram......................................................................................169
Figure 13-2. Local Bus Bridge Mode (LMS = 0) AC Timing Diagram....................................................170
Figure 13-3. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams.......................................172
Figure 13-4. Local Bus Configuration Mode (LMS = 1) AC Timing Diagrams (continued)....................173
Figure 13-5. PCI Bus Interface AC Timing Diagram..............................................................................174
Figure 13-6. JTAG Test Port Interface AC Timing Diagram..................................................................175
Figure 16-1. 27mm x 27mm PBGA with 256 Balls, 2oz Planes, +70°C Ambient, Under Natural
Convection at 3.0W.........................................................................................................................178
Figure 17-1. Application Drawing Key...................................................................................................179
Figure 17-2. Single T1/E1 Line Connection...........................................................................................179
Figure 17-3. Quad T1/E1 Connection....................................................................................................180
Figure 17-4. 16-Port T1 Application.......................................................................................................180
Figure 17-5. Dual T3 Application...........................................................................................................181
Figure 17-6. T3 Application (512 HDLC Channels)...............................................................................182
Figure 17-7. T3 Application (672 HDLC Channels)...............................................................................183
LIST OF TABLES Table 1-A. Data Sheet Definitions.............................................................................................................7
Table 2-A. Restrictions............................................................................................................................11
Table 2-B. Initialization Steps..................................................................................................................12
Table 2-C. Indirect Registers...................................................................................................................12
Table 3-A. Signal Description..................................................................................................................13
Table 3-B. RS Sampled Edge.................................................................................................................18
Table 3-C. TS Sampled Edge..................................................................................................................19
Table 4-A. Memory Map Organization.....................................................................................................26
Table 6-A. Channelized Port Modes........................................................................................................44
Table 6-B. Receive V.54 Search Routine................................................................................................57
Table 7-A. Receive HDLC Packet Processing Outcomes.......................................................................67
Table 7-B. Receive HDLC Functions.......................................................................................................68
Table 7-C. Transmit HDLC Functions.....................................................................................................68
Table 8-A. FIFO Priority Algorithm Select...............................................................................................74
Table 9-A. DMA Registers to be Configured by the Host on Power-Up..................................................84
Table 9-B. Receive DMA Main Operational Areas..................................................................................86
Table 9-C. Receive Descriptor Address Storage.....................................................................................90
Table 9-D. Receive Free-Queue Read/Write Pointer Absolute Address Calculation..............................93
Table 9-E. Receive Free-Queue Internal Address Storage.....................................................................93
Table 9-F. Receive Done-Queue Internal Address Storage....................................................................98
Table 9-G. Transmit DMA Main Operational Areas...............................................................................106
Table 9-H. Done-Queue Error-Status Conditions..................................................................................112
Table 9-I. Transmit Descriptor Address Storage...................................................................................114
Table 9-J. Transmit Pending-Queue Internal Address Storage.............................................................117
Table 9-K. Transmit Done-Queue Internal Address Storage.................................................................121
Table 11-A. Local Bus Signals..............................................................................................................147
Table 11-B. Local Bus 8-Bit Width Address, LBHE Setting...................................................................150
Table 11-C. Local Bus 16-Bit Width Address, LD, LBHE Setting..........................................................150
Table 12-A. Instruction Codes...............................................................................................................166
Table 16-A. Thermal Properties, Natural Convection............................................................................178
