DS3112N ,TEMPE T3/E3 Multiplexer 3.3V T3/E3 Framer and M13/E13/G.747 MuxAPPLICATIONS § Integrated FEAC controller § Wide Area Network Access Equipment § Integrated BERT su ..
DS3112N+ ,TEMPE T3 E3 Multiplexer, 3.3V T3/E3 Framer and M13/E13/G.747 MUXFEATURES FUNCTIONAL DIAGRAM Operates as M13 or E13 Multiplexer or as Stand-Alone T3 or E3 Framer ..
DS3112RD ,DS3/E3 Multiplexer Reference DesignFEATURES The DS3112RD is a reference design for the DS3112 Soldered DS3150 and DS3112 DS3/E3 fra ..
DS31256 ,256-Channel, High-Throughput HDLC ControllerFEATURES The DS31256 Envoy is a 256-channel HDLC 256 Independent, Bidirectional HDLC controller th ..
DS31256+ ,256-Channel, High-Throughput HDLC ControllerFEATURES6 2. DETAILED DESCRIPTION....7 3. SIGNAL DESCRIPTION ......13 3.1 OVERVIEW/SIGNAL LIST.13 3 ..
DS3131 ,40-Port, Unchannelized Bit-Synchronous HDLCAPPLICATIONS Routers ORDERING INFORMATION xDSL Access Multiplexers (DSLAMs) Clear-Channel (unchan ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS3112N
TEMPE T3/E3 Multiplexer 3.3V T3/E3 Framer and M13/E13/G.747 Mux
FEATURES § Operates as M13 or E13 multiplexer or as standalone T3 or E3 framer
§ Flexible multiplexer can be programmed for multiple configurations including:
- M13 multiplexing (28 T1 lines into a T3 data
stream) - E13 multiplexing (16 E1 lines into an E3 data
stream) - E1 to T3 multiplexing (21 E1 lines into a T3
data stream) § Two T1/E1 drop and insert ports
§ Supports T3 C-bit parity mode
§ B3ZS/HDB3 encoder and decoder
§ Generates and detects T3/E3 alarms
§ Generates and detects T2/E2 alarms § Integrated HDLC controller handles LAPD
messages without host intervention
§ Integrated FEAC controller
§ Integrated BERT supports performance
monitoring § T3/E3 and T1/E1 diagnostic (Tx to Rx), line
(Rx to Tx), and payload loopback supported
§ Nonmultiplexed or multiplexed 16-bit control
port (with optional 8-bit mode)
§ 3.3V supply with 5V tolerant I/O § Available in 256-pin 1.27mm pitch BGA
package
§ IEEE 1149.1 JTAG support
FUNCTIONAL DIAGRAM
APPLICATIONS § Wide Area Network Access Equipment
§ PBXs
§ Access Concentrators
§ Digital Cross-Connect Systems § Switches
§ Routers
§ Optical Multiplexers
§ ADMs
§ Test Equipment
ORDERING INFORMATION PIN-PACKAGE 256 BGA
DS3112
TABLE OF CONTENTS
1. INTRODUCTION................................................................................................................................4 2. SIGNAL DESCRIPTION..................................................................................................................11
2.1 OVERVIEW/SIGNAL PIN LIST...................................................................................................11
2.2 CPU BUS SIGNAL DESCRIPTION..............................................................................................17
2.3 T3/E3 RECEIVE FRAMER SIGNAL DESCRIPTION.................................................................19
2.4 T3/E3 TRANSMIT FORMATTER SIGNAL DESCRIPTION......................................................21 2.5 LOW SPEED (T1 OR E1) RECEIVE PORT SIGNAL DESCRIPTION.......................................23
2.6 LOW SPEED (T1 OR E1) TRANSMIT PORT SIGNAL DESCRIPTION...................................24
2.7 HIGH SPEED (T3 OR E3) RECEIVE PORT SIGNAL DESCRIPTION......................................26
2.8 HIGH SPEED (T3 OR E3) TRANSMIT PORT SIGNAL DESCRIPTION..................................26
2.9 JTAG SIGNAL DESCRIPTION.....................................................................................................27 2.10 SUPPLY, TEST, RESET, AND MODE SIGNAL DESCRIPTION............................................27
3. MEMORY MAP
.................................................................................................................................29
4. MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT......................................31 4.1 MASTER RESET AND ID REGISTER DESCRIPTION..............................................................31
4.2 MASTER CONFIGURATION REGISTERS DESCRIPTION......................................................32
4.3 MASTER STATUS AND INTERRUPT REGISTER DESCRIPTION.........................................37
4.4 TEST REGISTER DESCRIPTION................................................................................................46
5. T3/E3 FRAMER.................................................................................................................................47 5.1 GENERAL DESCRIPTION...........................................................................................................47
5.2 T3/E3 FRAMER CONTROL REGISTER DESCRIPTION...........................................................48
5.3 T3/E3 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION..............................53
5.4 T3/E3 PERFORMANCE ERROR COUNTERS............................................................................60
6. M13/E13/G.747 MULTIPLEXER AND T2/E2/G.747 FRAMER..................................................64 6.1 GENERAL DESCRIPTION...........................................................................................................64
6.2 T2/E2/G.747 FRAMER CONTROL REGISTER DESCRIPTION................................................64
6.3 T2/E2/G.747 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION...................66 6.4 T1/E1 AIS GENERATION CONTROL REGISTER DESCRIPTION..........................................70
7. T1/E1 LOOPBACK AND DROP AND INSERT FUNCTIONALITY.........................................73 7.1 GENERAL DESCRIPTION...........................................................................................................73
7.2 T1/E1 LOOPBACK CONTROL REGISTER DESCRIPTION......................................................74 7.3 T1 LINE LOOPBACK COMMAND STATUS REGISTER DESCRIPTION..............................78
7.4 T1/E1 DROP AND INSERT CONTROL REGISTER DESCRIPTION........................................79
8. BERT...................................................................................................................................................81 8.1 GENERAL DESCRIPTION...........................................................................................................81 8.2 BERT REGISTER DESCRIPTION................................................................................................81
DS3112
9. HDLC CONTROLLER.....................................................................................................................90 9.1 GENERAL DESCRIPTION...........................................................................................................90 9.2 HDLC CONTROL AND FIFO REGISTER DESCRIPTION........................................................91
9.3 HDLC STATUS AND INTERRUPT REGISTER DESCRIPTION..............................................95
10. FEAC CONTROLLER..................................................................................................................100 10.1 GENERAL DESCRIPTION.......................................................................................................100 10.2 FEAC CONTROL REGISTER DESCRIPTION........................................................................100
10.3 FEAC STATUS REGISTER DESCRIPTION............................................................................102
11. JTAG................................................................................................................................................103 11.1 JTAG DESCRIPTION................................................................................................................103 11.2 TAP CONTROLLER STATE MACHINE DESCRIPTION......................................................104
11.3 INSTRUCTION REGISTER AND INSTRUCTIONS...............................................................106 11.4 TEST REGISTERS.....................................................................................................................107
12. ELECTRICAL CHARACTERISTICS........................................................................................113
13. MECHANICAL DIMENSIONS...................................................................................................124
14. APPLICATIONS AND STANDARDS OVERVIEW.................................................................125 14.1 APPLICATION EXAMPLES.....................................................................................................125 14.2 M13 BASICS...............................................................................................................................126
14.3 E13 BASICS................................................................................................................................132
14.4 G.747 BASICS............................................................................................................................134
DS3112
1. INTRODUCTION The DS3112 TEMPE (T3 E3 MultiPlexEr) device can be used either as a multiplexer or a T3/E3 framer.
When the device is used as a multiplexer, it can be operated in one of three modes: M13 – multiplex 28 T1 lines into a T3 data stream E13 – multiplex 16 E1 lines into a E3 data stream G.747 – multiplex 21 E1 lines into a T3 data stream
See Figures 1A, 1B, and 1C for block diagrams of these three modes. In each of the block diagrams, the receive section is at the bottom and the transmit section is at the top. The receive path is defined as
incoming T3/E3 data and the transmit path is defined as outgoing T3/E3 data. When the device is
operated solely as a T3 or E3 framer, the multiplexer portion of the device is disabled and the raw T3/E3
payload will be output at the FRD output and input at the FTD input. See Figures 1A and 1B for details. In the receive path, raw T3/E3 data is clocked into the device (either in a bipolar or unipolar fashion) with
the HRCLK at the HRPOS and HRNEG inputs. The data is then framed by the T3/E3 framer and passed
through the two-step demultiplexing process to yield the resultant T1 and E1 data streams, which are
output at the LRCLK and LRDAT outputs. In the transmit path, the reverse occurs. The T1 and E1 data
streams are input to the device at the LTCLK and LTDAT inputs. The device will sample these inputs and then multiplex the T1 and E1 data streams through a two-step multiplexing process to yield the
resultant T3 or E3 data stream. Then this data stream is passed through the T3/E3 formatter to have the
framing overhead added, and the final data stream to be transmitted is output at the HTPOS and HTNEG
outputs using the HTCLK output. The DS3112 has been designed to meet all of the latest telecommunications standards. Table 1A lists all
of the applicable standards for the device.
The TEMPE device has a number of advanced features such as:
§ the ability to drop and insert up to two T1 or E1 ports § an onboard HDLC controller with 256-byte buffers
§ an onboard Bit Error Rate Tester (BERT)
§ advanced diagnostics to create and detect many different types of errors
See Table 1B for a complete list of main features within the device.
DS3112
APPLICABLE STANDARDS Table 1A 1) American National Standard for Telecommunications - ANSI T1.107 – 1995 “Digital Hierarchy -
Formats Specification” 2) American National Standard for Telecommunications - ANSI T1.231 - 199X – Draft “Digital
Hierarchy - Layer 1 In-Service Digital Transmission Performance Monitoring”
3) American National Standard for Telecommunications - ANSI T1.231 – 1993 “Digital Hierarchy -
Layer 1 In-Service Digital Transmission Performance Monitoring”
4) American National Standard for Telecommunications - ANSI T1.404 – 1994 “Network-to-Customer Installation – DS3 Metallic Interface Specification”
5) American National Standard for Telecommunications - ANSI T1.403 – 1999 “Network and Customer
Installation Interfaces – DS1 Electrical Interface”
6) American National Standard for Telecommunications - ANSI T1.102 – 1993 “Digital Hierarchy –
Electrical Interfaces” 7) Bell Communications Research - TR-TSY-000009, Issue 1, May 1986 “Asynchronous Digital
Multiplexes Requirements and Objectives”
8) Bell Communications Research - TR-TSY-000191, Issue 1, May 1986 “Alarm Indication Signal
Requirements and Objectives”
9) Bellcore - GR-499-CORE, Issue 1, December 1995 “Transport Systems Generic Requirements (TSGR): Common Requirements”
10) Bellcore - GR-820-CORE, Issue 1, November 1994 “Generic Digital Transmission Surveillance”
11) Network Working Group Request for Comments - RFC1407, January, 1993 “Definition of Managed
Objects for the DS3/E3 Interface Type”
12) International Telecommunication Union (ITU) G.703, 1991 “Physical/Electrical Characteristics of Hierarchical Digital Interfaces
13) International Telecommunication Union (ITU) G.823, March 1993 “The Control of Jitter and Wander
Within Digital Networks Which are Based on the 2048kbps Hierarchy”
14) International Telecommunication Union (ITU) G.742, 1993 “Second Order Digital Multiplex
Equipment Operating at 8448 kbps and Using Positive Justification” 15) International Telecommunication Union (ITU) G.747, 1993 “Second Order Digital Multiplex
Equipment Operating at 6312 kbps and Multiplexing Three Tributaries at 2048kbps”
16) International Telecommunication Union (ITU) G.751, 1993 “Digital Multiplex Equipments Operating
at the Third Order Bit Rate of 34368kbps and Using Positive Justification”
17) International Telecommunication Union (ITU) G.775, November 1994 “Loss Of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria”
18) International Telecommunication Union (ITU) O.151, October 1992 “Error Performance Measuring
Equipment Operating at the Primary Rate And Above”
19) International Telecommunication Union (ITU) O.153, October 1992 “Basic Parameters for the
Measurement of Error Performance at Bit Rates Below the Primary Rate” 20) International Telecommunication Union (ITU) O.161, 1984 “In-Service Code Violation Monitors for
Digital Systems”
DS3112
MAIN DS3112 TEMPE FEATURES Table 1B
General Features § Can be operated as a standalone T3 or E3 framer without any M13 or E13 multiplexing
§ T1/E1 FIFOs in the receive direction provide T1/E1 demultiplexed clocks with very little jitter § Two T1/E1 drop and insert ports
§ B3ZS/HDB3 encoder and decoder
§ T3 C-Bit Parity mode
§ All the receive T1/E1 ports can be clocked out on a common clock
§ All the transmit T1/E1 ports can be clocked in on a common clock § Generates gapped clocks that can be used as demand clocks in unchannelized T3/E3 applications
§ T1/E1 ports can be configured into a “loop-timed” mode
§ T3/E3 port interfaces can be either bipolar or unipolar
§ The clock, data, and control signals can be inverted to allow a glueless interface to other device
§ Loss of transmit and receive clock detect
T3/E3 Framer § Generates T3/E3 Alarm Indication Signal (AIS) and Remote Alarm Indication (RAI) alarms
§ Transmit framer pass through mode
§ Generates T3 idle signal
§ Detects the following T3/E3 alarms and events: Loss Of Signal (LOS), Loss Of Frame (LOF), Alarm
Indication Signal (AIS), Remote Alarm Indication (RAI), T3 idle signal, Change Of Frame Alignment (COFA), B3ZS and HDB3 code words being received, Severely Errored Framing Event (SEFE), and
T3 Application ID status indication
T2/E2 Framer § Generates T2/E2 Alarm Indication Signal (AIS) and Remote Alarm Indication (RAI) alarms § Generates Alarm Indication Signal (AIS) for T1/E1 data streams in both the transmit and receive
directions § Detects the following T2/E2 alarms and events: Loss Of Frame (LOF), Alarm Indication Signal
(AIS), and Remote Alarm Indication (RAI)
§ Detects T1 line loopback commands (C3 bit is the inverse of C1 and C2) § Generates T1 line loopback commands
HDLC Controller § Designed to handle multiple LAPD messages without Host intervention § 256 byte receive and transmit buffers are large enough to handle the three T3 messages (Path ID, Idle
Signal ID, and Test Signal ID) that are sent and received once a second which means the Host only
needs to access the HDLC Controller once a second § Handles all of the normal Layer 2 tasks such as zero stuffing/destuffing, CRC generation/checking,
abort generation/checking, flag generation/detection, and byte alignment § Programmable high and low watermarks for the FIFO
§ HDLC Controller can be used in either the T3 C-Bit Parity Mode or in the Sn Bits in the E3 Mode
DS3112
FEAC Controller § Designed to handle multiple FEAC code words without Host intervention
§ Receive FEAC automatically validates incoming code words and stores them in a 4-byte FIFO
§ Transmit FEAC can be configured to send either one code word, or constant code words, or two different code words back-to-back to create T3 Line Loopback commands
§ FEAC Controller can be used in either the T3 C-Bit Parity Mode or in the Sn Bits in the E3 Mode
BERT § Can generate and detect the pseudorandom patterns of 27 - 1, 211 - 1, 215 - 1 and QRSS as well as
repetitive patterns from 1 to 32 bits in length § BERT is a global chip resource that can be used either in the T3/E3 data path or in any one of the T1
or E1 data paths
§ Large error counter (24 bits) allows testing to proceed for long periods without Host intervention
§ Errors can be inserted into the generated BERT patterns for diagnostic purposes
Diagnostics § T3/E3 and T1/E1 diagnostic loopbacks (transmit to receive) § T3/E3 and T1/E1 line loopbacks (receive to transmit)
§ T3/E3 payload loopback
§ T3/E3 errors counters for: BiPolar Violations (BPV), Code Violations (CV), Loss Of Frame (LOF),
framing bit errors (F, M or FAS), EXcessive Zeros (EXZ), T3 Parity bits, T3 C-Bit Parity, and Far
End Block Errors (FEBE) § Error counters can be either updated automatically on one second boundaries as timed by the DS3112
or via software control or via an external hardware pulse
§ Can insert the following T3/E3 errors: BiPolar Violations (BPV), EXcessive Zeros (EXZ), T3 Parity bits, T3 C-Bit Parity, framing bit errors (F, M, or FAS)
§ Inserted errors can be either controlled via software or via an external hardware pulse § Generates T2/E2 Loss Of Frame (LOF)
Control Port § Nonmultiplexed or multiplexed 16-bit control port (with an optional 8-bit mode)
§ Intel and Motorola Bus compatible
Packaging and Power § 3.3V low-power CMOS with 5V tolerant inputs and outputs
§ 256-pin plastic BGA package (27mm x 27mm) § IEEE 1149.1 JTAG test port
DS3112
DS3112 FRAMER AND MULTIPLEXER BLOCK DIAGRAM (T3 MODE) Figure 1A FTCLK
FTD
FTDEN
FTSOF
LTCLK
LTDAT
LTCLK
LTDAT
LTCLK
LTDAT
LTCLK
LTDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCCLK
FRSOF
FRCLK
FRD
FRDEN
HRPOS
HRNEG
HRCLK
HTPOS
HTNEG
HTCLK
FRLOF
FRLOS
LTCCLK
LTDATA
LTCLKA
LTDATB
LTCLKB
LRCLKA
LRCLKB
LRDATA
LRDATB
FRMECU
T3E3MSJTMS
JTDO
JTDI
JTCLKJTRST*
FTMEI
G747E
CD0 to
CA0 to
CWR*
CRD*
CCS*CIMCINT*CMSTESTRST*CALE
DS3112
DS3112 FRAMER AND MULTIPLEXER BLOCK DIAGRAM (E3 MODE) Figure 1B FTCLK
FTD
FTDEN
FTSOF
LTCLK
LTDAT
LTCLK
LTDAT
LTCLKLTDAT
LTCLK
LTDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCLKLRDAT
LRCLK
LRDAT
LRCCLKFRSOF
FRCLK
FRD
FRDEN
HRPOS
HRNEG
HRCLK
HTPOS
HTNEG
HTCLK
FRLOF
FRLOS
LTCCLK
LTDATALTCLKA
LTDATB
LTCLKB
LRCLKA
LRCLKB
LRDATA
LRDATB
FRMECUJTMS
JTDO
JTDI
JTCLK
JTRST*
FTMEI
T3E3MS
(tied high)
G747E
(tied low)
CD0 to
CD15
CA0 to
CA7
CWR*
(CR/W*)
CRD*
(CDS*)
CCS*CIMCINT*CMSTESTRST*CALE
DS3112
DS3112 FRAMER AND MULTIPLEXER BLOCK DIAGRAM (G.747 MODE) Figure 1C
CD0 to
CD15
CA0 to
CA7
CWR*
(CR/W*)
CRD*
(CDS*)
CCS*CIMCINT*CMSTESTFTCLK
FTD
FTDEN
FTSOF
LTCLK
LTDAT
LTCLK
LTDAT
LTCLK
LTDAT
LRCLK
LRDAT
LRCLK
LRDAT
LRCLKLRDAT
LRCCLK
FRSOF
FRCLK
FRD
FRDEN
HRPOS
HRNEG
HRCLK
HTPOS
HTNEG
HTCLK
FRLOF
FRLOS
LTCCLK
LTDATALTCLKA
LTDATB
LTCLKB
LRCLKA
LRCLKB
LRDATA
LRDATB
RST*
FRMECU
T3E3MS
(tied low)JTMS
JTDO
JTDI
JTCLK
JTRST*
FTMEI
G747E
(tied high)
CALE
DS3112
2. SIGNAL DESCRIPTION
2.1 Overview/Signal Pin List This section describes the input and output signals on the DS3112. Signal names follow a convention that
is shown in Table 2.1A. Table 2.1B lists all of the signals, their signal type, description, and pin location. Symbols appended with an asterisks (*) are active low signals. The absence of an asterisks implies an
active high signal.
SIGNAL NAMING CONVENTION Table 2.1A
SIGNAL DESCRIPTION/PIN LIST Table 2.1B DS3112
DS3112
DS3112
DS3112
DS3112
DS3112
2.2 CPU Bus Signal Description Signal Name:
CMS Signal Description:
CPU Bus Mode Select Signal Type:
Input This signal should be tied low when the device is to be operated as a 16-bit bus. This signal should be tied
high when the device is to be operated as an 8-bit bus. 0 = CPU Bus is in the 16-Bit Mode 1 = CPU Bus is in the 8-Bit Mode
Signal Name:
CIM Signal Description:
CPU Bus Intel/Motorola Bus Select Signal Type:
Input The signal determines whether the CPU Bus will operate in the Intel Mode (CIM = 0) or the Motorola Mode (CIM = 1). The signal names in parenthesis are operational when the device is in the Motorola
Mode. 0 = CPU Bus is in the Intel Mode 1 = CPU Bus is in the Motorola Mode
DS3112
Signal Name:
CD0 to CD15 Signal Description:
CPU Bus Data Bus Signal Type:
Input/Output (3-State Capable) The external host will configure the device and obtain real time status information about the device via these signals. When reading data from the CPU Bus, these signals will be outputs. When writing data to
the CPU Bus, these signals will become inputs. When the CPU bus is operated in the 8-bit mode
(CMS = 1), CD8 to CD15 are inactive and should be tied low.
Signal Name:
CA0 to CA7 Signal Description:
CPU Bus Address Bus Signal Type:
Input These input signals determine which internal device configuration register that the external host wishes to access. When the CPU bus is operated in the 16-bit mode (CMS = 0), CA0 is inactive and should be tied
low. When the CPU bus is operated in the 8-bit mode (CMS = 1), CA0 is the least significant address bit.
Signal Name:
CWR* (CR/W*) Signal Description:
CPU Bus Write Enable (CPU Bus Read/Write Select) Signal Type:
Input In Intel Mode (CIM = 0), this signal will determine when data is to be written to the device. In Motorola Mode (CIM = 1), this signal will be used to determine whether a read or write is to occur.
Signal Name:
CRD* (CDS*) Signal Description:
CPU Bus Read Enable (CPU Bus Data Strobe) Signal Type:
Input In Intel Mode (CIM = 0) this signal will determine when data is to be read from the device. In Motorola
Mode (CIM = 1), a rising edge will be used to write data into the device. Signal Name:
CINT* Signal Description:
CPU Bus Interrupt Signal Type:
Output (Open Drain) This signal is an open-drain output which will be forced low if one or more unmasked interrupt sources
within the device is active. The signal will remain low until either the interrupt is serviced or masked.
Signal Name:
CCS* Signal Description:
CPU Bus Chip Select Signal Type:
Input This active low signal must be asserted for the device to accept a read or write command from an external host.
Signal Name:
CALE Signal Description:
CPU Bus Address Latch Enable Signal Type:
Input This input signal controls a latch that exists on the CA0 to CA7 inputs. When CALE is high, the latch is
transparent. The falling edge of CALE causes the latch to sample and hold the CA0 to CA7 inputs. In
non-multiplexed bus applications, CALE should be tied high. In multiplexed bus applications, CA[7:0]
should be tied to CD[7:0] and the falling edge of CALE will latch the address.
DS3112
2.3 T3/E3 Receive Framer Signal Description
Signal Name: FRSOF
Signal Description: T3/E3 Receive Framer Start Of Frame Sync Signal Signal Type: Output
This signal pulses for one FRCLK period to indicate the T3 or E3 frame boundary (Figure 2.3A). This
signal can be configured via the FRSOFI control bit in Master Control Register 3 (Section 4.2) to be
either active high (normal mode) or active low (inverted mode). Signal Name: FRCLK
Signal Description: T3/E3 Receive Framer Clock
Signal Type: Output This signal outputs the clock that is used to pass data through the receive T3/E3 framer. It can be sourced
from either the HRCLK or FTCLK inputs (Figures 1A and 1B). This signal is used to clock the receive data out of the device at the FRD output. Data can be either updated on a rising edge (normal mode) or a
falling edge (inverted mode). This option is controlled via the FRCLKI control bit in Master Control
Register 3 (Section 4.2). Signal Name: FRD
Signal Description: T3/E3 Receive Framer Serial Data Signal Type: Output
This signal outputs data from the receive T3/E3 framer. This signal is updated either on the rising edge of FRCLK (normal mode) or the falling edge of FRCLK (inverted mode). This option is controlled via the
FRCLKI control bit in Master Control Register 3 (Section 4.2). Also, this signal can be internally inverted
if enabled via the FRDI control bit in Master Control Register 3 (Section 4.2).
Signal Name: FRDEN Signal Description: T3/E3 Receive Framer Serial Data Enable or Gapped Clock Output
Signal Type: Output
Via the DENMS control bit in Master Control Register 1, this signal can be configured to either output a data enable or a gapped clock. In the data enable mode, this signal will go active when payload data is
available at the FRD output and it will go inactive when overhead data is being output at the FRD output. In the gapped clock mode, this signal will transition for each bit of payload data and will be suppressed
for each bit of overhead data. In the T3 Mode, overhead data is defined as the M Bits, F Bits, C Bits, X
Bits, and P Bits. In the E3 Mode, overhead data is defined as the FAS word, RAI Bit and Sn Bit (i.e., bits 1 to 12). See Figure 2.3A for an example. This signal can be internally inverted if enabled via the
FRDENI control bit in Master Control Register 3 (Section 4.2).
Signal Name: FRMECU
Signal Description: T3/E3 Receive Framer Manual Error Counter Update Strobe Signal Type: Input
Via the AECU control bit in Master Control Register 1 (Section 4.2), the DS3112 can be configured to use this asynchronous input to initiate an updating of the internal error counters. A zero to one transition
on this input causes the device to begin loading the internal error counters with the latest error counts.
This signal must be returned low before a subsequent updating of the error counters can occur. The host must wait at least 100ns before reading the error counters to allow the device time to update the error
counters. This signal is logically OR’ed with the MECU control bit in Master Control Register 1. If this signal is not used, then it should be tied low.
DS3112
Signal Name: FRLOS
Signal Description: T3/E3 Receive Framer Loss Of Signal Signal Type: Output
This signal will be forced high when the receive T3/E3 framer is in a Loss Of Signal (LOS) state. It will remain high as long as the LOS state persists and will return low when the framer exits the LOS state. See
Section 5.3 for details on the set and clear criteria for this signal. LOS status is also available via a
software bit in the T3/E3 Status Register (Section 5.3).
Signal Name: FRLOF Signal Description: T3/E3 Receive Framer Loss Of Frame
Signal Type: Output
This signal will be forced high when the receive T3/E3 framer is in a Loss Of Frame (LOF) state. It will remain high as long as the LOF state persists and will return low when the framer synchronizes. See
Section 5.3 for details on the set and clear criteria for this signal. LOF status is also available via a software bit in the T3/E3 Status Register (Section 5.3).
T3/E3 RECEIVE FRAMER TIMING Figure 2.3A
FRCLK Normal Mode
FRD (see note)
FRCLK Inverted Mode E3 (see note)
FRDEN Gapped Clock Mode for T3(see note)
FRDEN Gapped Clock Mode for E3(see note)
FRSOF (see note)
DS3112
2.4 T3/E3 Transmit Formatter Signal Description
Signal Name: FTSOF
Signal Description: T3/E3 Transmit Formatter Start Of Frame Sync Signal Signal Type: Output/Input
This signal can be configured via the FTSOFC control bit in Master Control Register 1 to be either an
output or an input. When this signal is an output, it pulses for one FTCLK period to indicate a T3 or E3
frame boundary (Figure 2.4A). When this signal is an input, it is sampled to set the transmit T3 or E3
frame boundary (Figure 2.4A). This signal can be configured via the FTSOFI control bit in Master Control Register 3 (Section 4.2) to be either active high (normal mode) or active low (inverted mode).
Signal Name: FTCLK
Signal Description: T3/E3 Transmit Formatter Clock
Signal Type: Input An accurate T3 (44.736MHz ±20ppm) or E3 (34.368MHz ±20ppm) clock should be applied at this signal.
This signal is used to clock data into the transmit T3/E3 formatter. Transmit data can be clocked into the
device either on a rising edge (normal mode) or a falling edge (inverted mode). This option is controlled
via the FTCLKI control bit in Master Control Register 3 (Section 4.2). Signal Name: FTD
Signal Description: T3/E3 Transmit Formatter Serial Data
Signal Type: Input
This signal inputs data into the transmit T3/E3 formatter. This signal can be sampled either on the rising
edge of FTCLK (normal mode) or the falling edge of FTCLK (inverted mode). This option is controlled via the FTCLKI control bit in Master Control Register 3 (Section 4.2). Also, the data input to this signal
can be internally inverted if enabled via the FTDI control bit in Master Control Register 3 (Section 4.2).
When T3 C-Bit Parity Mode is disabled, C Bits are sampled at this input. This signal is ignored when the
M13/E13 multiplexer is enabled. (See the UNCHEN control bit in Master Control Register 1.) If not
used, this signal should be tied low.
Signal Name: FTDEN
Signal Description: T3/E3 Transmit Formatter Serial Data Enable or Gapped Clock Output
Signal Type: Output
Via the DENMS control bit in Master Control Register 1, this signal can be configured to either output a data enable or a gapped clock. In the data enable mode, this signal will go active when payload data
should be made available at the FTD input. In the gapped clock mode, this signal will act as a demand
clock for the FTD input and it will transition for each bit of payload data needed at the FTD input and it
will be suppressed when the transmit formatter inserts overhead data and hence no data is needed at the
FTD input. In the T3 Mode, overhead data is defined as the M Bits, F Bits, C Bits, X Bits, and P Bits. In the E3 Mode, overhead data is defined as the FAS word, RAI Bit and Sn Bit (i.e., bits 1 to 12). See Figure
2.4A for an example. his signal can be internally inverted if enabled via the FTDENI control bit in
Master Control Register 3 (Section 4.2). This signal operates in the same manner even when the device is
configured in the Transmit Pass Through mode (see the TPT control bit in the T3/E3 Control Register).
DS3112
Signal Name: FTMEI
Signal Description: T3/E3 Transmit Formatter Manual Error Insert Strobe Signal Type: Input
Via the EIC control bit in the T3/E3 Error Insert Control Register (Section 5.2), the DS3112 can be configured to use this asynchronous input to cause errors to be inserted into the transmitted data stream.
A zero to one transition on this input causes the device to begin the process of causing errors to be
inserted. This signal must be returned low before any subsequent errors can be generated. If this signal is not used, then it should be tied low.
T3/E3 TRANSMIT FORMATTER TIMING Figure 2.4A
FTCLK
Inverted Mode
FTD (see note)
FTSOF Input Mode
(see note)
FTCLK Normal Mode
E3 (see note)
FTDEN Gapped Clock Mode for T3
(see note)
FTDEN
Gapped Clock Mode for E3(see note)
FTSOF Output Mode
(see note)
3.
DS3112
2.5 Low Speed (T1 or E1) Receive Port Signal Description
Signal Name: LRDAT1 to LRDAT28
Signal Description: Low Speed (T1 or E1) Receive Serial Data Outputs Signal Type: Output
These output signals present the demultiplexed serial data for the 28 T1 data streams or the 16/21 E1 data
streams. Data can be clocked out of the device either on rising edges (normal clock mode) or falling
edges (inverted clock mode) of the associated LRCLK. This option is controlled via the LRCLKI control
bit in Master Control Register 2 (Section 4.2). Also, the data can be internally inverted before being output if enabled via the LRDATI control bit in Master Control Register 2 (Section 4.2). When the device
is in the E3 Mode, LRDAT17 to LRDAT28 are meaningless and should be ignored. When the device is
in the G.747 Mode, LRDAT4, LRDAT8, LRDAT12, LRDAT16, LRDAT20, LRDAT24, and LRDAT28
are meaningless and should be ignored. When the M13/E13 multiplexer is disabled, then these outputs are
meaningless and should be ignored.
Signal Name: LRCLK1 to LRCLK28
Signal Description: Low Speed (T1 or E1) Receive Serial Clock Outputs
Signal Type: Output
These output signals present the demultiplexed serial clocks for the 28 T1 data streams or the 16/21 E1 data streams. The T1 or E1 serial data streams at the associated LRDAT signals can be clocked out of the
device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of LRCLK.
This option is controlled via the LRCLKI control bit in Master Control Register 2 (Section 4.2). When the
device is in the E3 Mode, LRCLK17 to LRCLK28 are meaningless and should be ignored. When the
device is in the G.747 Mode, LRCLK4, LRCLK8, LRCLK12, LRCLK16, LRCLK20, LRCLK24, and LRCLK28 are meaningless and should be ignored. When the M13/E13 multiplexer is disabled, then these
outputs are meaningless and should be ignored.
Signal Name: LRDATA/LRDATB
Signal Description: Low Speed (T1 or E1) Receive Drop Port Serial Data Outputs Signal Type: Output
These two output signals present the demultiplexed serial data from one of the 28 T1 data streams or from
one of the 16/21 E1 data streams (Section 7.4). Data can be clocked out of the device either on rising
edges (normal clock mode) or falling edges (inverted clock mode) of the associated LRCLK. This option
is controlled via the LRCLKI control bit in Master Control Register 2 (Section 4.2). Also, the data can be internally inverted before being output if enabled via the LRDATI control bit in Master Control Register
2 (Section 4.2). When the M13/E13 multiplexer is disabled, then these outputs are meaningless and
should be ignored.
DS3112
Signal Name: LRCLKA/LRCLKB
Signal Description: Low Speed (T1 or E1) Receive Drop Port Serial Clock Outputs Signal Type: Output
These output signals present the demultiplexed serial clocks from one of the 28 T1 data streams or from one of the 16/21 E1 data streams (Section 7.4). The T1 or E1 serial data streams at the associated LRDAT
signals can be clocked out of the device either on rising edges (normal clock mode) or falling edges
(inverted clock mode) of LRCLK. This option is controlled via the LRCLKI control bit in Master Control Register 2 (Section 4.2). When the M13/E13 multiplexer is disabled, then these outputs are meaningless
and should be ignored.
Signal Name: LRCCLK
Signal Description: Low Speed (T1 or E1) Receive Common Clock Input Signal Type: Input
If enabled via the LRCCEN control bit in Master Control Register 1 (Section 4.2), all 28 LRCLK or 16/21 LRCLK can be slaved to this common clock input. In T3 mode, LRCCLK would be a 1.544MHz
clock and in E3 mode, LRCCLK would be 2.048MHz. Use of this configuration is only possible in
applications where it can be guaranteed that all of the multiplexed T1 or E1 signals at the far end are based on a common clock. If this signal is not used, then it should be tied low. This signal can be
internally inverted. This option is controlled via the LRCLKI control bit in Master Control Register 2 (Section 4.2).
2.6 LOW SPEED (T1 OR E1) TRANSMIT PORT SIGNAL DESCRIPTION Signal Name: LTDAT1 to LTDAT28
Signal Description: Low Speed (T1 or E1) Transmit Serial Data Inputs
Signal Type: Input
These input signals sample the serial data from the 28 T1 data streams or the 16/21 E1 data streams that will be multiplexed into a single T3 or E3 data stream. Data can be clocked into the device either on
falling edges (normal clock mode) or rising edges (inverted clock mode) of the associated LTCLK. This
option is controlled via the LTCLKI control bit in Master Control Register 2 (Section 4.2). Also, the data
can be internally inverted before being multiplexed if enabled via the LTDATI control bit in Master
Control Register 2 (Section 4.2). When the device is in the E3 Mode, LTDAT17 to LTDAT28 are ignored and should be tied low. When the device is in the G.747 Mode, LTDAT4, LTDAT8, LTDAT12,
LTDAT16, LTDAT20, LTDAT24, and LTDAT28 are ignored and should be tied low. When the
M13/E13 multiplexer is disabled, then these inputs are ignored and should be tied low.
Signal Name: LTCLK1 to LTCLK28 Signal Description: Low Speed (T1 or E1) Transmit Serial Clock Inputs
Signal Type: Input
These input signals clock data in from the 28 T1 data streams or from the 16/21 E1 data streams. The T1
or E1 serial data streams at the associated LTDAT signals can be clocked into the device either on falling
edges (normal clock mode) or rising edges (inverted clock mode) of LTCLK. This option is controlled via the LTCLKI control bit in Master Control Register 2 (Section 4.2). When the device is in the E3 Mode,
LTCLK17 to LTCLK28 are meaningless and should be tied low. When the device is in the G.747 Mode,
LTCLK4, LTCLK8, LTCLK12, LTCLK16, LTCLK20, LTCLK24, and LTCLK28 are meaningless and
should be tied low. When the M13/E13 multiplexer is disabled, then these inputs are ignored and should
be tied low.
DS3112
Signal Name: LTDATA/LTDATB
Signal Description: Low Speed (T1 or E1) Transmit Insert Port Serial Data Inputs Signal Type: Input
These two input signals allow data to be inserted in place of any of the 28 T1 data streams or into any of the 16/21 E1 data streams (Section 7.4). Data can be clocked into the device either on falling edges
(normal clock mode) or rising edges (inverted clock mode) of the associated LTCLK. This option is
controlled via the LTCLKI control bit in Master Control Register 2 (Section 4.2). Also, the data can be internally inverted before being multiplexed if enabled via the LTDATI control bit in Master Control
Register 2 (Section 4.2). When the M13 / E13 multiplexer is disabled, then these inputs are ignored and should be tied low.
Signal Name: LTCLKA/LTCLKB Signal Description: Low Speed (T1 or E1) Transmit Insert Port Serial Clock Inputs
Signal Type: Input These two input signals are used to clock data into the device that will be inserted into one of the 28 T1
data streams or into one of the 16/21 E1 data streams (Section 7.4). The T1 or E1 serial data streams at
the associated LTDAT signals can be clocked into the device either on falling edges (normal clock mode) or rising edges (inverted clock mode) of LTCLKA/LTCLKB. This option is controlled via the LTCLKI
control bit in Master Control Register 2 (Section 4.2). When the M13 / E13 multiplexer is disabled, then these inputs are ignored and should be tied low.
Signal Name: LTCCLK Signal Description: Low Speed (T1 or E1) Transmit Common Clock Input
Signal Type: Input
If enabled via the LTCCEN in Master Control Register 1 (Section 4.2), all 28 LTCLK or 16 LTCLK
signals are disabled and all the data at the 28 LTDAT or 16 LTDAT inputs (as well as the LTDATA and
LTDATB inputs) will be clocked into the device using the LTCCLK signal. In T3 mode, LTCCLK would be a 1.544MHz clock and in E3 mode, LTCCLK would be 2.048MHz. If not used, this signal should be
tied low. If this signal is used, then all of the LTCLK signals should be tied low. This signal can be
internally inverted. This option is controlled via the LTCLKI control bit in Master Control Register 2
(Section 4.2).
DS3112
2.7 High-Speed (T3 or E3) Receive Port Signal Description
Signal Name: HRPOS/HRNEG
Signal Description: High-Speed (T3 or E3) Receive Serial Data Inputs Signal Type: Input
These input signals sample the serial data from the incoming T3 data streams or E3 data streams. Data
can be clocked into the device either on rising edges (normal clock mode) or falling edges (inverted clock
mode) of the associated HRCLK. This option is controlled via the HRCLKI control bit in Master Control
Register 2 (Section 4.2).
Signal Name: HRCLK
Signal Description: High-Speed (T3 or E3) Receive Serial Clock Input
Signal Type: Input
This signal is used to clock data in from the incoming T3 or E3 data streams. The T3 or E3 serial data streams at the HRPOS and HRNEG signals can be clocked into the device either on rising edges (normal
clock mode) or falling edges (inverted clock mode) of HRCLK. This option is controlled via the HRCLKI
control bit in Master Control Register 2 (Section 4.2).
Note: The HRCLK must be present for the host to be able to obtain status information (except the LOTC and LORC status bits – see Section 4.3) from the device.
2.8 High-Speed (T3 or E3) Transmit Port Signal Description
Signal Name: HTPOS/HTNEG
Signal Description: High-Speed (T3 or E3) Transmit Serial Data Outputs Signal Type: Output
These output signals present the outgoing T3 data streams or E3 data streams. Data can be clocked out of
the device either on rising edges (normal clock mode) or falling edges (inverted clock mode) of HTCLK.
This option is controlled via the HTCLKI control bit in Master Control Register 2 (Section 4.2). Also,
these outputs can be forced high or low via the HTDATH and HTDATL control bits respectively in Master Control Register 2 (Section 4.2).
Signal Name: HTCLK
Signal Description: High-Speed (T3 or E3) Transmit Serial Clock Output
Signal Type: Output This output signal is used to clock T3 or E3 data out of the device. The T3 or E3 serial data streams at the
HTPOS and HTNEG signals can be clocked out of the device either on rising edges (normal clock mode)
or falling edges (inverted clock mode) of HTCLK. This option is controlled via the HTCLKI control bit
in Master Control Register 2 (Section 4.2).
DS3112
2.9 JTAG Signal Description
Signal Name: JTCLK
Signal Description: JTAG IEEE 1149.1 Test Serial Clock Signal Type: Input
This signal is used to shift data into JTDI on the rising edge and out of JTDO on the falling edge. If not
used, this signal should be pulled high.
Signal Name: JTDI Signal Description: JTAG IEEE 1149.1 Test Serial Data Input
Signal Type: Input (with internal 10k pullup)
Test instructions and data are clocked into this signal on the rising edge of JTCLK. If not used, this signal
should be pulled high. This signal has an internal pullup. Signal Name: JTDO
Signal Description: JTAG IEEE 1149.1 Test Serial Data Output
Signal Type: Output
Test instructions are clocked out of this signal on the falling edge of JTCLK. If not used, this signal
should be left open circuited.
Signal Name: JTRST*
Signal Description: JTAG IEEE 1149.1 Test Reset
Signal Type: Input (with internal 10k pullup)
This signal is used to asynchronously reset the test access port controller. At power-up, JTRST must be set low and then high. This action will set the device into the boundary scan bypass mode allowing
normal device operation. If boundary scan is not used, this signal should be held low. This signal has an
internal pullup.
Signal Name: JTMS Signal Description: JTAG IEEE 1149.1 Test Mode Select
Signal Type: Input (with internal 10k pullup)
This signal is sampled on the rising edge of JTCLK and is used to place the test port into the various
defined IEEE 1149.1 states. If not used, this signal should be pulled high. This signal has an internal
pullup.
2.10 Supply, Test, Reset, and Mode Signal Description
Signal Name: RST*
Signal Description: Global Hardware Reset
Signal Type: Input (with internal 10k pullup) This active low asynchronous signal causes the device to be reset. When this signal is forced low, it
causes all of the internal registers to be forced to 00h and the high speed T3/E3 ports as well as the low
speed T1/E1 ports to source an unframed all ones data pattern. The device will be held in a reset state as
long as this signal is low. This signal should be activated after the hardware configuration signals (LIEN
and T3E3MS) and the clocks (FTCLK, LTCLK, HRCLK, and LITCLK) are stable and must be returned high before the device can be configured for operation.
DS3112
Signal Name: T3E3MS
Signal Description: T3/E3 Mode Select Input Signal Type: Input
This signal determines whether the DS3112 will operate in either the T3 mode or the E3 mode. It acts as a global control bit for the entire DS3112. This signal should be set into the proper state before a hardware
reset is issued via the RST* signal. This input is coupled with the G.747E input to create a special test
mode whereby all of the outputs are 3-stated (Table 2.10A). 0 = T3 Mode 1 = E3 Mode
Signal Name: G.747E
Signal Description: G.747 Mode Enable Input Signal Type: Input
This signal determines whether the DS3112 will operate in either the T3 mode or the G.747 mode. It acts as a global control bit for the entire DS3112. This signal should be set into the proper state before a
hardware reset is issued via the RST* signal. This input is coupled with the T3E3MS input to create a
special test mode whereby all of the outputs are 3-stated (Table 2.10A). 0 = T3 Mode 1 = G.747 Mode
MODE SELECT DECODE Table 2.10A Signal Name: TEST*
Signal Description: Factory Test Input Signal Type: Input (with internal 10k pullup)
This input should be left open circuited by the user. Signal Name: VSS
Signal Description: Digital Ground Reference Signal Type: N/A
All VSS signals should be tied together. Signal Name: VDD
Signal Description: Digital Positive Supply Signal Type: N/A
3.3V (±5%). All VDD signals should be tied together.
DS3112
3. MEMORY MAP
DS3112
*Addresses A0 to FF are not assigned.
DS3112
4. MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT
4.1 Master Reset and ID Register Description
The master reset and ID (MRID) register can be used to globally reset the device. When the RST bit is set
to one, all of the internal registers will be placed into their default state, which is 0000h. A reset can also be invoked by the RST* hardware signal.
The upper byte of the MRID register is read-only and it can be read by the host to determine the chip
revision. Contact the factory for specifics on the meaning of the value read from the ID0 to ID7 bits. Register Name: MRID
Register Description: Master Reset and ID Register
Register Address: 00h
Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit # 15 14 13 12 11 10 9 8
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Master Software Reset (RST). When this bit is set to a one by the host, it will force all of the internal registers to their default state, which is 0000h and forces the T3/E3 and T1/E1 outputs to send an
all ones pattern. This bit must be set high for a minimum of 100ns. This software bit is logically OR’ed
with the hardware signal RST*. 0 = normal operation 1 = force all internal registers to their default value of 0000h
Bit 1/Low Speed (T1/E1) Receive FIFO Reset (RFIFOR). A zero to one transition on this bit will
cause the receive T1/E1 demux FIFOs to be reset, which will cause them to be flushed. See the DS3112
Block Diagrams in Figures 1A and 1B for details on the placement of the FIFOs within the chip. This bit
must be cleared and set again for a subsequent reset to occur.
Bit 2/T2/E2/G.747 Force Receive Framer Resynchronization (T2E2RSY). A zero to one transition on
this bit will cause all seven of the T2 receive framers or all four of the E2 receive framers or all seven of
the G.747 framers to resynchronize. This bit must be cleared and set again for a subsequent
resynchronization to occur.
DS3112
Bit 3/T3/E3 Force Receive Framer Resynchronization (T3E3RSY). A zero to one transition on this bit
will cause the T3 receive framer or the E3 receive framer to resynchronize. This bit must be cleared and set again for a subsequent resynchronization to occur. Bits 8 to 15/Chip Revision ID Bit 0 to 7 (ID0 to ID7). Read-only. Contact the factory for details on the
meaning of the ID bits.
4.2 Master Configuration Registers Description Register Name: MC1
Register Description: Master Configuration Register 1
Register Address: 02h
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Zero Code Suppression Disable (ZCSD). 0 = enable the B3ZS and HDB3 encoders/decoders 1 = disable the B3ZS and HDB3 encoders/decoders
Bit 1/T3/E3 Unchannelized Mode Enable (UNCHEN). When this bit is set low, the M13/E13/G.747
multiplexer is enabled and data at the FTD input is ignored. When this bit is set high, the M13/E13/G.747 multiplexer is disabled and the LTDAT inputs are ignored. The table below displays which bits are not
sampled at the FTD input when UNCHEN = 1. 0 = enable the M13/E13/G.747 multiplexers and disable the FTD Input 1 = disable the M13/E13/G.747 multiplexers and enable the FTD Input
DS3112
Bit 2/T3 C-Bit Parity Mode Enable (CBEN). This bit is only active when the device is T3 mode. When
this bit is set low, C-Bit Parity is defeated and the C Bits are sourced from the M23 Multiplexer Block (Figure 1A). This bit should not be set low in the T3 unchannelized mode (UNCHEN = 1). When this bit
is set high, C-Bit Parity mode is enabled and the C bits are sourced from the T3 framer block (Figures 1A and 1C). 0 = disable C-Bit Parity mode (also known as the M23 Mode) 1 = enable C-Bit Parity mode
Bit 3/Automatic One-Second Error Counters Update Defeat (AECU). When this bit is set low, the device will automatically update the T3/E3 performance error counters on an internally created one
second boundary. The host will be notified of the update via the setting of the OST status bit in the
Master Status Register. In this mode, the host has a full one second period to retrieve the error information before if will be overwritten with the next update. When this bit is set high, the device will
defeat the automatic one second update and enable a manual update mode. In the manual update mode, the device relies on either the Framer Manual Error Counter Update (FRMECU) hardware input signal or
the MECU control bit to update the error counters. The FRMECU hardware input signal and MECU
control bit are logically OR’ed and hence a zero to one transition on either will initiate an error counter update to occur. After either the FRMECU signal or MECU bit has toggled, the host must wait at least
100ns before reading the error counters to allow the device time to complete the update. 0 = enable the automatic update mode and disable the manual update mode 1 = disable the automatic update mode and enable the manual update mode Bit 4/Manual Error Counter Update (MECU). A zero to one transition on this bit will cause the device
to update the performance error counters. This bit is ignored if the AECU control bit is set low. This bit
must be cleared and set again for a subsequent update. This bit is logically OR’ed with the external
FRMECU hardware input signal. After this bit has toggled, the host must wait at least 100ns before
reading the error counters to allow the device time to complete the update.
Bit 5/High-Speed (T3/E3) Port Unipolar Enable (UNI). When this bit is set low, the device will output
a bipolar coded signal at HTPOS and HTNEG and expect a bipolar coded signal at HRPOS and HRNEG.
When this bit is set high, the device will output a NRZ coded signal at HTPOS and expect a NRZ coded
signal at HRPOS. In the unipolar mode, the device will force the HTNEG output low and the HRNEG input is ignored and should be tied low. In the unipolar mode, the B3ZS and HDB3 coder/decoders
should be disabled by setting the ZCSD bit to one (ZCSD = 1). 0 = bipolar mode 1 = unipolar mode Bit 6/Loss Of Transmit Clock Mux Control (LOTCMC). The DS3112 can detect if the FTCLK fails to
transition. If this bit is set low, the device will take no action (other than setting the LOTC status bit)
when the FTCLK fails to transition. When this bit is set high, the device will automatically switch to the
input receive clock (HRCLK) when the FTCLK fails and transmit AIS. 0 = do not switch to the HRCLK signal if FTCLK fails to transition 1 = automatically switch to the HRCLK signal if the FTCLK fails to transition and send AIS
DS3112
Bit 7/T3/E3 Transmit Frame Sync I/O Control (FTSOFC). When this bit is set low, the FTSOF signal
will be an output and will pulse for one FTCLK cycle at the beginning of each frame. When this bit is high, the FTSOF signal is an input and the device uses it to determine the frame boundaries. 0 = FTSOF is an output 1 = FTSOF is an input
Bit 8/Low-Speed (T1/E1) Transmit Port Common Clock Enable (LTCCEN). When this bit is set high, the LTCLK1 to LTCLK28 and LTCLKA and LTCLKB inputs are ignored and a common clock
sourced via the LTCCLK input is used in their place. 0 = disable LTCCLK 1 = enable LTCCLK Bit 9/Low-Speed (T1/E1) Receive Port Common Clock Enable (LRCCEN). When this bit is set high,
the LRCLK1 to LRCLK28 and LRCLKA and LRCLKB outputs will all be sourced from the LRCCLK input. This configuration can only be used in applications where it can be insured that all of the T1 or E1
channels from the far end are being sourced from a common clock. 0 = disable LRCCLK 1 = enable LRCCLK Bit 10/High-Speed (T3/E3) Data Enable Mode Select (DENMS). When this bit is set low, the FRDEN
and FTDEN outputs will be asserted during payload data and deasserted during overhead data. When this
bit is high, FRDEN and FTDEN are gapped clocks that pulse during payload data and are suppressed during overhead data. 0 = FRDEN and FTDEN are data enables 1 = FRDEN and FTDEN are gapped clocks
Bit 11/Low-Speed (T1/E1) Port Loop Timed Mode (LLTM). When this bit is set low, the low speed T1 and E1 receive clocks (LRCLK) are not routed to the transmit side. When this bit is high, the LRCLKs
are routed to the transmit side to be used as the transmit T1 and E1 clocks. When enabled, all the low
speed ports are looped timed. This control bit affects all the low speed ports. The device is not capable of
setting individual low speed ports into and out of looped timed mode. See the block diagram in Figures
1A and 1B for more details. 0 = disable loop timed mode (LRCLK is not used to replace the associated LTCLK) 1 = enable loop timed mode (LRCLK replaces the associated LTCLK)
Register Name: MC2
Register Description: Master Configuration Register 2 Register Address: 04h
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default
DS3112
Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/HTCLK Invert Enable (HTCLKI). 0 = do not invert the HTCLK signal (normal mode) 1 = invert the HTCLK signal (inverted mode)
Bit 1/HTPOS/HTNEG Invert Enable (HTDATI). 0 = do not invert the HTPOS and HTNEG signals (normal mode) 1 = invert the HTPOS and HTNEG signals (inverted mode)
Bit 2/HRCLK Invert Enable (HRCLKI). 0 = do not invert the HRCLK signal (normal mode) 1 = invert the HRCLK signal (inverted mode) Bit 3/HRPOS/HRNEG Invert Enable (HTDATI). 0 = do not invert the HRPOS and HRNEG signals (normal mode) 1 = invert the HRPOS and HRNEG signals (inverted mode)
Bit 4/HTPOS/HTNEG Force High Disable (HTDATH). Please note that this bit must be set by the host in order for T3/E3 traffic to be output from the device. 0 = force the HTPOS and HTNEG signals high (force high mode) 1 = allow normal transmit data to appear at the HTPOS and HTNEG signals (normal mode)
Bit 5/HTPOS/HTNEG Force Low Enable (HTDATL). 0 = allow normal transmit data to appear at the HTPOS and HTNEG signals (normal mode) 1 = force the HTPOS and HTNEG signals low (force low mode) Bit 8/LTCLK Invert Enable (LTCLKI). 0 = do not invert the LTCLK[n], LTCLKA, LTCLKB, and LTCCLK signals (normal mode) 1 = invert the LTCLK[n], LTCLKA, LTCLKB, and LTCCLK signals (inverted mode)
Bit 9/LTDAT Invert Enable (LTDATI). 0 = do not invert the LTDAT[n], LTDATA and LTDATB signals (normal mode) 1 = invert the LTDAT[n], LTDATA and LTDATB signals (inverted mode)
Bit 10/LRCLK Invert Enable (LRCLKI). 0 = do not invert the LRCLK[n], LRCLKA, LRCLKB, and LRCCLK signals (normal mode) 1 = invert the LRCLK[n], LRCLKA, LRCLKB, and LRCCLK signals (inverted mode) Bit 11/LRDAT Invert Enable (LRDATI). 0 = do not invert the LRDAT[n], LRDATA and LRDATB signals (normal mode) 1 = invert the LRDAT[n], LRDATA and LRDATB signals (inverted mode)
DS3112
Register Name: MC3
Register Description: Master Configuration Register 3 Register Address: 06h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/FTDEN Invert Enable (FTDENI). 0 = do not invert the FTDEN signal (normal mode) 1 = invert the FTDEN signal (inverted mode)
Bit 1/FTD Invert Enable (FTDI). 0 = do not invert the FTD signal (normal mode) 1 = invert the FTD signal (inverted mode) Bit 2/FTCLK Invert Enable (FTCLKI). 0 = do not invert the FTCLK signal (normal mode) 1 = invert the FTCLK signal (inverted mode)
Bit 3/FTSOF Invert Enable (FTSOFI). 0 = do not invert the FTSOF signal (normal mode) 1 = invert the FTSOF signal (inverted mode)
Bit 4/FRDEN Invert Enable (FRDENI). 0 = do not invert the FRDEN signal (normal mode) 1 = invert the FRDEN signal (inverted mode) Bit 5/FRD Invert Enable (FRDI). 0 = do not invert the FRD signal (normal mode) 1 = invert the FRD signal (inverted mode)
Bit 6/FRCLK Invert Enable (FRCLKI). 0 = do not invert the FRCLK signal (normal mode) 1 = invert the FRCLK signal (inverted mode) Bit 7/FRSOF Invert Enable (FRSOFI). 0 = do not invert the FRSOF signal (normal mode) 1 = invert the FRSOF signal (inverted mode)
DS3112
4.3 Master Status and Interrupt Register Description
A Note about the Status Registers in the DS3112
The status registers in the DS3112 allow the host to monitor the real-time condition of the device. Most of
the status bits in the device can cause a hardware interrupt to occur. Also, most of the status bits within the device are latched to ensure that the host can detect changes in state and the true status of the device.
There are three types of status bits in the DS3112. The first type is called an event status bit and is
derived from a momentary condition or state that occurs within the device. The event status bits are
always cleared when read and can generate an interrupt when they are asserted. An example of an event
status bit is the one-second timer boundary occurrence (OST).
The second type of status bit is called an alarm status bit, which is derived from conditions that can occur
for longer than an instance. The alarm status bits will be cleared when read unless the alarm is still
present. The alarm status bits generate interrupts on a change in state in the alarm (i.e., when it is asserted
or deasserted). An example of an alarm status bit is the loss of frame (LOF).
The third type of status bit is called a real-time status bit. The real-time status bit remains active as long
as the condition exists and will generate an interrupt as long as the condition exists. An example of a
real-time status bit is the loss of transmit clock (LOTC).
EVENT STATUS BIT Figure 4.3A
ALARM STATUS BIT Figure 4.3B
Internal Signal
Status Bit
Interrupt
Internal Signal
Status Bit
Interrupt
Read
DS3112
REAL-TIME STATUS BIT Figure 4.3C
A Note about the MSR
The Master Status Register (MSR) is a special status register that can be used to help the host quickly locate changes in device status. There is a status bit in the MSR for each of the major blocks within the
DS3112. When an alarm or event occurs in one of these blocks, the device can be configured to set a bit
in the MSR. Status bits in the MSR can also cause a hardware interrupt to occur. In either polled or interrupt driven software routines, the host can first read the MSR to locate which status registers need to
be serviced.
Register Name: MSR
Register Description: Master Status Register Register Address: 08h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/One-Second Timer Boundary Occurrence (OST). This latched read-only event-status bit will be
set to a one on each one-second boundary as timed by the DS3112. The device chooses an arbitrary one
second boundary that is timed from the HRCLK signal. This bit will be cleared when read and will not be set again until another one-second boundary has occurred. The setting of this status bit can cause a
hardware interrupt to occur if the OST bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
Bit 1/Counter Overflow Event (COVF). This latched read-only event-status bit will be set to a one if any of the error counters saturates (the error counters saturate when full). This bit will be cleared when
read even if one or more of the error counters is still saturated. The setting of this status bit can cause a hardware interrupt to occur if the COVF bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when this bit is read.
Internal Signal
Status Bit
Interrupt
DS3112
Bit 2/Change in BERT Status (BERT). This read-only real-time status bit will be set to a one if there is
a major change of status in the BERT receiver and the associated interrupt enable bit is set in the BERTCO register. A major change of status is defined as either a change in the receive synchronization
(i.e., the BERT has gone into or out of receive synchronization), a bit error has been detected, or an overflow has occurred in either the Bit Counter or the Error Counter. The host must read the status bits of
the BERT in the BERT Status Register (BERTEC0) to determine the change of state. This bit will be
cleared when the BERTEC0 is read and will not be set again until the BERT has experienced another change of state. The setting of this status bit can cause a hardware interrupt to occur if the BERT bit in
the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the BERTEC0 register is read (Figure 4.3D).
Bit 3/Change in HDLC Status (HDLC). This read-only real-time status bit will be set to a one if there is a change of status in the HDLC controller and the associated interrupt enable bit is set in the IHSR
register. The host must read the status bits of the HDLC in the HDLC Status Register (HSR) to determine the change of state. This bit will be cleared when the HSR is read and will not be set again until the
HDLC has experienced another change of state. The setting of this status bit can cause a hardware
interrupt to occur if the HDLC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the HSR register is read (Figure 4.3E). Bit 4/Change in FEAC Status (FEAC). This read-only real-time status bit will be set to a one when the
FEAC controller has detected and verified a new Far End Alarm and Control (FEAC) 16-bit code word.
This bit will be cleared when the FEAC Status Register (FSR) is read and will not be set again until the FEAC controller has detected and verified another new code word. The setting of this status bit can cause
a hardware interrupt to occur if the FEAC bit in the Interrupt Mask for MSR (IMSR) register is set to a
one. The interrupt will be allowed to clear when the FSR register is read.
Bit 5/Change in T2/E2 LOF or AIS Status (T2E2SR1). This read-only real-time status bit will be set to a one when one or more of the T2/E2/G.747 framers have detected a change in either Loss Of Frame
(LOF) or Alarm Indication Signal (AIS) and the associated interrupt enable bit is set in the T2E2SR1
register. See the T2E2SR1 register description in Section 6.3 for more details. This bit will be cleared
when the T2E2SR1 register is read. The setting of this status bit can cause a hardware interrupt to occur if
the T2E2SR1 bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the T2E2SR1 register is read (Figure 4.3F).
Bit 6/Change in T2/E2 RAI Status (T2E2SR2). This read-only real-time status bit will be set to a one
when one or more of the T2/E2/G.747 framers have detected a change in the detection of the Remote
Alarm Indication (RAI) signal and the interrupt enable (bit 7) is set in the T2E2SR2 register. See the T2E2SR2 register description in Section 6.3 for more details. This bit will be cleared when the T2E2SR2
register is read. The setting of this status bit can cause a hardware interrupt to occur if the T2E2SR2 bit in
the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when
the T2E2SR2 register is read (Figure 4.3G). Bit 8/T1 Loopback Detected (T1LB). This read-only real-time status bit will be set to a one when one or
more of the T2 framers have detects an active T1 loopback command. See the T1LBSR1 and T1LBSR2
register descriptions in Section 7.3 for more details. This bit will be cleared when the T1 loopback
command is no longer active on any of the lines. The setting of this status bit can cause a hardware
interrupt to occur if the T1LB bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the none of the T2 framers detects an active T1 loopback
DS3112
Bit 9/Change in T3/E3 Framer Status (T3E3SR). This read-only real-time status bit will be set to a one
when the T3/E3 framer has detected a change in RAI, AIS, LOF, LOS, or T3 Idle signal or has detected the start of a Transmit or Receive Frame and the associated interrupt enable bit is set in the T3E3SR
register. See the T3E3SR register description in Section 5.3 for more details. This bit will be cleared when the T3E3SR register is read. The setting of this status bit can cause a hardware interrupt to occur if
the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be
allowed to clear when the T3E3SR register is read (Figure 4.3I).
Bit 10/Loss Of Transmit Clock Detected (LOTC). This read-only real-time status bit will be set to a one when the device detects that the FTCLK clock has not toggled for 200ns (±100ns). This bit will be
cleared when a clock is detected at the FTCLK input. The setting of this status bit can cause a hardware
interrupt to occur if the LOTC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when the device detects a clock at FTCLK. The HRCLK checks for the
presence of the FTCLK. On reset, both the LOTC and LORC status bits will be set and then immediately cleared if the clock is present.
Bit 11/Loss Of Receive Clock Detected (LORC). This read-only real-time status bit will be set to a one when the device detects that the HRCLK clock has not toggled for 200ns (±100ns). This bit will be
cleared when a clock is detected at the HRCLK input. The setting of this status bit can cause a hardware interrupt to occur if the LORC bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when the device detects a clock at HRCLK. The FTCLK checks for the
presence of the HRCLK. On reset, both the LOTC and LORC status bits will be set and then immediately cleared if the clock is present.
Bit 12/State of the T3E3MS Input Signal (T3E3MS). This read-only real-time status bit reflects the
current state of the external T3E3MS input signal. This status bit cannot generate an interrupt. Bit 13/State of the G.747E Input Signal (G.747E). This read-only real-time status bit reflects the
current state of the external G.747E input signal. This status bit cannot generate an interrupt.
BERT STATUS BIT FLOW Figure 4.3D
Note: All event and alarm latches above are cleared when the BERTEC0 register is read.
RLOS
(BERTEC0
Bit 4)
Internal RLOS
Signal from
BERTInternal Bit
Error DetectedSignal from
BERT
Internal CounterOverflow
Signal from
BERT
BED
BECO or BBCO
BERT
(IMSR Bit 2)
INT*
Hardware
Signal
BERT
Status Bit
(MSR Bit 2)
IESYNC (BERTC0 Bit 15)
IEBED (BERTC0 Bit 14)
IEOF (BERTC0 Bit 13)
DS3112
HDLC STATUS BIT FLOW Figure 4.3E
Note: All event latches above are cleared when the HSR register is read.
High Water Mark
DS3112
T2E2SR1 STATUS BIT FLOW Figure 4.3F
Note: All event and alarm latches above are cleared when the T2E2SR1 register is read.
LOF1(T2E2SR1
Bit 0)
Internal LOFSignal from
T2/E2 Framer 1
Internal LOF
Signal from
T2/E2 Framer 2
Internal LOF
Signal from
T2 Framer 7
IELOF
(T2E2SR1
Bit 7)
LOF2
(T2E2SR1
Bit 1)
LOF7
(T2E2SR1
Bit 6)
AIS1
(T2E2SR1
Bit 8)
Internal AIS
Signal from
T2/E2 Framer 1
Internal AIS
Signal from
T2/E2 Framer 2
Internal AIS
Signal from
T2 Framer 7
IEAIS
(T2E2SR1
Bit 15)
AIS2
(T2E2SR1
Bit 9)
AIS7
(T2E2SR1
Bit 14)
INT*Hardware
Signal
T2E2SR1
Status Bit
(MSR Bit 5)
DS3112
T2E2SR2 STATUS BIT FLOW Figure 4.3G
Note: All event and alarm latches above are cleared when the T2E2SR2 register is read.
T1LB STATUS BIT FLOW Figure 4.3H
RAI1(T2E2SR2
Bit 0)
Internal RAISignal from
T2/E2 Framer 1
Internal RAI
Signal fromT2/E2 Framer 2
Internal RAI
Signal from
T2 Framer 7
IERAI
(T2E2SR2
Bit 7)
RAI2
(T2E2SR2Bit 1)
RAI7
(T2E2SR2
Bit 6)
T2E2SR2
(IMSR Bit 6)
INT*Hardware
Signal
T2E2SR2
Status Bit
(MSR Bit 6)
LLB1
Internal T1
Loopback CommandSignal from
T2/E2 Framer
T1LB
(IMSR Bit 8)
INT*
Hardware
Signal
T1LB
Status Bit
(MSR Bit 8)
LLB2
Internal T1Loopback Command
Signal from
T2/E2 Framer
LLB28
Internal T1
Loopback Command
Signal fromT2/E2 Framer
DS3112
T3E3SR STATUS BIT FLOW Figure 4.3I
Note: All event and alarm latches above are cleared when the T3E3SR register is read.
Register Name: IMSR
Register Description: Interrupt Mask for Master Status Register
Register Address: 0Ah Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit # 15 14 13 12 11 10 9 8
Name
Default
T3E3SR
(IMSR Bit 9)
INT*
HardwareSignal
T3E3SRStatus Bit
(MSR Bit 9)Receive LOSSignal from
T3/E3 Framer
LOS
(T3E3SR Bit 0)
LOS (IT3E3SR Bit 0)Receive LOF
Signal fromT3/E3 Framer
LOF
(T3E3SR Bit 1)LOF (IT3E3SR Bit 1)Receive AIS
Signal from
T3/E3 Framer
AIS
(T3E3SR Bit 2)
AIS (IT3E3SR Bit 2)Receive RAI
Signal from
T3/E3 Framer
AIS
(T3E3SR Bit 3)
AIS (IT3E3SR Bit 3)Receive IdleSignal from
T3/E3 Framer
T3IDLE
(T3E3SR Bit 4)
T3IDLE (IT3E3SR Bit 4)Receive Start
Of FrameSignal from
T3/E3 Framer
RSOF
RSOF (IT3E3SR Bit 5)Transmit Start
Of Frame
Signal from
T3/E3 Framer
TSOF
TSOF (IT3E3SR Bit 6)
DS3112
Bit 0/One-Second Timer Boundary Occurrence (OST). 0 = interrupt masked 1 = interrupt unmasked Bit 1/Counter Overflow Event (COVF). 0 = interrupt masked 1 = interrupt unmasked
Bit 2/Change in BERT Status (BERT). 0 = interrupt masked 1 = interrupt unmasked Bit 3/Change in HDLC Status (HDLC). 0 = interrupt masked 1 = interrupt unmasked
Bit 4/Change in FEAC Status (FEAC). 0 = interrupt masked 1 = interrupt unmasked
Bit 5/Change in T2/E2 LOF or AIS Status (T2E2SR1). 0 = interrupt masked 1 = interrupt unmasked
Bit 6/Change in T2/E2 RAI Status (T2E2SR2). 0 = interrupt masked 1 = interrupt unmasked
Bit 8/T1 Loopback Detected (T1LB). 0 = interrupt masked 1 = interrupt unmasked Bit 9/Change in T3/E3 Framer Status (T3E3SR). 0 = interrupt masked 1 = interrupt unmasked
Bit 10/Loss Of Transmit Clock (LOTC). 0 = interrupt masked 1 = interrupt unmasked
Bit 11/Loss Of Receive Clock (LORC). 0 = interrupt masked 1 = interrupt unmasked
DS3112
4.4 Test Register Description
Register Name: TEST
Register Description: Test Register Register Address: 0Ch
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 5/Factory Test Bits (FT0 to FT5). These bits are used by the factory to place the DS3112 into
the test mode. For normal device operation, these bits should be set to zero whenever this register is
written to.
DS3112
5. T3/E3 FRAMER
5.1 General Description
On the receive side, the T3/E3 framer locates the frame boundaries of the incoming T3 or E3 data stream
and monitors the data stream for alarms and errors. Alarms are detected and reported in T3/E3 Status Register (T3E3SR) and the T3/E3 Information Register (T3E3INFO), which are described in Section 5.3.
Errors are accumulated in a set of error counters (Section 5.4). The host can force the T3/E3 framer to
resynchronize via the T3E3RSY control bit in the MRID register (Section 4.1). On the transmit side, the
device formats the outgoing data stream with the proper framing pattern and overhead and can generate
alarms. It can also inject errors for diagnostic testing purposes (T3E3EIC register). The transmit side of the framer is called the “formatter.”
The T3/E3 framer and formatter can be used in conjunction with the multiplexer or as a standalone
framer. This selection is made in the Master Configuration 1 (MC1) register (Section 4.2).
T3/E3 Line Loopback
The line loopback loops the incoming T3/E3 data (the HRCLK, HRPOS, and HRNEG inputs) directly back to the transmit side (the HTCLK, HTPOS, and HTNEG outputs). When this loopback is enabled, the
incoming receive data continues to pass through the device but the data output from the T3/E3 formatter
is replaced with the data being input to the device. See the block diagrams in Section 1 for a visual
description of this loopback.
T3/E3 Diagnostic Loopback
The diagnostic loopback loops the outgoing T3/E3 data from the T3/E3 formatter back to receive side framer. When this loopback is enabled, the incoming receive data at HRCLK, HRPOS, and HRNEG is
ignored. See the block diagrams in Section 1 for a visual description of this loopback. Please note that the
device can still generate AIS at the HTCLK, HTPOS, and HTNEG outputs when this loopback is invoked. This is important to keep the data that is being looped back from disturbing downstream
equipment.
T3/E3 Payload Loopback
The payload loopback loops the framed T3/E3 data from the receive side framer back to the transmit side
formatter. When this loopback is enabled, the incoming receive data continues to pass through the device
but the data normally being input to the T3/E3 formatter is ignored. See the block diagrams in Section 1 for a visual description of this loopback.
DS3112
5.2 T3/E3 FRAMER CONTROL REGISTER DESCRIPTION
Register Name: T3E3CR
Register Description: T3/E3 Control Register Register Address: 10h
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write.
Bit 0/T3/E3 Transmit Alarm Indication Signal (TAIS). When this bit is set high in the T3 mode, the
transmitter will generate a properly F-bit and M-bit framed 101010... data pattern with both X bits set to
one, all C bits set to zero, and the proper P bits. This is true regardless of whether the device is in the C-Bit Parity mode or not. When this bit is set high in the E3 mode, the transmitter will generate an
unframed all ones. When this bit it set low, normal data is transmitted. 0 = do not transmit AIS 1 = transmit AIS Bit 1/T3/E3 Transmit Remote Alarm Indication (TRAI). When this bit is set high in the T3 mode,
both X bits will be set to a zero. When this bit is set high in the E3 mode, the RAI bit (bit number 11 of
each E3 frame) will be set to a one. When this bit it set low in the T3 mode, both X bits will be set to one.
When this bit is set low in the E3 mode, the RAI bit will be set to a zero. 0 = do not transmit RAI 1 = transmit RAI
Bit 2/T3/E3 Transmit Pass Through Enable (TPT). 0 = enable the framer to insert framing and overhead bits 1 = framer will not insert any framing or overhead bits
Bits 3 and 4/E3 National Bit Control Bits 0 and 1 (E3SnC0 and E3SnC1). These bits determine from
where the E3 national bit is sourced. On the receive side, the Sn bit is always routed to the T3E3INFO
Register as well as the HDLC controller and the FEAC controller. These bits are ignored in the T3 mode.
DS3112
Bit 5/Transmit T3 Idle Signal Enable (T3IDLE). When this bit is set high, the T3 Idle Signal will be
transmitted instead of the normal transmit data. The T3 Idle Signal is defined as a normally T3 framed pattern (i.e., with the proper F bits and M bits along with the proper P bits) where the information bit
fields are completely filled with a data pattern of ...1100... and the C bits in Subframe 3 are set to zero and both X bits are set to one. This bit is ignored in the E3 mode. 0 = transmit data normally 1 = transmit T3 Idle Signal
Bit 6/T3/E3 Line Loopback Enable (LLB). See Figures 1A and 1B for a visual description of this loopback. 0 = disable loopback 1 = enable loopback
Bit 7/T3/E3 Diagnostic Loopback Enable (DLB). See Figures 1A and 1B for a visual description of this loopback. 0 = disable loopback 1 = enable loopback
Bit 8/E3 Code Violation Enable (E3CVE). This bit is ignored in the T3 mode. This bit is used in the E3 mode to configure the BiPolar Violation Count Register (BPVCR) to count either BiPolar Violations
(BPV) or Code Violations (CV). A BPV is defined as consecutive pulses (or marks) of the same polarity
that are not part of a HDB3 code word. A CV is defined in ITU O.161 as consecutive BPVs of the same polarity. 0 = count BPV 1 = count CV
Bits 9 and 10/T3/E3 Frame Error Counting Control Bits 0 and 1 (FECC0 and FECC1).
DS3112
Bit 11/Error Counting Control (ECC). This bit is used to control whether the device will increment the
error counters during Loss Of Frame (LOF) conditions. It only affects the error counters that count errors that are based on framed information and these include the following:
§ Frame Error Counter (when it is configured to count frame errors, not LOF occurrences) § T3 Parity Bit Error Counter
§ T3 C-Bit Parity Error Counter
§ T3 Far End Block Error or E3 RAI Counter
When this bit is set low, these error counters will not be allowed to increment during LOF conditions. When this bit is set high, these error counters will be allowed to increment during LOF conditions. 0 = stop the FECR/PCR/CPCR/FEBECR error counters from incrementing during LOF 1 = allow the FECR/PCR/CPCR/FEBECR error counters to increment during LOF
Bit 12/Automatic FEBE Defeat (AFEBED). This bit is ignored in the E3 mode and in the T3 mode when the device is not configured in the C-Bit Parity Mode. When this bit is low, the device will
automatically insert the FEBE codes into the transmitted data stream by setting all three C bits in
Subframe 4 to zero. 0 = automatically insert FEBE codes in the transmit data stream based on detected errors 1 = use the TFEBE control to determine the state of the FEBE codes
Bit 13/Transmit FEBE Setting (TFEBE). This bit is only active when AFEBED is active (i.e.,
AFEBED = 1). When this bit is low, the device will force the FEBE code to 111 continuously. When this bit is set high, the device will force the FEBE code to 000 continuously. 0 = force FEBE to 111 (null state) 1 = force FEBE to 000 (active state)
Bit 14/T3/E3 Payload Loopback Enable (PLB). See Figures 1A and 1B for a visual description of this loopback. 0 = disable loopback 1 = enable loopback
DS3112
Register Name: T3E3EIC
Register Description: T3/E3 Error Insert Control Register Register Address: 18h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/BiPolar Violation Insert (BPVI). A zero to one transition on this bit will cause a single BPV to be
inserted into the transmit data stream. Once this bit has been toggled from a 0 to a 1, the device waits for
the next occurrence of three consecutive ones to insert the BPV. This bit must be cleared and set again for a subsequent error to be inserted. Toggling this bit has no affect when the T3/E3 interface is in the
Unipolar Mode (Section 4.2 for details about the Unipolar Mode). In the manual error insert mode (MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long as this bit is set
high. When this bit is set low, no errors will be inserted. Bit 1/EXcessive Zero Insert (EXZI). A zero to one transition on this bit will cause a single EXZ event
to be inserted into the transmit data stream. An EXZ event is defined as three or more consecutive zeros in the T3 mode and four or more consecutive zeros in the E3 mode. Once this bit has been toggled from a
zero to a one, the device waits for the next possible B3ZS/HDB3 code word insertion and it suppresses
that code word from being inserted and hence this creates the EXZ event. This bit must be cleared and set again for a subsequent error to be inserted. Toggling this bit has no affect when the T3/E3 interface is in
the Unipolar Mode (Section 4.2 for details about the Unipolar Mode). In the Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long as this bit is set
high. When this bit is set low, no errors will be inserted. Bit 2/T3 Parity Bit Error Insert (T3PBEI). A zero to one transition on this bit will cause a single T3
parity error event to be inserted into the transmit data stream. A T3 parity event is defined as flipping the proper polarity of both the P bits in a T3 Frame. (See Section 15.2 for details about the P bits.) Once this
bit has been toggled from a zero to a one, the device waits for the next T3 frame to flip both P bits. This
bit must be cleared and set again for a subsequent error to be inserted. Toggling this bit has no affect when the device is operated in the E3 mode. In the Manual Error Insert mode (MEIMS = 1), errors will
be inserted on each toggle of the FTMEI input signal as long as this bit is set high. When this bit is set low, no errors will be inserted.
DS3112
Bit 3/T3 C-Bit Parity Error Insert (T3CPBEI). A zero to one transition on this bit will cause a single
T3 C-Bit parity error event to be inserted into the transmit data stream. A T3 parity event is defined as flipping the proper polarity of all three CP bits in a T3 Frame. (See Section 15.2 for details about the CP
bits.) Once this bit has been toggled from a zero to a one, the device waits for the next T3 frame to flip the three CP bits. This bit must be cleared and set again for a subsequent error to be inserted. Toggling
this bit has no affect when the T3 framer is not operated in the C-Bit parity mode (See Section 4.2 for
details about the C-Bit Parity mode.) or when the device is operated in the E3 mode. In the Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle of the FTMEI input signal as long as this
bit is set high. When this bit is set low, no errors will be inserted.
Bit 4/Frame Bit Error Insert (FBEI). A zero to one transition on this bit will cause the transmit framer
to generate framing bit errors. The type of framing bit errors inserted is controlled by the FBEIC0 and FBEIC1 bits (see discussion below). Once this bit has been toggled from a 0 to a 1, the device waits for
the next possible framing bit to insert the errors. This bit must be cleared and set again for a subsequent error to be inserted. In the Manual Error Insert mode (MEIMS = 1), errors will be inserted on each toggle
of the FTMEI input signal as long as this bit is set high. When this bit is set low, no errors will be
inserted.
Bits 5 and 6/Frame Bit Error Insert Control Bits 0 and 1 (FBEIC0 and FBEIC1).
Bit 7/Manual Error Insert Mode Select (MEIMS). When this bit is set low, the device will insert errors
on each 0 to 1 transition of the BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bits. When this bit is set
high, the device will insert errors on each 0 to 1 transition of the FTMEI input signal. The appropriate
BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bit must be set to one for this to occur. If all of the BPVI, EXZI, T3PBEI, T3CPBEI, and FBEI control bits are set to zero, no errors are inserted. 0 = use zero to one transition on the BPVI, EXZI, T3PBEI, T3CPBEI, or FBEI control bits to insert
errors 1 = use zero to one transition on the FTMEI input signal to insert errors
DS3112
5.3 T3/E3 Framer Status and Interrupt Register Description
Register Name: T3E3SR
Register Description: T3/E3 Status Register Register Address: 12h
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default Note: See Figure 5.3A for details on the signal flow for the status bits in the T3E3SR register. Bits that are underlined are read-only; all other bits are read-write.
Bit 0/Loss Of Signal Occurrence (LOS). This latched read-only alarm-status bit will be set to a one
when the T3 or E3 framer detects a loss of signal. This bit will be cleared when read unless a LOS condition still exists. A change in state of the LOS can cause a hardware interrupt to occur if the LOS bit
in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt
Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read.
The LOS alarm criteria is described in Tables 5.3A and 5.3B. Bit 1/Loss Of Frame Occurrence (LOF). This latched read-only alarm status bit will be set to a one
when the T3 or E3 framer detects a loss of frame. This bit will be cleared when read unless a LOF
condition still exists. A change in state of the LOF can cause a hardware interrupt to occur if the LOF bit
in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt
Mask for MSR (IMSR) register is set to a one. The interrupt will be allowed to clear when this bit is read. The LOF alarm criteria is described in Tables 5.3A and 5.3B.
Bit 2/Alarm Indication Signal Detected (AIS). This latched read-only alarm-status bit will be set to a
one when the T3 or E3 framer detects an incoming Alarm Indication Signal. This bit will be cleared when
read unless an AIS signal is still present. A change in state of the AIS detection can cause a hardware interrupt to occur if the AIS bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and
the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The interrupt will be
allowed to clear when this bit is read. The AIS alarm detection criteria is described in Tables 5.3A and
5.3B.
DS3112
Bit 3/Remote Alarm Indication Detected (RAI). This latched read-only alarm status bit will be set to a
one when the T3 or E3 framer detects an incoming Remote Alarm Indication (RAI) signal. This bit will be cleared when read unless an RAI signal is still present. A change in state of the RAI detection can
cause a hardware interrupt to occur if the RAI bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one. The
interrupt will be allowed to clear when this bit is read. The RAI alarm detection criteria is described in
Tables 5.3A and 5.3B. RAI can also be indicated via the FEAC codes when the device is operated in the C-Bit Parity Mode. Bit 4/T3 Idle Signal Detected (T3IDLE). This latched read-only alarm status bit will be set to a one
when the T3 framer detects an incoming idle signal. This bit will be cleared when read unless the idle
signal is still present. A change in state of idle detection can cause a hardware interrupt to occur if the IDLE bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one. The IDLE detection criteria is described in Table 5.3A. The interrupt will be allowed to clear when this bit is read. When the DS3112 is operated in the E3
mode, this status bit should be ignored. Bit 5/Transmit T3/E3 Start Of Frame (TSOF). This latched read-only event-status bit will be set to a
one on each T3/E3 transmit frame boundary. This bit is a software version of the FTSOF hardware signal and it will be cleared when read. The setting of this bit can cause a hardware interrupt to occur if the
TSOF bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the
Interrupt Mask for MSR (IMSR) register is set to a one.
Bit 6/Receive T3/E3 Start Of Frame (RSOF). This latched read-only event status bit will be set to a one
on each T3/E3 receive frame boundary. This bit is a software version of the FRSOF hardware signal and
it will be cleared when read. The setting of this bit can cause a hardware interrupt to occur if the RSOF
bit in the Interrupt Mask for T3E3SR (IT3E3SR) register is set to a one and the T3E3SR bit in the Interrupt Mask for MSR (IMSR) register is set to a one.
DS3112
T3E3SR STATUS BIT FLOW Figure 5.3A
Note: All event and alarm latches above are cleared when the T3E3SR register is read.
INT*
Hardware Signal
T3E3SR
Status Bit
(MSR Bit 9) Receive LOS Signal from
T3/E3 Framer
LOS
(T3E3SR Bit 0)
LOS (IT3E3SR Bit 0) Receive LOF
Signal from T3/E3 Framer
LOF (T3E3SR Bit 1)
LOF (IT3E3SR Bit 1) Receive AIS
Signal from
T3/E3 Framer
AIS
(T3E3SR Bit 2)
AIS (IT3E3SR Bit 2) Receive RAI
Signal from
T3/E3 Framer
RAI
(T3E3SR Bit 3)
RAI (IT3E3SR Bit 3) Receive Idle Signal from
T3/E3 Framer
T3IDLE
(T3E3SR Bit 4)
T3IDLE (IT3E3SR Bit 4) Receive Start
Of Frame Signal from
T3/E3 Framer
TSOF
TSOF (IT3E3SR Bit 5) Transmit Start
Of Frame
Signal from T3/E3 Framer
RSOF
RSOF (IT3E3SR Bit 6)
DS3112
Register Name: IT3E3SR
Register Description: Interrupt Mask for T3/E3 Status Register Register Address: 14h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write. Bit 0/Loss Of Signal Occurrence (LOS). 0 = interrupt masked 1 = interrupt unmasked
Bit 1/Loss Of Frame Occurrence (LOF). 0 = interrupt masked 1 = interrupt unmasked Bit 2/Alarm Indication Signal Detected (AIS). 0 = interrupt masked 1 = interrupt unmasked
Bit 3/Remote Alarm Indication Detected (RAI). 0 = interrupt masked 1 = interrupt unmasked
Bit 4/T3 Idle Signal Detected (T3IDLE). 0 = interrupt masked 1 = interrupt unmasked Bit 5/Transmit T3/E3 Start Of Frame (TSOF). 0 = interrupt masked 1 = interrupt unmasked
Bit 6/Receive T3/E3 Start Of Frame (RSOF). 0 = interrupt masked 1 = interrupt unmasked
DS3112
T3 ALARM CRITERIA Table 5.3A
Note 1: RAI can also be indicated via FEAC codes in the C-Bit Parity Mode
Note 2: LOS is not defined for unipolar (binary) operation.
DS3112
E3 ALARM CRITERIA Table 5.3B
Note: LOS is not defined for unipolar (binary) operation.
Register Name: T3E3INFO
Register Description: T3/E3 Information Register Register Address: 16h
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write. The status bits in the T3E3INFO cannot cause a hardware interrupt to occur.
Bit 0/Change Of Frame Alignment Detected (COFA). This latched read-only event-status bit will be
set to a one when the T3/E3 framer has experienced a change of frame alignment (COFA). A COFA occurs when the device achieves synchronization in a different alignment than it had previously. If the
device has never acquired synchronization before, then this status bit is meaningless. This bit will be
cleared when read and will not be set again until the framer has lost synchronization and reacquired
synchronization in a different alignment. Bit 1/Zero Suppression Code Word Detected (ZSCD). This latched read-only event-status bit will be
set to a one when the T3/E3 framer has detected a B3ZS/HDB3 code word. This bit will be cleared when
read and will not be set again until the framer has detected another B3ZS/HDB3 code word.
DS3112
Bit 2/F Bit or FAS Error Detected (FBE). This latched read-only status bit will be set to a one when
the DS3112 has detected an error in either the F bits (T3 mode) or the FAS word (E3 mode). This bit will be cleared when read and will not be set again until the device detects another error. Bit 3/M Bit Error Detected (MBE). This latched read-only event status bit will be set to a one when the
DS3112 has detected an error in the M bits. This bit will be cleared when read and will not be set again
until the device detects another error in one of the M bits. This status bit has no meaning in the E3 mode and should be ignored. Bit 4/EXcessive Zeros Detected (EXZ). This latched read-only event status bit will be set to a one each
time the DS3112 has detected a consecutive string of either three or more zeros (T3 mode) or four or
more zeros (E3 mode). This bit will be cleared when read and will not be set again until the device detects another EXcessive Zero event. Bit 5/Severely Errored Framing Event Detected (SEFE). This latched read-only event-status bit will
be set to a one each time the DS3112 has detected either three or more F bits in error out of 16
consecutive F bits (T3 mode) or four bad FAS words in a row (E3 mode). This bit will be cleared when read and will not be set again until the device detects another SEFE event. Bit 8/E3 National Bit (E3Sn). This read-only real-time status bit reports the incoming E3 National Bit
(Sn). It is loaded at the start of each E3 frame as the Sn bit is decoded. The host can use the RSOF status
bit in the T3/E3 Status Register (T3E3SR) to determine when to read this bit.
Bit 9/T3 Application ID Channel Status (T3AIC). This read-only real-time status bit can be used to
help determine whether an incoming T3 data stream is in C-Bit Parity mode or M23 mode. In C-Bit
Parity mode, it is recommended that the first C bit in each M frame be set to one. In M23 mode, the first
C bit in each M frame should be toggling between zero and one to indicate that the bits need to be stuffed or not. This bit will be set to a one when the device detects that the first C bit in the M frame is set to one
for 1020 times or more out of 1024 consecutive M frames (109ms). It will be allowed to be cleared when
the device detects that the first C bit is set to one less than 1020 times out of 1024 consecutive M frames
(109ms). This status bit has no meaning in the E3 mode and should be ignored. Bit10/Loss Of Signal Clear Detected (LOSC). This latched read-only event-status bit will be set to a
one each time the T3/E3 framer exits a Loss Of Signal (LOS) state. This bit will be cleared when read and
will not be set again until the device once again exits the LOS state. The LOS alarm criteria is described
in Tables 5.3A and 5.3B. This status bit is useful in helping the host determine if the LOS persists as
defined in ANSI T1.231.
Bit11/Loss Of Frame Clear Detected (LOFC). This latched read-only event-status bit will be set to a
one each time the T3/E3 framer exits a Loss Of Frame (LOF) state. This bit will be cleared when read and
will not be set again until the device once again exits the LOF state. The LOF alarm criteria is described
in Tables 5.3A and 5.3B. This status bit is useful in helping the host determine if the LOF persists as defined in ANSI T1.231.
DS3112
Bit12/Alarm Indication Signal Clear Detected (AISC). This latched read-only event status bit will be
set to a one each time the T3/E3 framer no longer detects the AIS alarm state. This bit will be cleared when read and will not be set again until the device once again exits the AIS alarm state. The AIS alarm
criteria is described in Tables 5.3A and 5.3B. This status bit is useful in helping the host determine if the AIS persists as defined in ANSI T1.231.
Bit13/Remote Alarm Indication Clear Detected (RAIC). This latched read-only event-status bit will be set to a one each time the T3/E3 framer no longer detects the RAI alarm state. This bit will be cleared
when read and will not be set again until the device once again exits the RAI alarm state. The RAI alarm criteria is described in Tables 5.3A and 5.3B. This status bit is useful in helping the host determine if the
RAI persists as defined in ANSI T1.231.
5.4 T3/E3 Performance Error Counters
There are six error counters in the DS3112. All of the errors counters are 16 bits in length. The host has three options as to how these errors counters are updated. The device can be configured to automatically
update the counters once a second or manually via either an internal software bit (MECU) or an external
signal (FRMECU). See Section 4.2 for details. All the error counters saturate when full and will not
rollover. Register Name: BPVCR
Register Description: BiPolar Violation Count Register
Register Address: 20h
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/16-Bit BiPolar Violation Counter (BPV0 to BPV15). These bits report the number of BiPolar Violations (BPV). In the E3 Mode, this counter can also be configured via the E3CVE bit in the
T3E3 Control Register (Section 5.2) to count Code Violations (CV). A BPV is defined as consecutive
pulses (or marks) of the same polarity that are not part of a B3ZS/HDB3 code word. A CV is defined in
ITU O.161 as consecutive BPVs of the same polarity.
DS3112
Register Name: EXZCR
Register Description: EXcessive Zero Count Register Register Address: 22h
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/16-Bit EXcessive Zero Counter (EXZ0 to EXZ15). These bits report the number of EXcessive Zero occurrences (EXZ). An EXZ occurrence is defined as three or more consecutive zeros in
the T3 mode and four or more consecutive zeros in the E3 mode. As an example, a string of eight
consecutive zeros would only increment this counter once.
Register Name: FECR
Register Description: Frame Error Count Register
Register Address: 24h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15 / 16-Bit Framing Bit Error Counter (FE0 to FE15). These bits report either the number of
Loss Of Frame (LOF) occurrences or the number of framing bit errors received. The FECR is configured
via the host by the Frame Error Counting Control Bits (FECC0 and FECC1) in the T3E3 Control Register (Section 5.2). The possible configurations are shown below.
DS3112
When the FECR is configured to count LOF occurrences, the FECR increments by one each time the
device loses receive synchronization. When the FECR is configured to count framing bit errors, it can be configured via the ECC control bit in the T3/E3 Control Register (Section 5.2) to either continue counting
frame bit errors during a LOF or not.
Register Name: PCR
Register Description: T3 Parity Bit Error Count Register Register Address: 26h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 15/16-Bit T3 Parity Bit Error Counter (PE0 to PE15). These bits report the number of T3
parity bit errors. In the E3 mode, this counter is meaningless and should be ignored. A parity bit error is
defined as an occurrence when the two parity bits do not match one another or when the two Parity Bits do not match the parity calculation made on the information bits. Via the ECC control bit in the T3/E3
Control Register (Section 5.2), the PCR can be configured to either continue counting parity bit errors during a LOF or not.
Register Name: CPCR
Register Description: T3 C-Bit Parity Bit Error Count Register
Register Address: 28h
Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit # 15 14 13 12 11 10 9 8
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
DS3112
Bits 0 to 15/16-Bit T3 C-Bit Parity Bit Error Counter (CPE0 to CPE15). These bits report the
number of T3 C-bit parity bit errors. When the device is not in the C-bit parity mode or when the device is in the E3 mode, this counter is meaningless and should be ignored. A C-bit parity bit error is defined as
an occurrence when the majority decoded three CP parity bits do not match the parity calculation made on the information bits. Via the ECC control bit in the T3/E3 control register (Section 5.2), the CPCR can
be configured to either continue counting C-bit parity bit errors during a LOF or not. Register Name: FEBECR
Register Description: T3 Far End Block Error or E3 RAI Count Register Register Address: 2Ah
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 15/16-Bit T3 Far End Block Error or E3 RAI Counter (FEBE0 to FEBE15). In the T3 C-bit parity mode, these bits report the number of T3 Far End Block Errors (FEBE). This counter
increments each time the three FEBE bits do not equal 111. In the E3 Mode, these bits report the number of times the RAI bit is received in the “disturbed state” (i.e., the number of times that it is set to a one). In
the T3 mode, when the device is not in the C-bit parity mode, this counter is meaningless and should be
ignored. Via the ECC control bit in the T3/E3 control register (Section 5.2), the FEBECR can be configured to either continue counting FEBEs or active RAI bits during a LOF or not.
DS3112
6. M13/E13/G.747 MULTIPLEXER AND T2/E2/G.747 FRAMER
6.1 General Description
Note: If the DS3112 is used as a standalone T3/E3 framer and the multiplexer functionality is disabled, then the registers and functionality described in this section are not applicable and should be ignored by
the host.
On the receive side, the T2/E2/G.747 framer locates the frame boundaries of the incoming T2/E2/G.747
data stream and monitors the data stream for alarms and errors. Alarms are detected and reported in
T2/E2 Status Registers (T2E2SR1 and T2E2SR2), which are described in Section 6.3. The host can force the T2/E2/G.747 framer to resynchronize via the T2E2RSY control bit in the MRID register (Section
4.1). On the transmit side, the device formats the outgoing data stream with the proper framing pattern
and overhead and can generate alarms. It can also inject errors for diagnostic testing purposes. The
transmit side of the framer is called the “formatter.”
T1/E1 AIS Generation
The DS3112 can generate an Alarm Indication Signal (AIS) for the T1 and E1 data streams in both the
transmit and receive directions. AIS for T1 and E1 signals is defined as an unframed all ones pattern. On
reset, the DS3112 will force AIS in both the transmit and receive directions on all 28 T1 and 16/21 E1
data streams. It is the host’s task to configure the device to pass normal traffic via the T1E1RAIS1,
T1E1RAIS2, T1E1TAIS1, and T1E1TAIS2 registers (Section 6.4).
6.2 T2/E2/G.747 Framer Control Register Description
Register Name: T2E2CR1
Register Description: T2/E2 Control Register 1 Register Address: 30h Bit # 7 6 5 4 3 2 1 0
Name
Default
Bit # 15 14 13 12 11 10 9 8
Name
Default Note: Bits that are underlined are read-only; all other bits are read-write.
DS3112
Bits 0 to 6/T2/E2/G.747 Transmit Remote Alarm Indication (TRAIn where n = 1 to 7). When this
bit is set high in the T3 mode, the X bit will be set to zero. When this bit is set high in the E3 mode, the RAI bit (bit number 11 of each E2 frame) will be set to a one. In the E3 mode, TRAI5 to TRAI7 (bits 4 to
6) are disabled and should be set low by the host. When this bit is set high in the G.747 mode, the RAI bit (bit number 1 of Set 2 in each G.747 frame) will be set to a one. When this bit it set low in the T3 mode,
the X bit will be set to a one. When this bit is set low in the E3 and G.747 modes, the RAI bit will be set
to zero. 0 = do not transmit RAI 1 = transmit RAI
Bits 8 to 14/T2/E2/G.747 Transmit Alarm Indication Signal (TAISn where n = 1 to 7). When this bit
is set high, the transmit formatter will generate an unframed all ones pattern. When this bit it set low, normal data is transmitted. In the E3 mode, TAIS5 to TAIS7 (bits 4 to 6) are disabled and should be set
low by the host. 0 = do not transmit AIS 1 = transmit AIS Register Name: T2E2CR2
Register Description: T2/E2 Control Register 2 Register Address: 32h
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default
Note: Bits that are underlined are read-only; all other bits are read-write.
Bits 0 to 6/T2/E2/G.747 Transmit Loss Of Frame Generation (LOFGn where n = 1 to 7). A zero to one transition on this bit will cause the T2/E2/G.747 transmit formatter to generate enough framing bit
errors to cause the far end to lose frame synchronization. This bit must be cleared and set again for a subsequent set of errors to be generated.
Bits 8 to 11 / E2 Transmit National Bit Setting (E2Snn where n = 1 to 4). These bits are ignored in the T3 and G.747 modes. The received Sn can be read from the T2E2 Status Register 2. 0 = force the Sn bit to zero 1 = force the Sn bit to one
DS3112
6.3 T2/E2/G.747 Framer Status And Interrupt Register Description Register Name: T2E2SR1
Register Description: T2/E2 Status Register 1
Register Address: 34h Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default Note: See Figure 6.3A for details on the signal flow for the status bits in the T2E2SR1 register. Bits that are underlined are read-only; all other bits are read-write. Bits 0 to 6/Loss Of Frame Occurrence (LOFn when n = 1 to 7). This latched read-only alarm-status
bit will be set to a one each time the corresponding T2/E2/G.747 framer detects a Loss Of Frame (LOF). This bit will be cleared when read unless a LOF condition still exists in that T2/E2/G.747 framer. A
change in state of the LOF in one or more of the T2/E2/G.747 framers can cause the T2E2SR1 status bit (in the MSR register) to be set and a hardware interrupt to occur if the IELOF bit is set to a one and the
T2E2SR1 bit in the Interrupt Mask for MSR (IMSR) register is set to a one (Figure 6.3A). The interrupt
will be allowed to clear when this bit is read. The LOF alarm criteria is described in Tables 6.3A, 6.3B, and 6.3C. In the E3 mode, LOF5 to LOF7 (bits 4 to 6) are meaningless and should be ignored. Bit 7/Interrupt Enable for Loss of Frame Occurrence (IELOF). This bit should be set to one if the host wishes to have T2/E2/G.747 LOF occurrences cause a hardware interrupt or the setting of the
T2E2SR1 status bit in the MSR register (Figure 6.3A). The T2E2SR1 bit in the Interrupt Mask for the
Master Status Register (IMSR) must also be set to one for an interrupt to occur. 0 = interrupt masked 1 = interrupt unmasked
Bits 8 to 14/Alarm Indication Signal Detected (AISn when n = 1 to 7). This latched read-only alarm-status bit will be set to a one each time the corresponding T2/E2/G.747 framer detects an incoming AIS
alarm. This bit will be cleared when read unless the AIS alarm still exists in that T2/E2/G.747 framer. A change in state of the AIS detector in one or more of the T2/E2/G.747 framers can cause the T2E2SR1
status bit (in the MSR register) to be set and a hardware interrupt to occur if the IEAIS bit is set to a one
and the T2E2SR1 bit in the Interrupt Mask for MSR (IMSR) register is set to a one (Figure 6.3A). The interrupt will be allowed to clear when this bit is read. The AIS alarm criteria is described in Tables 6.3A,
6.3B, and 6.3C. In the E3 mode, AIS5 to AIS7 (bits 4 to 6) are meaningless and should be ignored. Bit 15/Interrupt Enable for Alarm Indication Signal (IEAIS). This bit should be set to one if the host
wishes to have T2/E2/G.747 AIS detection occurrences cause a hardware interrupt or the setting of the
T2E2SR1 status bit in the MSR register (Figure 6.3A). The T2E2SR1 bit in the Interrupt Mask for the Master Status Register (IMSR) must also be set to one for an interrupt to occur. 0 = interrupt masked 1 = interrupt unmasked
DS3112
T2E2SR1 STATUS BIT FLOW Figure 6.3A
Note: All event and alarm latches above are cleared when the T2E2SR1 register is read. Register Name: T2E2SR2
Register Description: T2/E2 Status Register 2 Register Address: 36h
Bit # 7 6 5 4 3 2 1 0
Name
Default Bit # 15 14 13 12 11 10 9 8
Name
Default Note: See Figure 6.3B for details on the signal flow for the status bits in the T2E2SR2 register. Bits that are underlined are read-only; all other bits are read-write.
LOF1(T2E2SR1
Bit 0)
Internal LOFSignal from
T2/E2 Framer 1
Internal LOF
Signal from
T2/E2 Framer 2
Internal LOF
Signal from
T2 Framer 7
IELOF
(T2E2SR1
Bit 7)
LOF2
(T2E2SR1
Bit 1)
LOF7
(T2E2SR1
Bit 6)
AIS1
(T2E2SR1
Bit 8)
Internal AIS
Signal from
T2/E2 Framer 1
Internal AIS
Signal from
T2/E2 Framer 2
Internal AIS
Signal from
T2 Framer 7
IEAIS
(T2E2SR1
Bit 15)
AIS2
(T2E2SR1
Bit 9)
AIS7
(T2E2SR1
Bit 14)
T2E2SR1
(IMSR Bit 5)
INT*Hardware
Signal
T2E2SR1
Status Bit
(MSR Bit 5)
DS3112
Bits 0 to 6/Remote Alarm Indication Signal Detected (RAIn when n = 1 to 7). This latched read-only
alarm-status bit will be set to a one each time the corresponding T2/E2/G.747 framer detects an incoming RAI alarm. This bit will be cleared when read unless the RAI alarm still exists in that T2/E2/G.747
framer. A change in state of the RAI in one or more of the T2/E2/G.747 framers can cause the T2E2SR2 status bit (in the MSR register) to be set and a hardware interrupt to occur if the IERAI bit is set to a one
and the T2E2SR2 bit in the Interrupt Mask for MSR (IMSR) register is set to a one (Figure 6.3B). The
interrupt will be allowed to clear when this bit is read. The RAI alarm criteria is described in Tables 6.3A, 6.3B, and 6.3C. In the E3 mode, RAI5 to RAI7 (bits 4 to 6) are meaningless and should be ignored. Bit 7/Interrupt Enable for Remote Alarm Indication Signal (IERAI). This bit should be set to one if
the host wishes to have RAI detection occurrences cause a hardware interrupt or the setting of the
T2E2SR2 status bit in the MSR register (Figure 6.3B). The T2E2SR2 bit in the Interrupt Mask for the Master Status Register (IMSR) must also be set to one for an interrupt to occur. 0 = interrupt masked 1 = interrupt unmasked
Bits 8 to 11/E2 Receive National Bit (E2Snn when n = 1 to 4). This read-only real-time status bit reports the incoming E2 National Bit (Sn). It is loaded at the start of each E2 frame as the Sn bit is
decoded. The host can use the E2SOF status bit to determine when to read this bit. In the T3 and G.747 modes, this bit is meaningless and should be ignored. This bit cannot cause an interrupt to occur.
Bits 12 to 15/E2 Receive Start Of Frame (E2SOFn where n = 1 to 4). This latched read-only event-status bit will be set to a one on each E2 receive frame boundary. This bit will be cleared when read. The
setting of this status bit cannot cause an interrupt to occur.
T2E2SR2 STATUS BIT FLOW Figure 6.3B
Note: All event and alarm latches above are cleared when the T2E2SR2 register is read.
RAI1(T2E2SR2
Bit 0)
Internal RAISignal from
T2/E2 Framer 1
Internal RAI
Signal fromT2/E2 Framer 2
Internal RAI
Signal from
T2 Framer 7
IERAI
(T2E2SR2
Bit 7)
RAI2
(T2E2SR2Bit 1)
RAI7
(T2E2SR2
Bit 6)
T2E2SR2
(IMSR Bit 6)
INT*Hardware
Signal
T2E2SR2
Status Bit
(MSR Bit 6)
