DS3112N+ ,TEMPE T3 E3 Multiplexer, 3.3V T3/E3 Framer and M13/E13/G.747 MUXFEATURES FUNCTIONAL DIAGRAM Operates as M13 or E13 Multiplexer or as Stand-Alone T3 or E3 Framer ..
DS3112RD ,DS3/E3 Multiplexer Reference DesignFEATURES The DS3112RD is a reference design for the DS3112 Soldered DS3150 and DS3112 DS3/E3 fra ..
DS31256 ,256-Channel, High-Throughput HDLC ControllerFEATURES The DS31256 Envoy is a 256-channel HDLC 256 Independent, Bidirectional HDLC controller th ..
DS31256+ ,256-Channel, High-Throughput HDLC ControllerFEATURES6 2. DETAILED DESCRIPTION....7 3. SIGNAL DESCRIPTION ......13 3.1 OVERVIEW/SIGNAL LIST.13 3 ..
DS3131 ,40-Port, Unchannelized Bit-Synchronous HDLCAPPLICATIONS Routers ORDERING INFORMATION xDSL Access Multiplexers (DSLAMs) Clear-Channel (unchan ..
DS3131DK ,Bit-SynchronouS (BoSS) HDLC Controller Demo KitAPPLICATIONS Routers ORDERING INFORMATION xDSL Access Multiplexers (DSLAMs) PART TEMP RANGE PIN-PA ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS3112+-DS3112N+
TEMPE T3 E3 Multiplexer, 3.3V T3/E3 Framer and M13/E13/G.747 MUX
FEATURES � Operates as M13 or E13 Multiplexer or as
Stand-Alone T3 or E3 Framer � Flexible Multiplexer can be Programmed for
Multiple Configurations Including:
M13 Multiplexing (28 T1 Lines into a T3
Data Stream)
E13 Multiplexing (16 E1 Lines into an E3
Data Stream)
E1 to T3 Multiplexing (21 E1 Lines into a T3
Data Stream) � Two T1/E1 Drop and Insert Ports � Supports T3 C-Bit Parity Mode � B3ZS/HDB3 Encoder and Decoder � Generates and Detects T3/E3 Alarms � Generates and Detects T2/E2 Alarms � Integrated HDLC Controller Handles LAPD
Messages Without Host Intervention � Integrated FEAC Controller � Integrated BERT Supports Performance
Monitoring � T3/E3 and T1/E1 Diagnostic (Tx to Rx), Line
(Rx to Tx), and Payload Loopback
Supported � Nonmultiplexed or Multiplexed 16-Bit
Control Port (with Optional 8-Bit Mode) � 3.3V Supply with 5V Tolerant I/O � Available in 256-Pin 1.27mm Pitch PBGA
Package � IEEE 1149.1 JTAG Support
DS3112
TEMPE T3/E3 Multiplexer
3.3V T3/E3 Framer and M13/E13/G.747 Mux
FUNCTIONAL DIAGRAM
APPLICATIONS Wide Area Network Access Equipment
PBXs
Access Concentrators
Digital Cross-Connect Systems
Switches
Routers
Optical Multiplexers
ADMs
Test Equipment
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS3112 0°C to +70°C 256 PBGA
DS3112+ 0°C to +70°C 256 PBGA
DS3112N -40°C to +85°C 256 PBGA
DS3112N+-40°C to +85°C 256 PBGA
+Denotes lead-free/RoHS-compliant package.
T1/E1
T1/E1
T1/E1
T1/E1
T1/E1
T1/E1
T1/E1
T1/E1
T3/E3
T2/E2
T2/E2
DS3112
DS3112
TABLE OF CONTENTS DETAILED DESCRIPTION 7 1.1 APPLICABLE STANDARDS..............................................................................................................8
1.2 MAIN DS3112 TEMPE FEATURES................................................................................................9
1.2.1 General Features...................................................................................................................................9
1.2.2 T3/E3 Framer.........................................................................................................................................9
1.2.3 T2/E2 Framer.........................................................................................................................................9
1.2.4 HDLC Controller.....................................................................................................................................9
1.2.5 FEAC Controller.....................................................................................................................................9
1.2.6 BERT....................................................................................................................................................10
1.2.7 Diagnostics...........................................................................................................................................10
1.2.8 Control Port..........................................................................................................................................10
1.2.9 Packaging and Power..........................................................................................................................10
PIN DESCRIPTION 14 2.2 CPU BUS SIGNAL DESCRIPTION.................................................................................................19
2.3 T3/E3 RECEIVE FRAMER SIGNAL DESCRIPTION...........................................................................21
2.4 T3/E3 TRANSMIT FORMATTER SIGNAL DESCRIPTION...................................................................23
2.5 LOW-SPEED (T1 OR E1) RECEIVE PORT SIGNAL DESCRIPTION....................................................25
2.6 LOW-SPEED (T1 OR E1) TRANSMIT PORT SIGNAL DESCRIPTION..................................................26
2.7 HIGH-SPEED (T3 OR E3) RECEIVE PORT SIGNAL DESCRIPTION...................................................28
2.8 HIGH-SPEED (T3 OR E3) TRANSMIT PORT SIGNAL DESCRIPTION.................................................28
2.9 JTAG SIGNAL DESCRIPTION.......................................................................................................29
2.10 SUPPLY, TEST, RESET, AND MODE SIGNAL DESCRIPTION............................................................29
MEMORY MAP 31 MASTER DEVICE CONFIGURATION AND STATUS/INTERRUPT 33 4.1 MASTER RESET AND ID REGISTER DESCRIPTION.........................................................................33
4.2 MASTER CONFIGURATION REGISTERS DESCRIPTION...................................................................34
4.3 MASTER STATUS AND INTERRUPT REGISTER DESCRIPTION..........................................................38
4.3.1 Status Registers...................................................................................................................................38
4.3.2 MSR.....................................................................................................................................................39
4.4 TEST REGISTER DESCRIPTION....................................................................................................47
T3/E3 FRAMER 48 5.1 T3/E3 LINE LOOPBACK...............................................................................................................48
5.2 T3/E3 DIAGNOSTIC LOOPBACK...................................................................................................48
5.3 T3/E3 PAYLOAD LOOPBACK........................................................................................................48
5.4 T3/E3 FRAMER CONTROL REGISTER DESCRIPTION.....................................................................49
5.5 T3/E3 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION...............................................53
5.6 T3/E3 PERFORMANCE ERROR COUNTERS..................................................................................59
M13/E13/G.747 MULTIPLEXER AND T2/E2/G.747 FRAME 62 6.1 T1/E1 AIS GENERATION.............................................................................................................62
6.2 T2/E2/G.747 FRAMER CONTROL REGISTER DESCRIPTION..........................................................62
6.3 T2/E2/G.747 FRAMER STATUS AND INTERRUPT REGISTER DESCRIPTION....................................64
6.4 T1/E1 AIS GENERATION CONTROL REGISTER DESCRIPTION.......................................................68
T1/E1 LOOPBACK AND DROP AND INSERT FUNCTIONALITY 70 7.1 T1/E1 LINE LOOPBACK...............................................................................................................70
7.2 T1/E1 DIAGNOSTIC LOOPBACK...................................................................................................70
7.3 T1 LINE LOOPBACK COMMAND....................................................................................................70
DS3112
7.6 T1 LINE LOOPBACK COMMAND STATUS REGISTER DESCRIPTION.................................................75
7.7 T1/E1 DROP AND INSERT CONTROL REGISTER DESCRIPTION......................................................76
BERT 78 8.1 BERT REGISTER DESCRIPTION..................................................................................................78
HDLC CONTROLLER 87 9.1 RECEIVE OPERATION..................................................................................................................87
9.2 TRANSMIT OPERATION................................................................................................................87
9.2 HDLC CONTROL AND FIFO REGISTER DESCRIPTION..................................................................88
9.3 HDLC STATUS AND INTERRUPT REGISTER DESCRIPTION.............................................................91
10 FEAC CONTROLLER 96 10.1 FEAC CONTROL REGISTER DESCRIPTION...................................................................................96
10.2 FEAC STATUS REGISTER DESCRIPTION......................................................................................98
11 JTAG 99 11.1 TAP CONTROLLER STATE MACHINE DESCRIPTION....................................................................100
11.1.1 Test-Logic-Reset...........................................................................................................................101
11.1.2 Run-Test-Idle.................................................................................................................................101
11.1.3 Select-DR-Scan.............................................................................................................................101
11.1.4 Capture-DR....................................................................................................................................101
11.1.5 Shift-DR.........................................................................................................................................101
11.1.6 Exit1-DR.........................................................................................................................................101
11.1.7 Pause-DR......................................................................................................................................101
11.1.8 Exit2-DR.........................................................................................................................................101
11.1.9 Update-DR.....................................................................................................................................101
11.1.10 Select-IR-Scan...............................................................................................................................101
11.1.11 Capture-IR.....................................................................................................................................102
11.1.12 Shift-IR...........................................................................................................................................102
11.1.13 Exit1-IR..........................................................................................................................................102
11.1.14 Pause-IR........................................................................................................................................102
11.1.15 Exit2-IR..........................................................................................................................................102
11.1.16 Update-IR.......................................................................................................................................102
11.2 INSTRUCTION REGISTER AND INSTRUCTIONS.............................................................................103
11.2.1 SAMPLE/PRELOAD......................................................................................................................103
11.2.2 EXTEST.........................................................................................................................................103
11.2.3 BYPASS.........................................................................................................................................103
11.2.4 IDCODE.........................................................................................................................................103
11.2.5 HIGHZ............................................................................................................................................103
11.2.6 CLAMP...........................................................................................................................................104
11.3 TEST REGISTERS......................................................................................................................104
11.3.1 Bypass Register.............................................................................................................................104
11.3.2 Identification Register....................................................................................................................104
11.3.3 Boundary Scan Register................................................................................................................104
12 DC ELECTRICAL CHARACTERISTICS 109
13 AC ELECTRICAL CHARACTERISTICS 110
14 APPLICATIONS AND STANDARDS OVERVIEW 121 14.1 APPLICATION EXAMPLES...........................................................................................................121
14.2 M13 BASICS.............................................................................................................................122
14.3 T2 FRAMING STRUCTURE.........................................................................................................123
14.4 M12 MULTIPLEXING..................................................................................................................123
14.5 T3 FRAMING STRUCTURE.........................................................................................................125
DS3112
14.8 E13 BASICS.............................................................................................................................128
14.9 E2 FRAMING STRUCTURE AND E12 MULTIPLEXING....................................................................129
14.10 E3 FRAMING STRUCTURE AND E23 MULTIPLEXING................................................................129
14.11 G.747 BASICS......................................................................................................................131
14.12 G.747 FRAMING STRUCTURE AND E12 MULTIPLEXING...........................................................132
15 PACKAGE INFORMATION 133 15.1 256-BALL PBGA (56-G6002-001)............................................................................................133
DS3112
LIST OF FIGURES Figure 1-1. DS3112 Framer and Multiplexer Block Diagram (T3 Mode)...................................................................11
Figure 1-2. DS3112 Framer and Multiplexer Block Diagram (E3 Mode)...................................................................12
Figure 1-3. DS3112 Framer and Multiplexer Block Diagram (G.747 Mode).............................................................13
Figure 2-1. T3/E3 Receive Framer Timing................................................................................................................22
Figure 2-2. T3/E3 Transmit Formatter Timing...........................................................................................................24
Figure 4-1. Event Status Bit.......................................................................................................................................38
Figure 4-2. Alarm Status Bit.......................................................................................................................................38
Figure 4-3. Real-Time Status Bit...............................................................................................................................39
Figure 4-4. BERT Status Bit Flow..............................................................................................................................41
Figure 4-5. HDLC Status Bit Flow..............................................................................................................................42
Figure 4-6. T2E2SR1 Status Bit Flow........................................................................................................................43
Figure 4-7. T2E2SR2 Status Bit Flow........................................................................................................................44
Figure 4-8. T1LB Status Bit Flow...............................................................................................................................44
Figure 4-9. T3E3SR Status Bit Flow..........................................................................................................................45
Figure 5-1. T3E3SR Status Bit Flow..........................................................................................................................54
Figure 6-1. T2E2SR1 Status Bit Flow........................................................................................................................65
Figure 6-2. T2E2SR2 Status Bit Flow........................................................................................................................66
Figure 7-1. T1LBSR1 and T1LBSR2 Status Bit Flow................................................................................................76
Figure 8-1. BERT Status Bit Flow..............................................................................................................................86
Figure 9-1. HSR Status Bit Flow................................................................................................................................94
Figure 11-1. JTAG Block Diagram.............................................................................................................................99
Figure 11-2. TAP Controller State Machine.............................................................................................................100
Figure 13-1. Low-Speed (T1 and E1) Port AC Timing Diagram..............................................................................111
Figure 13-2. High-Speed (T3 and E3) Port AC Timing Diagram.............................................................................112
Figure 13-3. Framer (T3 and E3) Port AC Timing Diagram.....................................................................................113
Figure 13-4. Intel Read Cycle (Nonmultiplexed)......................................................................................................115
Figure 13-5. Intel Write Cycle (Nonmultiplexed)......................................................................................................115
Figure 13-6. Motorola Read Cycle (Nonmultiplexed)..............................................................................................116
Figure 13-7. Motorola Write Cycle (Nonmultiplexed)...............................................................................................116
Figure 13-8. Intel Read Cycle (Multiplexed)............................................................................................................117
Figure 13-9. Intel Write Cycle (Multiplexed)............................................................................................................117
Figure 13-10. Motorola Read Cycle (Multiplexed)...................................................................................................118
Figure 13-11. Motorola Write Cycle (Multiplexed)...................................................................................................118
Figure 13-12. JTAG Test Port Interface AC Timing Diagram..................................................................................119
Figure 13-13. Reset and Manual Error Counter/Insert AC Timing Diagram............................................................120
Figure 14-1. Channelized T3/E3 Application...........................................................................................................121
Figure 14-2. Unchannelized Dual T3/E3 Application...............................................................................................122
Figure 14-3. T2 M-Frame Structure.........................................................................................................................124
Figure 14-4. T2 Stuff Block Structure......................................................................................................................124
Figure 14-5. T3 M-Frame Structure.........................................................................................................................127
Figure 14-6. T3 Stuff Block Structure......................................................................................................................128
Figure 14-7. E2 Frame Structure.............................................................................................................................130
Figure 14-8. E3 Frame Structure.............................................................................................................................130
Figure 14-9. G.747 Frame Structure........................................................................................................................132
