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DS28EC20-DS28EC20P+T
20Kb 1-Wire EEPROM
GENERAL DESCRIPTION The DS28EC20 is a 20480-bit, 1-Wire® EEPROM organized as 80 memory pages of 256 bits each. An additional page is set aside for control functions. Data is written to a 32-byte scratchpad, verified, and then copied to the EEPROM memory. As a special feature, blocks of eight memory pages can be write protected or put in EPROM-Emulation mode, where bits can only be changed from a 1 to a 0 state. The DS28EC20 communicates over the single-conductor 1-Wire bus. The communication follows the standard 1-Wire protocol. Each device has its own unalterable and unique 64-bit ROM registration number. The registration number is used to address the device in a multidrop 1-Wire net environment.
APPLICATIONS Device Authentication IEEE 1451.4 Sensor TEDS Ink/Toner Cartridges Medical Sensors PCB Identification Wireless Base Stations
ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS28EC20+ -40°C to +85°C 3 TO-92
DS28EC20+T -40°C to +85°C 3 TO-92, T&R
DS28EC20P+ -40°C to +85°C 6 TSOC
DS28EC20P+T -40°C to +85°C 6 TSOC, T&R +Denotes a lead(Pb)-free/RoHS-compliant package. T = Tape and reel.
TYPICAL OPERATING CIRCUIT PX.Y µC
VCC I/O DS28EC20 GND
RPUP (300Ω to 2.2kΩ)
FEATURES 20480 Bits of Nonvolatile (NV) EEPROM Partitioned into Eighty 256-Bit Pages Individual 8-Page Groups of Memory Pages (Blocks) can be Permanently Write Protected or Put in OTP EPROM-Emulation Mode ("Write to 0") Read and Write Access Highly Backward-Compatible to Legacy Devices (e.g., DS2433) 256-Bit Scratchpad with Strict Read/Write Protocols Ensures Integrity of Data Transfer 200k Write/Erase Cycle Endurance at +25°C Unique Factory-Programmed 64-Bit Registration Number Ensures Error-Free Device Selection and Absolute Part Identity Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise Communicates to Host at 15.4kbps or 90kbps Using 1-Wire Protocol Low-Cost TO-92 Package Operating Range: 5V ±5%, -40°C to +85°C Operating Range: 3.3V ±5%, 0°C to +70°C (Standard Speed only) IEC 1000-4-2 Level 4 ESD Protection (±8kV Contact, ±15kV Air, Typical) for I/O Pin
PIN CONFIGURATION PIN 1 ---------- GND PIN 2 ---------- I/O PIN 3 ---------- N.C.
28EC20 BOTTOM VIEW 2 3
2 3 FOR TAPE-AND-REEL THE LEADS ARE FORMED TO 100 MILS (2.54mm) SPACING VERSUS 50 MILS (1.27mm) FOR BULK.
TSOC, Top View
PIN 1 ---------- N.C. PIN 2 ---------- I/O PIN 3 ---------- GND PIN 4, 5, 6 ---- N.C.
TO-92
Commands, bytes, and modes are capitalized for clarity. 1-Wire is a registered trademark of Maxim Integrated Products, Inc.
DS28EC20 20Kb 1-Wire EEPROM
DS28EC20: 20Kb 1-Wire EEPROM
ABSOLUTE MAXIMUM RATINGS I/O Voltage to GND -0.5V, +6V I/O Sink Current 20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C Storage Temperature Range -55°C to +125°C Lead Temperature (soldering, 10s) +300°C Soldering Temperature (reflow) TO-92 +250°C TSOC +260°C
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
5.0V SUPPLY ELECTRICAL CHARACTERISTICS (VPUP = 5.0V ±5%, TA = -40°C to +85°C, unless otherwise noted.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O PIN GENERAL DATA 1-Wire Pullup Resistance RPUP (Notes 2, 3) 0.3 2.2 kΩ
Input Capacitance CIO (Notes 4, 5) 2000 pF
Input Load Current IL I/O pin at VPUP 0.05 3.5 µA
High-to-Low Switching Threshold VTL (Notes 5, 6, 7) 1.6 VPUP -1.8 V
Input Low Voltage VIL (Notes 2, 8) 0.5 V
Low-to-High Switching Threshold VTH (Notes 5, 6, 9) 2.5 VPUP -1.1 V
Switching Hysteresis VHY (Notes 5, 6, 10) 0.30 1.30 V
Output Low Voltage VOL At 4mA (Note 11) 0.20 V
Recovery Time (Notes 2, 12) tREC Standard speed 5 µs Overdrive speed 5
Rising-Edge Hold-off Time (Notes 5, 13) tREH Standard speed 0.5 5.0 µs Overdrive speed Not applicable (0)
Timeslot Duration (Notes 2, 14) tSLOT Standard speed 65 µs Overdrive speed 11
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE Reset-Low Time (Note 2) tRSTL Standard speed 480 640 µs Overdrive speed 48 80
Presence-Detect High Time tPDH Standard speed 15 60 µs Overdrive speed 2 6
Presence-Detect Low Time tPDL Standard speed 60 240 µs Overdrive speed 8 24
Presence-Detect Sample Time (Notes 2, 15) tMSP Standard speed 60 75 µs Overdrive speed 6 10
I/O PIN, 1-Wire WRITE Write-0 Low Time (Notes 2, 16, 17) tW0L Standard speed 60 120 µs Overdrive speed 6 15.5
Write-1 Low Time (Notes 2, 17) tW1L Standard speed 1 15 µs Overdrive speed 1 2
I/O PIN, 1-Wire READ Read-Low Time (Notes 2, 18) tRL Standard speed 5 15 - δ µs Overdrive speed 0.800 2 - δ
Read-Sample Time Standard speed tRL + δ 15
DS28EC20: 20Kb 1-Wire EEPROM
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
EEPROM Programming Current IPROG (Note 19) 0.9 mA
Programming Time tPROG (Note 20) 10 ms
Write/Erase Cycles (Endurance) (Notes 21, 22) NCY At +25°C 200k At +85°C (worst case) 50k
Data Retention (Notes 23, 24, 25) tDR At +85°C (worst case) 40 years
Note 1: Limits are 100% production tested at TA = +25°C and/or TA = +85°C. Limits over the operating temperature range and relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2: System requirement.
Note 3: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and current requirements during EEPROM programming. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 4: Typical value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is charged, it does not affect normal communication.
Note 5: Guaranteed by design, characterization and/or simulation only. Not production tested.
Note 6: VTL, VTH, and VHY are a function of the internal supply voltage which is itself a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on I/O. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY.
Note 7: Voltage below which, during a falling edge on I/O, a logic 0 is detected.
Note 8: The voltage on I/O needs to be less or equal to VILMAX at all times the master is driving I/O to a logic 0 level.
Note 9: Voltage above which, during a rising edge on I/O, a logic 1 is detected.
Note 10: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least VHY to be detected as logic 0.
Note 11: The I-V characteristic is approximately linear for voltages less than 1V.
Note 12: Applies to a single device attached to a 1-Wire line.
Note 13: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Note 14: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 15: Interval after tRSTL during which a bus master can read a logic 0 on I/O if there is a DS28EC20 present. The power-up presence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 16: Highlighted numbers are NOT in compliance with legacy 1-Wire product standards. See comparison table below.
Note 17: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 18: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 19: Current drawn from I/O during the EEPROM programming interval. During a programming cycle the voltage at I/O drops by IPROG × RPUP below VPUP. If VPUP and RPUP are within their EC table limits, the residual I/O voltage meets the guaranteed-by-design minimum voltage requirements for programming.
Note 20: The tPROG interval begins tREHMAX after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid copy scratchpad sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL.
Note 21: Write-cycle endurance is degraded as TA increases.
Note 22: Not 100% production-tested; guaranteed by reliability monitor sampling.
Note 23: Data retention is degraded as TA increases.
Note 24: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing.
Note 25: EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C.
LEGACY VALUES DS28EC20 VALUES
PARAMETER STANDARD SPEED OVERDRIVE SPEED# STANDARD SPEED OVERDRIVE SPEED# MIN MAX MIN MAX MIN MAX MIN MAX tSLOT (incl. tREC) 61µs (undefined) 7µs (undefined) 65µs* (undefined) 11µs (undefined)
tRSTL 480µs (undefined) 48µs 80µs 480µs 640µs 48µs 80µs
tPDH 15µs 60µs 2µs 6µs 15µs 60µs 2µs 6µs
tPDL 60µs 240µs 8µs 24µs 60µs 240µs 8µs 24µs
tW0L 60µs 120µs 6µs 16µs 60µs 120µs 6µs 15.5µs
*Intentional change, longer recovery time requirement due to modified 1-Wire front-end. #For operation at overdrive speed, the DS28EC20 requires VPUP to be 5V ±5%.
DS28EC20: 20Kb 1-Wire EEPROM
3.3V SUPPLY ELECTRICAL CHARACTERISTICS (VPUP = 3.3V ±5%, TA = 0°C to +70°C, unless otherwise noted.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
I/O PIN GENERAL DATA 1-Wire Pullup Resistance RPUP (Notes 1, 2) 0.3 2.2 kΩ
Input Capacitance CIO (Notes 3, 4) 2000 pF
Input Load Current IL I/O pin at VPUP 0.05 3.5 µA
High-to-Low Switching Threshold VTL (Notes 4, 5, 6) 0.49 VPUP -1.9 V
Input Low Voltage VIL (Notes 1, 7) 0.5 V
Low-to-High Switching Threshold VTH (Notes 4, 5, 8) 1.09 VPUP -1.1 V
Switching Hysteresis VHY (Notes 4, 5, 9) 0.33 0.70 V
Output Low Voltage VOL At 4mA (Note 10) 0.30 V
Recovery Time tREC Standard speed (Notes 1, 11) 5 µs
Rising-Edge Hold-off Time tREH Standard speed (Notes 4, 12) 0.5 5.0 µs
Timeslot Duration tSLOT Standard speed (Notes 1, 13) 65 µs
I/O PIN, 1-Wire RESET, PRESENCE DETECT CYCLE Reset-Low Time tRSTL Standard speed (Note 1) 480 640 µs
Presence-Detect High Time tPDH Standard speed 15 60 µs
Presence-Detect Low Time tPDL Standard speed 60 240 µs
Presence-Detect Sample Time tMSP Standard speed (Notes 1, 14) 60 75 µs
I/O PIN, 1-Wire WRITE Write-0 Low Time tW0L Standard speed (Notes 1, 15) 60 120 µs
Write-1 Low Time tW1L Standard speed (Notes 1, 15) 1 15 µs
I/O PIN, 1-Wire READ Read-Low Time tRL Standard speed (Notes 1, 16) 5 15 - δ µs
Read-Sample Time tMSR Standard speed (Notes 1, 16) tRL + δ 15 µs
EEPROM Programming Current IPROG (Note 17) 0.9 mA
Programming Time tPROG (Note 18) 10 ms
Write/Erase Cycles (Endu-rance) (Notes 19, 20) NCY At +25°C 200k At +70°C 50k
Data Retention tDR (Notes 21, 22, 23) 40 years
DS28EC20: 20Kb 1-Wire EEPROM
Note 1: System requirement.
Note 2: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system, 1-Wire recovery times, and current requirements during EEPROM programming. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 3: Typical value represents the internal parasite capacitance when VPUP is first applied. Once the parasite capacitance is charged, it does not affect normal communication.
Note 4: Guaranteed by design, characterization and/or simulation only. Not production tested.
Note 5: VTL, VTH, and VHY are a function of the internal supply voltage which is itself a function of VPUP, RPUP, 1-Wire timing, and capacitive loading on I/O. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of VTL, VTH, and VHY.
Note 6: Voltage below which, during a falling edge on I/O, a logic 0 is detected.
Note 7: The voltage on I/O needs to be less or equal to VILMAX at all times the master is driving I/O to a logic 0 level.
Note 8: Voltage above which, during a rising edge on I/O, a logic 1 is detected.
Note 9: After VTH is crossed during a rising edge on I/O, the voltage on I/O has to drop by at least VHY to be detected as logic 0.
Note 10: The I-V characteristic is approximately linear for voltages less than 1V.
Note 11: Applies to a single device attached to a 1-Wire line.
Note 12: The earliest recognition of a negative edge is possible at tREH after VTH has been reached on the preceding rising edge.
Note 13: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 14: Interval after tRSTL during which a bus master can read a logic 0 on I/O if there is a DS28EC20 present. The power-up presence detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 15: ε in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to VTH. The actual maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 16: δ in Figure 11 represents the time required for the pullup circuitry to pull the voltage on I/O up from VIL to the input high threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 17: Current drawn from I/O during the EEPROM programming interval. The pullup circuit on I/O during the programming interval should be such that the voltage at I/O is greater than or equal to 3.0V. For 3.3V±5% VPUP operation of the DS28EC20, a low-impedance bypass of RPUP, which can be activated during programming, is required.
Note 18: The tPROG interval begins tREHMAX after the trailing rising edge on I/O for the last time slot of the E/S byte for a valid copy scratchpad sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the device has returned from IPROG to IL.
Note 19: Write-cycle endurance is degraded as TA increases.
Note 20: Not 100% production-tested; guaranteed by reliability monitor sampling.
Note 21: Data retention is degraded as TA increases.
Note 22: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data sheet limit at operating temperature range is established by reliability testing.
Note 23: EEPROM writes may become nonfunctional after the data retention time is exceeded. Long-time storage at elevated temperatures is not recommended; the device may lose its write capability after 10 years at +125°C or 40 years at +85°C.
DS28EC20: 20Kb 1-Wire EEPROM
PIN DESCRIPTION
NAME FUNCTION I/O 1-Wire Bus Interface. Open drain, requires external pullup resistor.
GND Ground Reference
N.C. Not Connected
DESCRIPTION The DS28EC20 combines 20Kb of data EEPROM with a fully featured 1-Wire interface in a single chip. The memory is organized as 80 pages of 256 bits each. In addition, the device has one page for control functions such as permanent write protection and EPROM-Emulation mode for individual 2048-bit (8-page) memory blocks. A volatile 256-bit memory page called the scratchpad acts as a buffer when writing data to the EEPROM to ensure data integrity. Data is first written to the scratchpad, from which it can be read back for verification before transferring it to the EEPROM. The operation of the DS28EC20 is controlled over the single-conductor 1-Wire bus. Device communication follows the standard 1-Wire protocol. The energy required to read and write the DS28EC20 is derived entirely from the 1-Wire communication line. Each DS28EC20 has its own unalterable and unique 64-bit registration number. The registration number guarantees unique identification and is used to address the device in a multidrop 1-Wire net environment. Multiple DS28EC20 devices can reside on a common 1-Wire bus and be operated independently of each other. Applications of the DS28EC20 include device authentication, analog-sensor calibration such as IEEE-P1451.4 Smart Sensors TEDS, ink and toner print cartridge identification, medical-sensor calibration data storage, PC board identification, and data for self-configuration of central office switches, wireless base stations, PBXs, or other modular-based rack systems. The DS28EC20 provides a high degree of backward compatibility with the DS2433. Besides the different family codes, the only protocol change that is required on an existing DS2433 implementation is a lengthening of the programming duration (tPROG) from 5ms to 10ms.
Figure 1. Block Diagram I/O
64-Bit Registration #
1-Wire Function Control
Memory Function Control Unit
Parasite Power
32-Byte Scratchpad Data Memory 80 Pages of 32 Bytes each
CRC16 Generator
Special Function Registers
DS28EC20 DS28EC20: 20Kb 1-Wire EEPROM
OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the DS28EC20. The DS28EC20 has four main data components: 1) 64-bit registration number, 2) 32-byte scratchpad, 3) eighty 32-byte pages of EEPROM, and 4) special function registers. The hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the seven ROM (network) function commands: 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Skip ROM, 5) Resume, 6) Overdrive Skip ROM, or 7) Overdrive Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all subsequent communication occurs at a higher speed. For operation at overdrive speed, the DS28EC20 requires VPUP to be 5V ±5%. The protocol required for these ROM function commands is described in Figure 9. After a ROM function command is successfully executed, the memory functions become accessible and the master may provide any one of the five memory function commands. The protocol for these commands is described in Figure 7. All data is read and written least significant bit first.
Figure 2. Hierarchical Structure for 1-Wire Protocol DS28EC20 Command Level:
1-Wire ROM Function Commands (see Figure 9)
DS28EC20-Specific Memory Function Commands (see Figure 7)
Available Commands: Data Field Affected:
Read ROM Match ROM Search ROM Skip ROM Resume Overdrive Skip* Overdrive Match*
64-bit Reg. #, RC-Flag 64-bit Reg. #, RC-Flag 64-bit Reg. #, RC-Flag RC-Flag RC-Flag RC-Flag, OD-Flag 64-bit Reg. #, RC-Flag, OD-Flag
Write Scratchpad Read Scratchpad Copy Scratchpad Read Memory Extended Read Mem.
32-byte Scratchpad, Flags 32-byte Scratchpad Data Memory, Register Page Data Memory, Register Page Data Memory, Register Page * For operation at overdrive speed, the DS28EC20 requires VPUP to be 5V ±5%.
64-BIT ROM Each DS28EC20 contains a unique ROM code that is 64 bits long. The first 8 bits are a 1-Wire family code. The next 48 bits are a unique serial number. The last 8 bits are a cyclic redundancy check (CRC) of the first 56 bits. See Figure 3 for details. The 1-Wire CRC is generated using a polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Additional information about the 1-Wire CRC is available in Application Note 27: Understanding and Using Cyclic Redundancy Checks with Maxim iButton® Products (www.maximintegrated.com/AN27). The shift register bits are initialized to 0. Then, starting with the least significant bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered, the serial number is entered. After the last bit of the serial number has been entered, the shift register contains the CRC value. Shifting in the 8 bits of the CRC returns the shift register to all 0s.
Figure 3. 64-Bit ROM MSB LSB
8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (43h)
MSB LSB MSB LSB MSB LSB
DS28EC20: 20Kb 1-Wire EEPROM
Figure 4. 1-Wire CRC Generator 0 X1 X2 X3 X4 X5 X6 X7 X8
Polynomial = X8 + X5 + X4 + 1 st STAGE 2nd STAGE 3rd STAGE 4th STAGE 6th STAGE 5th STAGE 7th STAGE 8th STAGE
INPUT DATA
MEMORY Data memory and special function registers are located in a linear address space, as shown in Figure 5. The data memory and the registers have unrestricted read access. The data memory consists of 80 pages of 32 bytes each. Eight adjacent pages form one 2Kb block. Each block can be individually set to open (default), write protected, or EPROM mode by setting the associated protection byte in the register page, which starts at address 0A00h. Besides the 10 block protection control bytes (one for each 2Kb data memory block) the register page contains 20 bytes of user EEPROM plus a memory block lock byte and a register page lock byte. Starting at address 0A20h, the DS28EC20 has a read-only memory page that stores a factory byte and a 2-byte field reserved for a factory-administered service to program manufacturer identification. All other bytes of that page are reserved. The manufacturer ID can be a customer-supplied identification code that assists the application software in identifying the product the DS28EC20 is associated with. Contact the factory to set up and register a custom manufacturer ID. In addition to the EEPROM, the device has a 32-byte volatile scratchpad. Writes to the EEPROM array are a two-step process. First, data is written to the scratchpad, and then copied into the main array. The user can verify the data in the scratchpad prior to copying. The protection control registers, along with the Memory Block Lock byte, determine whether write protection, EPROM mode, or copy protection is enabled for each of the 10 data memory blocks. A value of 55h sets write protection for the associated memory block. A value of AAh sets EPROM mode. The Memory Block Lock byte, if programmed to either 55h or AAh, sets copy protection for all write-protected data memory blocks. Blocks in EPROM mode are not affected. Programming the Register Page Lock byte to either 55h or AAh copy protects the entire register page. The protection control registers and the Lock bytes write protect themselves if set to 55h or AAh. Any other setting leaves them open for unrestricted write access. See the Copy Protection section for explanation of copy protect vs. write protect.
Write Protection: Write protection prevents data from being changed, but does not block the copy-scratchpad function; this allows the memory to be reprogrammed with the same data. In EEPROM devices digital information is stored as electrical charge (electrons) on floating gates. Quantum mechanical effects allow electrons to be transported in large numbers to and from the floating gate for programming and erasing memory cells. Electrons leave the floating gate at a temperature-dependent rate. The higher the temperature, the faster is the rate at which electrons escape. This rate is expressed as Data Retention in the EC table. Reprogramming the memory returns the charge to the original value for a full data retention time. This is particularly useful in applications where data retention is a concern, e.g., at high temperatures.
Copy Protection: Copy protection blocks the execution of the copy-scratchpad function. This feature achieves a higher level of security, and should only be used after all write-protected locations and their associated protection control bytes are set to their final values. Copy protection does not prevent copying data from one device to another.
DS28EC20: 20Kb 1-Wire EEPROM
Figure 5. Memory Map
ADDRESS RANGE TYPE DESCRIPTION PROTECTION CODES (NOTES) 0000h to 00FFh R/(W) Data Memory Pages 0 to 7 (Block 0) (Protection controlled by address 0A00h)
0100h to 01FFh R/(W) Data Memory Pages 8 to 15 (Block 1) (Protection controlled by address 0A01h)
0200h to 02FFh R/(W) Data Memory Pages 16 to 23 (Block 2) (Protection controlled by address 0A02h)
0300h to 03FFh R/(W) Data Memory Pages 24 to 31 (Block 3) (Protection controlled by address 0A03h)
0400h to 04FFh R/(W) Data Memory Pages 32 to 39 (Block 4) (Protection controlled by address 0A04h)
0500h to 05FFh R/(W) Data Memory Pages 40 to 47 (Block 5) (Protection controlled by address 0A05h)
0600h to 06FFh R/(W) Data Memory Pages 48 to 55 (Block 6) (Protection controlled by address 0A06h)
0700h to 07FFh R/(W) Data Memory Pages 56 to 63 (Block 7) (Protection controlled by address 0A07h)
0800h to 08FFh R/(W) Data Memory Pages 64 to 71 (Block 8) (Protection controlled by address 0A08h)
0900h to 09FFh R/(W) Data Memory Pages 72 to 79 (Block 9) (Protection controlled by address 0A09h)
0A00h* to 0A09h* R/(W) Protection Control Blocks 0 to 9
55h: Write protected; AAh: EPROM mode. Address 0A00h is associated with Block 0, address 0A01h with Block 1, etc.
0A0Ah to 0A1Dh R/(W) User EEPROM (Protection controlled by address 0A1Fh)
0A1Eh* R/(W) Memory Block Lock (See text)
0A1Fh* R/(W) Register Page Lock (See text)
0A20h R Factory Byte (55h no valid manufacturer ID, AAh 0A23h to 0A24h are a valid Manufacturer ID)
0A21h to 0A22h R Factory Trim Bytes (Unspecified value)
0A23h to 0A24h R Manufacturer ID Validity depends on factory byte
0A25h to 0A3Fh R Reserved (Unspecified value)
* Once programmed to AAh or 55h this address becomes read-only. All other codes can be stored but neither write-protect the address nor activate any function.
DS28EC20: 20Kb 1-Wire EEPROM
ADDRESS REGISTERS AND TRANSFER STATUS The DS28EC20 employs three address registers: TA1, TA2, and E/S (Figure 6). Registers TA1 and TA2 must be loaded with the target address to which the data is written or from which data is read. Register E/S is a read-only transfer status register used to verify data integrity with write commands. E/S bits E[4:0] are loaded with the incoming T[4:0] on a Write Scratchpad command and increment on each subsequent data byte. This is, in effect, a byte-ending offset counter within the 32-byte scratchpad. Bit 5 of the E/S register, called PF, is set if the number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due to a loss of power. A valid write to the scratchpad clears the PF bit. Bit 6 has no function; it always reads 0. The highest valued bit of the E/S register, called authorization accepted (AA), is valid only if the PF flag reads 0. If PF is 0 and AA is 1, the data stored in the scratchpad has already been copied to the target memory address. Writing data to the scratchpad clears this flag.
Figure 6. Address Registers Bit # 7 6 5 4 3 2 1 0
Target Address (TA1) T7 T6 T5 T4 T3 T2 T1 T0 Target Address (TA2) T15 T14 T13 T12 T11 T10 T9 T8 Ending Address with Data Status (E/S) (Read Only) AA 0 PF E4 E3 E2 E1 E0
WRITING WITH VERIFICATION To write data to the DS28EC20, the scratchpad must be used as intermediate storage. First, the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be written to the scratchpad. Under certain conditions (see the Write Scratchpad Command section) the master receives an inverted CRC16 of the command, address (actual address sent), and data at the end of the Write Scratchpad command sequence. Knowing this CRC value, the master can compare it to the value it has calculated itself to decide if the communication was successful and precede to the Copy Scratchpad command. If the master could not receive the CRC16, it should send the Read Scratchpad command to verify data integrity. As a preamble to the scratchpad data, the DS28EC20 repeats the target address TA1 and TA2 and sends the contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad or there was a loss of power since data was last written to the scratchpad. The master does not need to continue reading; it can start a new trial to write data to the scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the device did not recognize the Write command. If everything went correctly, both flags are cleared and the ending offset indicates the address of the last byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After the master has verified the data, it can send the Copy Scratchpad command, for example. This command must be followed exactly by the data of the three address registers TA1, TA2, and E/S. The master should obtain the contents of these registers by reading the scratchpad. As soon as the DS28EC20 has received these bytes correctly, it starts copying the scratchpad data to the requested location, provided that the target memory is not copy protected, the PF flag is cleared, and there was no Read Memory or Extended Read Memory command issued between Write Scratchpad and Copy Scratchpad.
DS28EC20: 20Kb 1-Wire EEPROM
MEMORY FUNCTION COMMANDS The Memory Function Flowchart (Figure 7) describes the protocols necessary for accessing the memory of the DS28EC20. The target address registers TA1 and TA2 are used for both read and write. To prevent accidental changes to the data memory or control registers the device employs a BS-flag indicating a “bad sequence”. The communication between master and DS28EC20 takes place either at standard speed (default, OD = 0) or at overdrive speed (OD = 1). If not explicitly set into the Overdrive mode, the DS28EC20 assumes standard speed. For operation at overdrive speed, the DS28EC20 requires VPUP to be 5V ±5%.
WRITE SCRATCHPAD COMMAND [0Fh] The Write Scratchpad command applies to the data memory and the writable addresses in the register page. After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T[4:0]. The E/S bits E[4:0] are loaded with the starting byte offset, and increment with each subsequent byte. Effectively, E[4:0] is the byte offset of the last full byte written to the scratchpad. Only full bytes are accepted. If the last byte is incomplete its content is ignored and the partial byte flag PF is set. The PF flag is also set if the master ends the command before a complete target address is transmitted. The PF and BS flags are both cleared when a complete target address is received. When executing the Write Scratchpad command, the CRC generator inside the DS28EC20 (Figure 13) calculates a 16-bit CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. This CRC is generated using the CRC16 polynomial (X16 + X15 + X2 + 1) by first clearing the CRC generator and then shifting in the command code (0Fh) of the Write Scratchpad command, the target addresses TA1 and TA2 as supplied by the master, and all the data bytes. The master can end the Write Scratchpad command at any time. However, if the end of the scratchpad is reached (E[4:0] = 11111b), the master can send 16 read-time slots to receive the CRC generated by the DS28EC20. If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in memory, rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad is loaded with the bitwise logical AND of the transmitted data and the data already in memory. The DS28EC20’s memory address range is 0000h to 0A3Fh. If the bus master sends a target address higher than this, the DS28EC20’s internal circuitry sets the four most significant address bits to zero as they are shifted into the internal address register. The Read Scratchpad command reveals the modified target address. The master identifies such address modifications by comparing the target address read back to the target address transmitted. If the master does not read the scratchpad, a subsequent Copy Scratchpad command does not work since the most significant bits of the target address the master sends do not match the value the DS28EC20 expects.
READ SCRATCHPAD COMMAND [AAh] The Read Scratchpad command allows verifying the target address and the integrity of the scratchpad data. After issuing the command code, the master begins reading. The first two bytes are the target address. The next byte is the Ending Offset/Data Status byte (E/S) followed by the scratchpad data beginning at the byte offset (T[4:0]). The scratchpad data can be different from what the master originally sent. This is of particular importance if the target address is within the register page or a page in either Write Protection or EPROM modes. See the Write Scratchpad Command section for details. The master should read through the end of the scratchpad, after which it receives an inverted CRC16, based on data as it was sent by the DS28EC20. If the master continues reading after the CRC, all data are logic 1s.
DS28EC20: 20Kb 1-Wire EEPROM
Figure 7-1. Memory Function Flowchart 0Fh Write Scratch- pad
Bus Master TX EEPROM Array Target Address TA1 (T[7:0]), TA2 (T[15:8]) To Figure 7, 2nd Part
From Figure 7, 2nd Part
Bus Master TX Memory Function Command
To ROM Functions Flow Chart (Figure 9)
From ROM Functions Flow Chart (Figure 9)
Master TX Reset
Master TX Data Byte To Scratchpad Offset
DS28EC20 sets Scratch-pad Offset = (T[4:0]), Clears PF, AA, BS
Scrpad. Offset = 11111b
DS28EC20 TX CRC16 of Command, Address, Data Bytes as they were sent by the bus master
DS28EC20 Increments Scratchpad Offset
Master TX Reset Bus Master RX “1”s Partial Byte
PF = 1
If the memory is write-protected, the DS28EC20 copies the data byte from the target address into the scratchpad.
If the memory is in EPROM mode, the DS28EC20 stores the bitwise logical AND of the transmitted byte and the data byte from the targeted address into the scratchpad. DS28EC20 sets (E[4:0]) = Scratchpad Offset
Note: The PF Flag is set upon power-on reset. It is cleared only if a com-plete 16-bit target address is trans-mitted. Sending less than 16 bits for the target address sets the PF flag.
DS28EC20: 20Kb 1-Wire EEPROM
Figure 7-2. Memory Function Flowchart (continued) AAh Read Scratch- Pad
DS28EC20 sets Scratch-pad Offset = (T[4:0])
Bus Master RX TA1 (T[7:0]), TA2 (T[15:8]) and E/S Byte
Bus Master RX Data Byte from Scratchpad Offset
Bus Master RX “1”s Master TX Reset
Master TX Reset
DS28EC20 Increments Scratchpad Offset
Scrpad. Offset = 11111b From Figure 7, 1st Part
To Figure 7, 1st Part
To Figure 7, 3rd Part
From Figure 7, 3rd Part
See note in Write Scratchpad flow chart for additional details.
Bus Master RX CRC16 of Command, Address, E/S Byte, Data Bytes as sent by the DS28EC20
DS28EC20: 20Kb 1-Wire EEPROM
Figure 7-3. Memory Function Flowchart (continued) From Figure 7, 2nd Part
To Figure 7, 2nd Part
To Figure 7, 4th Part
From Figure 7, 4th Part * 1-Wire idle high for tPROG for power
55h Copy Scratch- Pad
Bus Master TX TA1 (T[7:0]), TA2 (T[15:8]) and E/S Byte
Bus Master RX “1”s
Master TX Reset Auth. Code Match
DS28EC20 copies Scratch- pad Data to Address
AA = 1
DS28EC20 TX “0”
Master TX Reset
Master TX Reset
DS28EC20 TX “1”
Copy- Protected PF = 0 BS = 0
