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DS28E10P+
1-Wire SHA-1 Authenticator
DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
219-0009; Rev 2; 4/11
General Description
The DS28E10 combines secure challenge-and-response
authentication functionality based on the FIPS 180-3
specified Secure Hash Algorithm (SHA-1) with 224 bits
of one-time programmable user EPROM in a single
chip. Once written, the memory is automatically write
protected. Additionally, each device has its own guaran-
teed unique 64-bit ROM identification number (ROM ID)
that is factory programmed into the chip. Memory writes
are performed 4 bytes at a time. A secure and low-cost
factory programming service is available to preprogram
device data, including the SHA-1 security data compo-
nents. The device communicates over the single-contact
1-Wire® bus. The communication follows the standard
1-Wire protocol with the ROM ID acting as node address
in the case of a multidevice 1-Wire network.
Applications
Reference Design License Management
System Intellectual Property Protection
Sensor/Accessory Authentication and Calibration
Ordering Information
FeaturesDedicated Hardware-Accelerated SHA-1 Engine
for Generating SHA-1 MACsOne Page of 28 Bytes User OTP EPROMIrreversible Write ProtectionUnique, Factory-Programmed 64-Bit Identification
Number1-Wire Interface for Standard and Overdrive SpeedCommunicates with Host at Up to 15.4kbps at
Standard Speed or Up to 125kbps in Overdrive ModeOperating Range from 2.8V to 3.6V, -40NC to +85NC3-Lead SOT23, 6-Lead TSOC Package±6kV Human Body Model (HBM) ESD Protection
(typ) on 1-Wire and VCC Pin
+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
Typical Operating Circuit
1-Wire is a registered trademark of Maxim Integrated Products, Inc.
EVALUATION KIT
AVAILABLE
RPUP
3.3V
Px.11-Wire
VCCVCC
GNDGND
DS28E10PARTTEMP RANGEPIN-PACKAGE
DS28E10R+T-40NC to +85NC3 SOT23
DS28E10P+-40NC to +85NC6 TSOC
DS28E10P+T-40NC to +85NC6 TSOC
DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
IO Voltage to GND .....................................................-0.5V, +7V
IO Sink Current ...................................................................20mA
VCC Voltage to GND ..................................................-0.5V, +7V
Operating Temperature Range ..........................-40NC to +85NC
Junction Temperature .....................................................+150NC
Storage Temperature Range ............................-55NC to +125NC
Lead Temperature (soldering, 10s) ................................+300NC
Soldering Temperature (reflow) ......................................+260NC
ELECTRICAL CHARACTERISTICS
(TA = -40NC to +85NC, see Note 1.)
ABSOLUTE MAXIMUM RATINGS
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
VCC PIN
Supply Voltage VCCDuring nonprogramming state (Note 2)2.83.6V
Standby Current ICCSVCC = 3.6V0.54.0FA
Operating Current ICCOVCC = 3.6V, reading (Note 3)30FA
IO PIN: GENERAL DATA
1-Wire Pullup VoltageVPUP(Note 4)2.83.6V
1-Wire Pullup Resistance RPUP(Notes 4, 5)0.32.2kI
Input CapacitanceCIO(Note 3)50pF
Input Load Current IL(IO pin at VPUP) (Note 3)2FA
Input Low Voltage VIL(Notes 4, 6, 7)0.3 O VCCV
Input High VoltageVIH(Notes 3, 8)0.7 O VCCV
Switching HysteresisVHY(Notes 3, 9)0.05 O VCCV
Output Low Voltage VOLAt 4mA load (Note 10)0.3V
Recovery Time (Notes 4, 11)tRECStandard speed, RPUP = 2.2kI5FsOverdrive speed, RPUP = 2.2kI2
Rising-Edge Hold-Off Time
(Notes 3, 12)tREHStandard speed0.55FsOverdrive speedNot applicable (0)
Timeslot Duration (Notes 4, 13)tSLOTStandard speed65FsOverdrive speed8
IO PIN: 1-Wire RESET, PRESENCE DETECT CYCLE
Reset Low Time (Note 4)tRSTLStandard speed480640FsOverdrive speed4880
Presence-Detect High TimetPDHStandard speed1560FsOverdrive speed 26
Presence-Detect Low TimetPDLStandard speed60240FsOverdrive speed824
Presence-Detect Sample Time
(Notes 4, 14)tMSPStandard speed6075FsOverdrive speed610
IO PIN: 1-Wire WRITE
Write-Zero Low Time
(Notes 4, 15)tW0LStandard speed60120FsOverdrive Speed616
Write-One Low TimeStandard speed115
DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
ELECTRICAL CHARACTERISTICS (continued)
(TA = -40NC to +85NC, see Note 1.)
Note 1: Specifications at TA = -40NC are guaranteed by design only and not production tested.
Note 2: Refer to the full data sheet for this note.
Note 3: Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 4: System requirement.
Note 5: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery
times. The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
For more heavily loaded systems, an active pullup such as that found in the DS2482-x00 might be required.
Note 6: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 7: The voltage on IO needs to be less than or equal to VILMAX at all times while the master is driving IO to a logic 0 level.
Note 8: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 9: After VIH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic 0.
Note 10: The I-V characteristic is linear for voltages less than 1V.
Note 11: Applies to a single DS28E10 attached to a 1-Wire line.
Note 12: The earliest recognition of a negative edge is possible at tREH after VIH has been reached on the preceding rising edge.
Note 13: Defines maximum possible bit rate. Equal to 1/(tW0LMIN + tRECMIN).
Note 14: Interval after tRSTL during which a bus master is guaranteed to sample a logic 0 on IO if there is a DS28E10 present.
Minimum limit is tPDHMAX; maximum limit is tPDHMIN + tPDLMIN.
Note 15: ε in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VIH. The actual
maximum duration for the master to pull the line low is tW1LMAX + tF - ε and tW0LMAX + tF - ε, respectively.
Note 16: d in Figure 10 represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX + tF.
Note 17: Data retention is degraded as TA increases.
Note 18: Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to
data sheet limit at operating temperature range is established by reliability testing.
Note 19: Refer to the full data sheet for this note.
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITS
IO PIN: 1-Wire READ
Read Low Time
(Notes 4, 16)tRLStandard speed515 - dFsOverdrive speed12 - d
Read Sample Time
(Notes 4, 16)tMSRStandard speedtRL + d15FsOverdrive speedtRL + d2
EPROM
Programming Current IPROGVPP = VPP(MAX) (Note 3)Refer to the full data
sheet.
Programming Time tPPms
Programming VoltageVPP(Note 2)V
Data Retention tDRAt +85NC (Notes 17, 18)10Years
SHA-1 Engine
SHA-1 Computation Current ICCSHAVCC = 3.6VRefer to the full data
sheet.
SHA-1 Computation TimetCSHA(Note 19)ms
DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
Detailed Description
The DS28E10 combines a 512-bit SHA-1 engine, security
data, 224 bits of one-time programmable (OTP) EPROM,
and a 64-bit ROM ID in a single chip. Data is transferred
serially through the 1-Wire protocol, which requires only
a single data lead and a ground return. In addition to its
important use as a unique data value in cryptographic
SHA-1 computations, the device’s 64-bit ROM ID can
be used to electronically identify the equipment in which
the DS28E10 is used. The ROM ID also serves as node
address in a multidrop 1-Wire network environment
where multiple devices reside on a common 1-Wire bus
and operate independently of each other.
Overview
The block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
device. The device has six main data components: 64-bit
ROM ID, security data, challenge buffer, 28 bytes of OTP
user EPROM memory, special function registers, and a
512-bit SHA-1 engine. Figure 2 shows the hierarchical
structure of the 1-Wire protocol. The bus master must
first provide one of the seven ROM (network) function
commands: 1) Read ROM, 2) Match ROM, 3) Search
ROM, 4) Skip ROM, 5) Resume (communication), 6)
Overdrive-Skip ROM or 7) Overdrive-Match ROM. Upon
completion of an Overdrive-Skip ROM or Overdrive-
Match ROM command executed at standard speed,
the device enters overdrive mode where all subsequent
communication occurs at a higher speed. The protocol
required for these ROM function commands is described
in Figure 8. After a ROM function command is success-
fully executed, the memory and SHA-1 functions become
accessible and the master can provide any one of the
six available function commands. The protocol for these
commands is described in Figure 6. All data is read and
written least significant bit first.
Pin Configurations
Pin Description
VCC
GND
N.C.
N.C.
N.C.
TSOCDS28E10
VCCGND
DS28E10
SOT23-3
TOP VIEW
PINNAMEFUNCTIONSOT23TSOC2IO1-Wire Bus Interface. Open drain; requires external pullup resistor.3VCCSupply Pin for Operating Power 1GNDGround Supply for the Device4, 5, 6N.C.Not Connected
DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
Figure 1. Block Diagram
Figure 2. Hierarchical Structure for 1-Wire Protocol
Refer to the full data sheet.
DS28E10
1-Wire FUNCTION
CONTROLIO (1-Wire)
VCC
CRC-16
GENERATOR
64-BIT
ROM ID
CHALLENGE BUFFER
512-BIT
SHA-1 ENGINE
GND
224 BITS USER
MEMORY
REGISTERS
SECURITY DATA
MEMORY AND
SHA-1 FUNCTION
CONTROL UNIT
POWER
DISTRIBUTION
AVAILABLE COMMANDS:DATA FIELD AFFECTED:READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
64-BIT ROM ID, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT ROM ID, RC-FLAG, OD-FLAG
1-Wire ROM
FUNCTION COMMANDS
DEVICE-SPECIFIC MEMORY
FUNCTION COMMANDS
COMMAND LEVEL:DS28E10
MSB
8-BIT
CRC CODE48-BIT SERIAL NUMBER
MSBMSBLSB
LSB
LSB
8-BIT FAMILY CODE
MSBLSB
DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
64-Bit ROM ID
Each device contains a unique ROM ID that is 64 bits
long. The first 8 bits are a 1-Wire family code. The next
48 bits are a unique serial number. The last 8 bits are a
cyclic redundancy check (CRC) of the first 56 bits. See
Figure 3 for details. The 1-Wire CRC is generated using
a polynomial generator consisting of a shift register and
XOR gates as shown in Figure 4. The polynomial is X8 +
X5 + X4 + 1. Additional information about the 1-Wire CRC
is available in Application Note 27: Understanding and
Using Cyclic Redundancy Checks with Maxim iButton®
Products.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After the
last bit of the serial number has been entered, the shift
register contains the CRC value. Shifting in the 8 bits of
the CRC returns the shift register to all 0s.
Memory
The device has three memory areas: user memory, secu-
rity data, and special function registers. User memory
and special function registers are located in a linear
address space, as shown in Figure 5. The user memory
begins at address 0000h and ends at address 0017h.
Refer to the full data sheet for additional information.
The user-writeable memory is implemented in EPROM
technology. The factory-default state of the memory is
00h. During programming, bits of the target 4-byte block
can be changed to a 1 or a 0. Once a block is written,
the entire 4-byte block becomes automatically write pro-
tected. This means it is not possible to program a block
multiple times, e.g., to change a few bits at a time.
Memory and SHA-1 Function
Commands
This section describes the commands and flowcharts
needed to use the memory and SHA-1 engine of the
device. Refer to the full data sheet for more informa-
tion.
Figure 4. 1-Wire CRC Generator
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
7TH
STAGE
8TH
STAGE
6TH
STAGE
5TH
STAGEX1X2X3X4
POLYNOMIAL = X8 + X5 + X4 + 1
INPUT DATAX6X7X8
DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
1-Wire Bus System
The 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances the DS28E10
is a slave device. The bus master is typically a micro-
controller. The discussion of this bus system is broken
down into three topics: hardware configuration, transac-
tion sequence, and 1-Wire signaling (signal types and
timing). The 1-Wire protocol defines bus transactions in
terms of the bus state during specific time slots, which
are initiated on the falling edge of sync pulses from the
bus master.
Hardware Configuration
The 1-Wire bus has only a single line by definition; it is
important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device
attached to the 1-Wire bus must have open-drain or
three-state outputs. The 1-Wire port of the DS28E10
is open drain with an internal circuit equivalent to that
shown in Figure 7.multidrop bus consists of a 1-Wire bus with multiple
slaves attached. The DS28E10 supports both a standard
and overdrive communication speed of 15.4kbps (max)
and 125kbps (max), respectively. The value of the pullup
resistor primarily depends on the network size and load
conditions. The DS28E10 requires a pullup resistor of
2.2kI (max) at any speed.
The idle state for the 1-Wire bus is high. If for any reason
a transaction must be suspended, the bus must be left
in the idle state if the transaction is to resume. If this
does not occur and the bus is left low for more than 16Fs
(overdrive speed) or more than 120Fs (standard speed),
one or more devices on the bus could be reset.
Transaction Sequence
The protocol for accessing the DS28E10 through the
1-Wire port is as follows:
• Initialization
• ROM Function Command
• Memory/SHA-1 Function Command
• Transaction/Data
Initialization
All transactions on the 1-Wire bus begin with an initializa-
tion sequence. The initialization sequence consists of a
reset pulse transmitted by the bus master followed by a
presence pulse(s) transmitted by the slave(s). The pres-
ence pulse lets the bus master know that the DS28E10
is on the bus and is ready to operate. For more details,
see the 1-Wire Signaling section.
1-Wire ROM Function Commands
Once the bus master has detected a presence, it can
issue one of the seven ROM function commands that
the DS28E10 supports. All ROM function commands are
8 bits long. A list of these commands follows (see the
flowchart in Figure 8). Under certain conditions, the ROM
function commands may not operate properly right after
power-up. See the Applications Information section for a
method to ensure proper operation.
Read ROM [33h]
The Read ROM command allows the bus master to read
the DS28E10’s 8-bit family code, unique 48-bit serial
number, and 8-bit CRC. This command can only be used
if there is a single slave on the bus. If more than one
slave is present on the bus, a data collision occurs when
Figure 7. Hardware Configuration
RPUP
VPUP
BUS MASTEROPEN-DRAIN
PORT PIN100Ω MOSFET
DATA
DS28E10 1-Wire PORTRx = RECEIVE
Tx = TRANSMIT
DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
all slaves try to transmit at the same time (open drain
produces a wired-AND result). The resultant family code
and 48-bit serial number result in a mismatch of the CRC.
Match ROM [55h]
The Match ROM command, followed by a 64-bit ROM ID,
allows the bus master to address a specific DS28E10 on
a multidrop bus. Only the DS28E10 that exactly matches
the 64-bit ROM ID responds to the following memory
or SHA-1 function command. All other slaves wait for a
reset pulse. This command can be used with a single or
multiple devices on the bus.
Search ROM [F0h]
When a system is initially brought up, the bus master
might not know the number of devices on the 1-Wire
bus or their ROM ID numbers. By taking advantage of
the wired-AND property of the bus, the master can use process of elimination to identify the ID of all slave
devices. For each bit of the ID number, starting with the
least significant bit, the bus master issues a triplet of
time slots. On the first slot, each slave device participat-
ing in the search outputs the true value of its ID number
bit. On the second slot, each slave device participating
in the search outputs the complemented value of its ID
number bit. On the third slot, the master writes the true
value of the bit to be selected. All slave devices that do
not match the bit written by the master stop participat-
ing in the search. If both of the read bits are zero, the
master knows that slave devices exist with both states of
the bit. By choosing which state to write, the bus master
branches in the search tree. After one complete pass,
the bus master knows the ROM ID number of a single
device. Additional passes identify the ID numbers of the
remaining devices. Refer to Application Note 187: 1-Wire
Search Algorithm for a detailed discussion, including an
example.
Skip ROM [CCh]
This command can save time in a single-drop bus sys-
tem by allowing the bus master to access the memory
or SHA-1 functions without providing the 64-bit ROM
ID. If more than one slave is present on the bus and,
for example, a read command is issued following the
Skip ROM command, data collision occurs on the bus
as multiple slaves transmit simultaneously (open-drain
pulldowns produce a wired-AND result).
Resume Command [A5h]
To maximize the data throughput in a multidrop environ-
ment, the Resume command is available. This command
checks the status of the RC bit and, if it is set, directly
transfers control to the memory and SHA-1 functions,
similar to a Skip ROM command. The only way to set
the RC bit is through successfully executing the Match
ROM, Search ROM, or Overdrive-Match ROM command.
Once the RC bit is set, the device can repeatedly be
accessed through the Resume command. Accessing
another device on the bus clears the RC bit, preventing
two or more devices from simultaneously responding to
the Resume command.
Overdrive-Skip ROM [3Ch]
On a single-drop bus this command can save time by
allowing the bus master to access the memory functions
without providing the 64-bit ROM ID. Unlike the normal
Skip ROM command, the Overdrive-Skip ROM sets the
DS28E10 in the overdrive mode (OD = 1). All communi-
cation following this command must occur at overdrive
speed until a reset pulse of minimum 480Fs duration
resets all devices on the bus to standard speed (OD = 0).
When issued on a multidrop bus, this command sets all
overdrive-supporting devices into overdrive mode. To
subsequently address a specific overdrive-supporting
device, a reset pulse at overdrive speed must be issued
followed by a Match ROM or Search ROM command
sequence. This speeds up the time for the search pro-
cess. If more than one slave supporting overdrive is pres-
ent on the bus and the Overdrive-Skip ROM command
is followed by a read command, data collision occurs on
the bus as multiple slaves transmit simultaneously (open-
drain pulldowns produce a wired-AND result).
Overdrive-Match ROM [69h]
The Overdrive-Match ROM command followed by a
64-bit ROM ID transmitted at overdrive speed allows
the bus master to address a specific DS28E10 on a
multidrop bus and to simultaneously set it in overdrive
mode. Only the DS28E10 that exactly matches the 64-bit
number responds to the subsequent memory or SHA-1
function command. Slaves already in overdrive mode
from a previous Overdrive-Skip ROM or successful
Overdrive-Match ROM command remain in overdrive
mode. All overdrive-capable slaves return to standard
speed at the next reset pulse of minimum 480Fs dura-
tion. The Overdrive-Match ROM command can be used
with a single or multiple devices on the bus.
DS28E10
1-Wire SHA-1 Authenticator
ABRIDGED DATA SHEET
DS28E10 Tx
PRESENCE PULSE
BUS MASTER Tx
RESET PULSE
BUS MASTER Tx ROM
FUNCTION COMMAND
DS28E10 Tx
CRC BYTE
DS28E10 Tx
FAMILY CODE
(1 BYTE)
DS28E10 Tx
SERIAL NUMBER
(6 BYTES)
RC = 0
MASTER Tx BIT 0
RC = 0RC = 0RC = 0
OD = 0Y
33h
READ ROM
COMMAND
55h
MATCH ROM
COMMAND
BIT 0 MATCHBIT 0 MATCHNNN
F0h
SEARCH ROM
COMMAND
RESET PULSE
CCh
SKIP ROM
COMMAND
RC = 1
MASTER Tx BIT 1
MASTER Tx BIT 63
BIT 1 MATCH
BIT 63 MATCH
RC = 1
FROM MEMORY AND SHA-1 FUNCTION
FLOWCHART (FIGURE 6)
TO MEMORY AND SHA-1 FUNCTION
FLOWCHART (FIGURE 6)
DS28E10 Tx BIT 0
DS28E10 Tx BIT 0
MASTER Tx BIT 0
BIT 1 MATCH
BIT 63 MATCH
DS28E10 Tx BIT 1
DS28E10 Tx BIT 1
MASTER Tx BIT 1
DS28E10 Tx BIT 63
DS28E10 Tx BIT 63
MASTER Tx BIT 63
TO FIGURE 8b
TO FIGURE 8b
FROM FIGURE 8b
FROM FIGURE 8b
