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DS28E04-100
4096-Bit Addressable 1-Wire EEPROM with PIO
GENERAL DESCRIPTION The DS28E04-100 is a 4096-bit, 1-Wire® EEPROM
chip with seven address inputs. The address inputs
are directly mapped into the 1-Wire 64-bit Device ID Number to easily enable the host system to identify
the physical location or functional association of the DS28E04-100 in a multidevice 1-Wire network en-
vironment. The 4096-bit EEPROM array is configured as 16 pages of 32 bytes with a 32 byte scratchpad to
perform write operations. EEPROM memory pages can be individually write protected or put in EPROM-
emulation mode, where bits can only be changed from a 1 to a 0 state. In addition to the memory, the
DS28E04-100 has two general-purpose I/O ports that can be used for input or to generate level and/or
pulse outputs. Activity registers also capture port activity for state change monitoring. The DS28E04-
100 communicates over the single-contact 1-Wire bus. The communication follows the standard Dallas
Semiconductor 1-Wire protocol.
APPLICATIONS Autoconfiguration of Modular Systems such as
Central-Office Switches, Cellular Base Stations, Access Products, Optical Network Units, and
PBXs Accessory/PCB Identification
TYPICAL OPERATING CIRCUIT
FEATURES 4096 bits of EEPROM Memory Partitioned into
16 Pages of 256 Bits Seven Address Inputs for Physical Location Configuration Two General-Purpose PIO Pins with Pulse-Generation Capability Individual Memory Pages can be Permanently
Write-Protected or put in OTP EPROM-Emulation Mode (“Write to 0”) Communicates to Host with a Single Digital
Signal at 15.3kbps or 111kbps Using 1-Wire Protocol Parasitic or VCC Powered Conditional Search Based on PIO Status or PIO
Activity Switchpoint Hysteresis and Filtering to Optimize Performance in the Presence of Noise Reads and Writes Over a Wide 2.8V to 5.25V
Voltage Range from -40°C to +85°C 16-Pin, 150-mil SO Package
ORDERING INFORMATION PIN CONFIGURATION
SO (150 mils)
DS28E04-100
4096-Bit Addressable 1-Wire EEPROM
with PIOCommands, Registers, and Modes are capitalized for clarity.
1-Wire is a registered trademark of Dallas Semiconductor Corp.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
ABSOLUTE MAXIMUM RATINGS All Pins: Voltage to GND -0.5V, +6V
All Pins: Sink Current 20mA Operating Temperature Range -40°C to +85°C Junction Temperature +150°C
Storage Temperature Range -40°C to +85°C Soldering Temperature See IPC/JEDEC J-STD-020A
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS (VPUP = 2.8V to 5.25V, VCC = VPUP, floated or grounded, TA = -40°C to +85°C.)
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Note 1: System requirement.
Note 2: Maximum instantaneous pulldown current through all pins combined.
Note 3: Guaranteed by design, simulation only. Not production tested.
Note 4: This load current is caused by the internal weak pullup, which asserts a logical 1 to address pins that are not connected. The
logical state of the address pins must not change during the execution of ROM function commands during those time slots in
which these bits are relevant.
Note 5: The I-V characteristic is linear for voltages less than 1V.
Note 6: Width of the narrowest pulse that trips the activity latch. Back to back pulses that are active for < tPWMIN (max) and that have an
intermediate inactive time < tPWMIN (max) are not guaranteed to be filtered.
Note 7: The Pulse function requires that VCC power is available; otherwise the command will not be executed.
Note 8: Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times. The
specified value here applies to systems with only one device and with the minimum 1-Wire recovery times. For more heavily
loaded systems, an active pullup such as that found in the DS2482-x00, DS2480B, or DS2490 may be required.
Note 9: Capacitance on the data pin could be 800pF when VPUP is first applied. If a 2.2k� resistor is used to pull up the data line, 2.5µs
after VPUP has been applied the parasite capacitance will not affect normal communications.
Note 10: VTL, VTH, and VHY are a function of the internal supply voltage.
Note 11: Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 12: The voltage on IO needs to be less than or equal to VILMAX whenever the master drives the line low.
Note 13: Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 14: After VTH is crossed during a rising edge on IO, the voltage on IO has to drop by at least VHY to be detected as logic '0'.
Note 15: Applies to a single DS28E04-100 without VCC supply, attached to a 1-Wire line.
Note 16: The earliest recognition of a negative edge is possible at tREH after VTH has been previously reached.
Note 18: Interval during the negative edge on IO at the beginning of a Presence Detect pulse between the time at which the voltage is
80% of VPUP and the time at which the voltage is 20% of VPUP.
Note 19: � represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to VTH.
Note 20: � represents the time required for the pullup circuitry to pull the voltage on IO up from VIL to the input high threshold of the bus
master.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Note 21: Current drawn during the EEPROM programming interval. If the device does not get VCC power, the pullup circuit on IO during the
programming interval should be such that the voltage at IO is greater than or equal to VPUP(min). If VPUP in the system is close to
Vpup(min) then a low-impedance bypass of RPUP that can be activated during programming may need to be added.
Note 22: The tPROG interval begins tREHmax after the trailing rising edge on IO for the last time slot of the E/S byte for a valid Copy Scratchpad
sequence. Interval ends once the device's self-timed EEPROM programming cycle is complete and the current drawn by the
device has returned from IPROG to IL or ICCS, respectively.
1) Intentional change, longer recovery time requirement due to modified 1-Wire front end.
PIN DESCRIPTION
DETAILED DESCRIPTION The DS28E04-100 combines 4096 bits of EEPROM, a 16-byte control page, two general-purpose PIO pins, seven
external address pins, and a fully featured 1-Wire interface in a single chip. PIO outputs are configured as open-
drain and provide an on-resistance of 100� max. A robust PIO channel-access communication protocol ensures
that PIO output-setting changes occur error-free. The DS28E04-100 has an additional memory area called the scratchpad that acts as a buffer when writing to the main memory or the control page. Data is first written to the
scratchpad from which it can be read back. The copy scratchpad command transfers the data to its final memory location. Each DS28E04-100 has a device ID number that is 64 bits long. The user can define seven bits of this
number through address pins. The remaining 57 bits are factory-lasered into the chip. The device ID number guarantees unique identification and is used to address the device in a multidrop 1-Wire network environment,
where multiple devices reside on a common 1-Wire bus and operate independently of each other. The DS28E04-100 also supports 1-Wire conditional search capability based on PIO conditions or power-on-reset activity. The
DS28E04-100 has an optional VCC supply connection. When an external supply is absent, device power is supplied parasitically from the 1-Wire bus. When an external supply is present, PIO states are maintained in the absence of
the 1-Wire bus power source. Applications of the DS28E04-100 include autoconfiguration and state monitoring of modular systems such as central-office switches, cellular base stations, access products, optical network units, and
PBXs, and accessory/PC board identification.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
OVERVIEW The block diagram in Figure 1 shows the relationships between the major control and memory sections of the
DS28E04-100. The DS28E04-100 has five main data components: 1) 64-bit device ID number, 2) 32-byte scratchpad, 3) sixteen 32-byte pages of EEPROM, 4) Special Function Register, and 5) PIO Control Registers. The
hierarchical structure of the 1-Wire protocol is shown in Figure 2. The bus master must first provide one of the eight ROM Function Commands, 1) Read ROM, 2) Match ROM, 3) Search ROM, 4) Conditional Search ROM, 5) Skip
ROM, 6) Resume, 7) Overdrive-Skip ROM or 8) Overdrive-Match ROM. Upon completion of an Overdrive ROM command byte executed at standard speed, the device enters Overdrive mode where all subsequent
communication occurs at a higher speed. The protocol required for these ROM function commands is described in Figure 14. After a ROM function command is successfully executed, the memory/control functions become
accessible and the master may provide any one of the nine Memory/Control Function commands. The protocol for these commands is described in Figure 9. All data is read and written least significant bit first.
Figure 1. Block Diagram
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Figure 2. Hierarchical Structure for 1-Wire Protocol 64-BIT DEVICE ID NUMBER (NETWORK ADDRESS)
Each DS28E04-100 has a unique device ID number that is 64 bits long, as shown in Figure 3. The first 8 bits are a 1-Wire family code. The next 8 bits are an external address byte, of which the lower 7 bits are connected to the
address input pins A0 to A6. This allows the user to set a portion of the Device ID Number by connecting some of these pins to GND (logic 0) or to VCC (logic 1) or leaving them open (logic 1). The next 40 bits are a lasered serial
number. Even if multiple DS28E04-100 are used in a 1-Wire network and all address inputs are wired to the same state or left open (unconnected), the unique 40-bit serialization field will prevent any address conflict, allowing to
communicate with each device individually. The last 8 bits are a lasered CRC (Cyclic Redundancy Check) of the first 56 bits, assuming that the address input pins A0 to A6 are at logic 1. The 1-Wire CRC is generated using a
polynomial generator consisting of a shift register and XOR gates as shown in Figure 4. The polynomial is X8 + X5 + X4 + 1. Further information on the Device ID CRC is found in section CRC Generation near the end of this
document. Figure 3. 64-Bit Device ID Number
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Figure 4. 1-Wire CRC Generator MEMORY
The DS28E04-100 EEPROM array consists of 17 pages of 32 bytes each, starting at address 0000h and ending at
address 021Fh. All memory addresses in this range have unrestricted read access. The data memory consists of 16 pages of 32 bytes each. The register page consists of 32 bytes starting at address 0200h. It contains 16 page
protection control bytes (one for each data memory page), the register page lock byte, the factory bytes, and the reserved bytes. The reserved bytes are for future use by the factory and should be not be used. They have no
effect on device operation.
The protection control registers, along with the register page lock byte, determine whether write protection, EPROM mode, or copy protection is enabled for each of the 16 data memory pages. A value of 55h sets write protection for
the associated memory page. A value of AAh sets EPROM mode. A value of 55h or AAh for the register page lock byte sets copy protection for all write-protected data memory pages, as well as the register page. EPROM mode
pages are not affected. The protection control registers and the register page lock byte write protect themselves if set to 55h or AAh. Any other setting leaves them open for unrestricted write access. In addition to the EEPROM, the device has a 32-byte volatile scratchpad. Writes to the EEPROM array are a two-
step process. First, data is written to the scratchpad through the Write Scratchpad command, and then copied into the main array through the Copy Scratchpad command. The user can verify the data written to the scratchpad
through the Read Scratchpad command prior to copying into the main array.
If a memory location is write protected, data sent by the master to the associated address during a Write Scratchpad command is not loaded into the scratchpad. Instead, it is replaced by the data in EEPROM located at
the target address. If a memory location is in EPROM mode, the scratchpad is loaded with the logical AND of the data sent by the master and the data in EEPROM at the target address. Copy Scratchpad commands to write-
protected or EPROM mode memory locations are allowed. This allows write-protected data in the device to be refreshed, i.e., reprogrammed with the current data. If a memory location is copy protected, a Copy Scratchpad command to that location will be blocked, which is
indicated by FFh success bytes. Copy protection is used for a higher level of security, and should only be used after all write-protected pages and their associated protection control bytes are set to their final values. Copy
protection as implemented with this device does not prevent copying data from one device to another; it only blocks the execution of the copy scratchpad command with a target address of a copy-protected memory page.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Figure 5. Memory Map
Address locations 0000h to 021Fh are nonvolatile. Address locations 0220h to 0225 are volatile. Once programmed to AAh or 55h this address becomes read-only. All other codes can be stored but will neither
write-protect the address nor activate any function. Limited write access through Write Register command
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
PIO-RELATED REGISTERS
Figure 6 shows the simplified logic diagram of a PIO channel. The registers related to the PIO pins are located in
the address range 0220h to 0225h. All these registers are volatile, i.e., they lose their state when the device is powered down. All PIO-related registers can be read like any data memory. There are special commands to control
the PIOs for input (read), output (write), pulse-generation, and to reset the activity latches.
Figure 6. PIO Simplified Logic Diagram
PIO Logic State Register
The logic state of the PIO pins can be obtained by reading this register using the Read Memory command. This
register is read-only. Each bit is associated with the pin of the respective PIO channel. Bits 2 to 7 have no function; they always read 1. The data in this register reflects the PIO state at the last (most significant) bit of the byte that
proceeds reading the first (least significant) bit of this register. See the PIO Access Read command description for details.
PIO Output Latch State Register
The data in this register represents the latest data written to the PIOs through the PIO Access Write command.
This register is read using the Read Memory command. This register is not affected if the device re-initializes itself after an ESD hit. This register is read-only. Each bit is associated with the output latch of the respective PIO
channel. Bits 2 to 7 have no function; they always read 1. The flip-flops of this register power up as specified by the state of the POL pin. If the chip has to power up with all PIO channels off, the POL pin must be connected to a logic
"1".
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
PIO Activity Latch State Register
The data in this register represents the current state of the PIO activity latches. This register is read using the Read Memory command. This register is read-only. Each bit is associated with the activity latch of the respective PIO
channel. Bits 2 to 7 have no function; they always read 0. A state transition on a PIO pin, High�Low or Low�High, of a duration greater than tPWMIN causes the associated bit in the register to be set to a 1. This register
is cleared to 00h by a power-on reset, or by successful execution of the Reset Activity Latches command.
The next three registers control the device's participation a Conditional Search ROM sequence. The interaction of the various signals that determine whether the device responds to a conditional search is illustrated in Figure 7.
There is a selection mask, SM, to select the participating PIOs, a polarity selection SP to specify for each channel whether the channel signal needs to be 1 or 0 to qualify, and a PLS bit to select either the activity latches or PIO
pins as inputs. The signals of all channels are fed into an AND gate as well as an OR gate. The CT bit finally selects the AND’ed or OR’ed result as the conditional search response signal CSR. If CT is 0, the channel signal of
at least one of the selected channels must match the corresponding polarity. If CT is 1, the channel signals of all selected channels must match the corresponding polarity. Figure 7. CONDITIONAL SEARCH LOGIC Conditional Search Channel Selection Mask Register
The data in this register controls whether a PIO channel qualifies for participation in the conditional search command. To include a PIO channel, the bits in this register that correspond to those channels need to be set to 1.
This register can only be written through the Write Register command. This register is read/write. Each bit is associated with the respective PIO channel as shown in Figure 7. Bits 2 to 7 have no function; they always read 0
and cannot be changed to 1. This register is cleared to 00h by a power-on reset.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Conditional Search Channel Polarity Selection Register
The data in this register specifies the polarity of each selected PIO channel for the device to respond to the conditional search command. This register can only be written through the Write Registers command. Within a PIO
channel, the data source may be either the channel's input pin or the channel's activity latch, as specified by the PLS bit in the Control/Status register at address 0225h. This register is read/write. Each bit is associated with the
respective PIO channel as shown in Figure 7. Bits 2 to 7 have no function; they always read 0 and cannot be changed to 1. This register is cleared to 00h at power-up.
Control/Status Register
The data in this register reports status information and further configures the device for conditional search. This
register can only be written through the Write Registers command. This register is read/write. The power-up state of the PORL bit is "1". CT and PLS power up as "0". The functional assignments of the individual bits are explained
in the table below. Bits 2, 4, and 5 have no function; they always read 0 and cannot be set to 1.
Control/Status Register Details
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
ADDRESS REGISTERS AND TRANSFER STATUS
The DS28E04-100 employs three address registers, called TA1, TA2, and E/S (Figure 8). Registers TA1 and TA2
must be loaded with the target address to which the data will be written or from which data is read. Register E/S is a read-only transfer-status register, used to verify data integrity of write commands. The lower five bits of the E/S
register indicate the Ending Offset within the 32-byte scratchpad. Bit 5 of the E/S register, called PF, is set if the number of data bits sent by the master is not an integer multiple of 8 or if the data in the scratchpad is not valid due
to a loss of power. A valid write to the scratchpad clears the PF bit. Bit 6 has no function; it always reads 0. Note that the lowest five bits of the target address also determine the address within the scratchpad, where intermediate
storage of data will begin. This address is called byte offset. If the target address (TA1) for a Write command is 03CH for example, then the scratchpad stores incoming data beginning at the byte offset 1CH and is full after only
four bytes. The corresponding ending offset in this example is 1FH. For maximum data bandwidth, the target address for writing should point to the beginning of a new page, i.e., the byte offset is 0. Thus the full 32-byte
capacity of the scratchpad is available, resulting also in the ending offset of 1FH. However, it is possible to write one or several contiguous bytes somewhere within a page. The ending offset together with the partial flag support
the master checking the data integrity after a Write command. The highest valued bit of the E/S register, called AA is valid only if the PF flag reads 0. If PF is 0 and AA is 1, a copy has taken place. Writing data to the scratchpad
clears the AA flag. Figure 8. Address Registers WRITING WITH VERIFICATION
To write data to the DS28E04-100 EEPROM sections, the scratchpad has to be used as intermediate storage. First the master issues the Write Scratchpad command to specify the desired target address, followed by the data to be
written to the scratchpad. Under certain conditions (see Write Scratchpad command) the master will receive an inverted CRC16 of the command, address (actual address sent), and data (as sent by the master) at the end of the
Write Scratchpad command sequence. Knowing this CRC value, the master can compare it to the value it has calculated to decide whether the communication was successful and proceed to the Copy Scratchpad command. If
the master could not receive the CRC16, it should use the Read Scratchpad command to verify data integrity. As a preamble to the scratchpad data, the DS28E04-100 repeats the target address TA1 and TA2 and sends the
contents of the E/S register. If the PF flag is set, data did not arrive correctly in the scratchpad or there was a loss of power since data was last written to the scratchpad. The master does not need to continue reading; it can start a
new trial to write data to the scratchpad. Similarly, a set AA flag together with a cleared PF flag indicates that the device did not recognize the Write command. If everything went correctly, both flags are cleared and the ending
offset indicates the address of the last byte written to the scratchpad. Now the master can continue reading and verifying every data byte. After the master has verified the data, it can send the Copy Scratchpad command. This
command must be followed exactly by the data of the three address registers, TA1, TA2, and E/S. The master should obtain the contents of these registers by reading the scratchpad.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
MEMORY/CONTROL FUNCTION COMMANDS
The Memory/Control Function Flow Chart (Figure 9) describes the protocols necessary to access the memory and
the PIO pins of the DS28E04-100. Examples on how to use these functions are included at the end of this document. The communication between master and DS28E04-100 takes place either at standard speed (default,
OD = 0) or at Overdrive peed (OD = 1). If not explicitly set into the Overdrive Mode, the DS28E04-100 powers up in standard speed.
WRITE SCRATCHPAD COMMAND [0Fh]
The Write Scratchpad command applies to the data memory, and the writeable addresses in the register page.
After issuing the Write Scratchpad command, the master must first provide the 2-byte target address, followed by the data to be written to the scratchpad. The data is written to the scratchpad starting at the byte offset of T4:T0.
The ending offset (E4:E0) is the byte offset at which the master stops writing data. Only full data bytes are accepted. If the last data byte is incomplete, its content will be ignored and the partial byte flag PF will be set. When executing the Write Scratchpad command, the CRC generator inside the DS28E04-100 (Figure 18)
calculates a CRC of the entire data stream, starting at the command code and ending at the last data byte as sent by the master. This CRC is generated using the CRC16 polynomial by first clearing the CRC generator and then
shifting in the command code (0FH) of the Write Scratchpad command, the Target Addresses (TA1 and TA2) as supplied by the master, and all the data bytes. The master may end the Write Scratchpad command at any time.
However, if the end of the scratchpad is reached (E4:E0 = 11111b), the master can send 16 read-time slots and receive the CRC generated by the DS28E04-100. If a Write Scratchpad is attempted to a write-protected location, the scratchpad is loaded with the data already in
memory, rather than the data transmitted. Similarly, if the target address page is in EPROM mode, the scratchpad is loaded with the bitwise logical AND of the transmitted data and data already in memory. READ SCRATCHPAD COMMAND [AAh]
The Read Scratchpad command allows verification of the target address and the scratchpad data. After issuing the
command code, the master begins reading. The first two bytes are the target address. The next byte is the ending offset/data status byte (E/S) followed by the scratchpad data, which may be different from what the master
originally sent. This is of particular importance if the target address is within the register page or a page in either Write-Protected or EPROM modes. See the Write Scratchpad description for details. The master should read
E4:E0-T4:T0+1 bytes, after which it receives the inverted CRC16, based on data as it was sent by the DS28E04-100. If the master continues reading after the CRC, all data will be logic 1s. COPY SCRATCHPAD [55h]
The Copy Scratchpad command is used to copy data from the scratchpad to the data memory and the writable sections of the Register Page. After issuing the Copy Scratchpad command, the master must provide a 3-byte
authorization pattern, which should have been obtained by an immediately preceding Read Scratchpad command. This 3-byte pattern must exactly match the data contained in the three address registers (TA1, TA2, E/S, in that
order). If the pattern matches, the target address is valid, the PF flag is not set, and the target memory is not copy-protected, the AA (Authorization Accepted) flag is set and the copy begins. The data to be copied is determined by
the three address registers. The scratchpad data from the beginning offset through the ending offset will be copied to memory, starting at the target address. Anywhere from 1 to 32 bytes can be copied with this command. The
device’s internal data transfer takes 10ms maximum during which the voltage on the 1-Wire bus must not fall below 2.8V. After waiting 10ms, the master may issue read time slots to receive AAh confirmation bytes until the master
issues a reset pulse. If the PF flag is set or the target memory is copy-protected, the copy will not begin and the AA flag will not be set.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Figure 9-1. Memory/Control Function Flow Chart
From ROM Functions
Flow Chart (Figure 14)
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Figure 9-2. Memory/Control Function Flow Chart (continued)
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Figure 9-3. Memory/Control Function Flow Chart (continued)
memory locations.
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Figure 9-4. Memory/Control Function Flow Chart (continued)
DS28E04-100: 4096-Bit 1-Wire Addressable EEPROM with PIO
Figure 9-5. Memory/Control Function Flow Chart (continued)
