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DS28E02Q-W01+7T
1-Wire SHA-1 Authenticated 1Kb EEPROM with 1.8V Operation
General DescriptionThe DS28E02 combines 1024 bits of EEPROM with
challenge-and-response authentication security imple-
mented with the FIPS 180-3 Secure Hash Algorithm
(SHA-1). The 1024-bit EEPROM array is configured as
four pages of 256 bits with a 64-bit scratchpad to per-
form write operations. All memory pages can be write
protected, and one page can be put in EPROM-emula-
tion mode, where bits can only be changed from a 1 to
a 0 state. Each DS28E02 has its own guaranteed
unique 64-bit ROM registration number that is factory
installed into the chip. The DS28E02 communicates
over the single-contact 1-Wire®bus. The communica-
tion follows the standard 1-Wire protocol with the regis-
tration number acting as the node address in the case
of a multidevice 1-Wire network.
ApplicationsReference Design License Management
System Intellectual Property Protection
Sensor/Accessory Authentication and Calibration
Medical Consumable Authentication
Printer Cartridge Configuration and Monitoring
Features1024 Bits of EEPROM Memory Partitioned Into
Four Pages of 256 BitsOn-Chip 512-Bit SHA-1 Engine to Compute 160-
Bit Message Authentication Codes (MACs) and to
Generate SecretsWrite Access Requires Knowledge of the Secret
and the Capability of Computing and Transmitting
a 160-Bit MAC as AuthorizationUser-Programmable Page Write Protection for
Page 0, Page 3, or All Four Pages TogetherUser-Programmable OTP EPROM Emulation Mode
for Page 1 (“Write to 0”)Communicates to Host with a Single Digital
Signal at 12.5kbps or 35.7kbps Using 1-Wire
ProtocolSwitchpoint Hysteresis and Filtering to Optimize
Communication Performance in the Presence of
NoiseReads and Writes Over 1.75V to 3.65V Voltage
Range from -20°C to +85°C6-Lead TSOC and TDFN Packages
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
Ordering Information219-0008; Rev 1; 3/12
ABRIDGED DATASHEET
PART TEMP RANGE PIN-PACKAGE DS28E02P+ -20°C to +85°C 6 TSOC
DS28E02P+T&R -20°C to +85°C 6 TSOC
DS28E02Q+T&R -20°C to +85°C6 TDFN-EP*
(2.5k pcs)
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
RPUP
VCC
GND
DS28E02
Typical Operating Circuit
DS28E02
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ABRIDGED DATASHEET
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(TA= -20°C to +85°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
IO Voltage Range to GND .......................................-0.5V to +4V
IO Sink Current ...................................................................20mA
Operating Temperature Range...........................-20°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-55°C to +125°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
IO PIN: GENERAL DATA 1-Wire Pullup Voltage VPUP (Note 2) 1.75 3.65 V
1-Wire Pullup Resistance RPUP (Notes 2, 3) 300 750
Input Capacitance CIO (Notes 4, 5) 1500 pF
Input Load Current ILIO pin at VPUP 0.05 5 µA
High-to-Low Switching Threshold VTL(Notes 5, 6, 7) 0.4 VPUP –
0.89 V
Input Low Voltage VIL (Notes 2, 8) 0.30 V
Low-to-High Switching Threshold VTH (Notes 5, 6, 9) 0.74 VPUP –
0.49 V
Switching Hysteresis VHY (Notes 5, 6, 10) 0.26 1.02 V
Output Low Voltage VOL At 4mA current load (Note 11) 0.4 V
Standard speed, RPUP = 75020 Recovery Time (Notes 2, 12) tREC Overdrive speed 20 µs
Standard speed 80 Time Slot Duration (Notes 2, 13) tSLOTOverdrive speed 28 µs
IO PIN: 1-Wire RESET, PRESENCE-DETECT CYCLE Standard speed 480 640 Reset Low Time (Note 2) tRSTL Overdrive speed 50 80 µs
Standard speed 480 Reset High Time (Note 14) tRSTH Overdrive speed 48 µs
Standard speed 60 72 Presence-Detect Sample Time
(Notes 2, 15) tMSPOverdrive speed 7 10 µs
IO PIN: 1-Wire WRITE Standard speed 60 120 Write-Zero Low Time (Notes 2, 16) tW0L Overdrive speed 8 15.5 µs
Standard speed 1 15 Write-One Low Time (Notes 2, 16) tW1L Overdrive speed 1 2 µs
IO PIN: 1-Wire READ Standard speed 5 15 - Read Low Time (Notes 2, 17) tRLOverdrive speed 1 2 - µs
Standard speed tRL + 15 Read Sample Time (Notes 2, 17) tMSROverdrive speed tRL + 2 µs
EEPROM IO voltage < 3.65V 3.5 Programming Current
ELECTRICAL CHARACTERISTICS (continued)(TA= -20°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Programming Time tPROG (Note 19) 25 ms
At +25°C 200,000 Write/Erase Cycles (Endurance)
(Notes 20, 21) NCY At +85°C 50,000 —
Data Retention (Notes 22, 23, 24) tDR At +85°C40 Years
SHA-1 ENGINE Computation Current ILCSHA (Notes 5, 18) mA
Computation Time (Notes 5, 25) tCSHA Refer to full data sheet ms
Note 1:Limits are 100% production tested at TA= +25°C and/or TA= +85°C. Limits over the operating temperature range and
relevant supply voltage range are guaranteed by design and characterization. Typical values are not guaranteed.
Note 2:System requirement.
Note 3:Maximum allowable pullup resistance is a function of the number of 1-Wire devices in the system and 1-Wire recovery times.
The specified value here applies to systems with only one device and with the minimum 1-Wire recovery times.
Note 4:Maximum value represents the internal parasite capacitance when VPUPis first applied. Once the parasite capacitance is
charged, it does not affect normal communication.
Note 5:Guaranteed by design, characterization, and/or simulation only. Not production tested.
Note 6:VTL, VTH, and VHYare a function of the internal supply voltage, which is a function of VPUP, RPUP, 1-Wire timing, and
capacitive loading on IO. Lower VPUP, higher RPUP, shorter tREC, and heavier capacitive loading all lead to lower values of
VTL, VTH, and VHY.
Note 7:Voltage below which, during a falling edge on IO, a logic 0 is detected.
Note 8:The voltage on IO must be less than or equal to VILMAXat all times the master is driving IO to a logic 0 level.
Note 9:Voltage above which, during a rising edge on IO, a logic 1 is detected.
Note 10:After VTHis crossed during a rising edge on IO, the voltage on IO must drop by at least VHYto be detected as logic 0.
Note 11:The I-V characteristic is linear for voltages less than 1V.
Note 12:Applies to a single device attached to a 1-Wire line.
Note 13:Defines maximum possible bit rate. Equal to 1/(tW0LMIN+ tRECMIN).
Note 14:An additional reset or communication sequence cannot begin until the reset high time has expired.
Note 15:Interval after tRSTLduring which a bus master can read a logic 0 on IO if there is a DS28E02 present. The power-up presence
detect pulse could be outside this interval but will be complete within 2ms after power-up.
Note 16:εin Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VILto VTH. The actual
maximum duration for the master to pull the line low is tW1LMAX+ tF- εand tW0LMAX+ tF- ε, respectively.
Note 17:δin Figure 12 represents the time required for the pullup circuitry to pull the voltage on IO up from VILto the input-high
threshold of the bus master. The actual maximum duration for the master to pull the line low is tRLMAX+ tF.
Note 18:Current drawn from IO during the EEPROM programming interval or SHA-1 computation.
Note 19:Refer to full data sheet for this note.
Note 20:Write-cycle endurance is degraded as TAincreases.
Note 21:Not 100% production tested; guaranteed by reliability monitor sampling.
Note 22:Data retention is degraded as TAincreases.
Note 23:Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to the
data sheet limit at operating temperature range is established by reliability testing.
Note 24:EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-term storage at elevated tem-
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
Note 25:Refer to full data sheet for this note.
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ABRIDGED DATASHEET
DS28E02
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ABRIDGED DATASHEET
Pin Description
PIN
TSOCTDFN-EPNAMEFUNCTION1 3 GND Ground Reference 2 IO 1-Wire Bus Interface. Open-drain signal that requires an external pullup resistor.
3, 4, 5, 6 1, 4, 5, 6 N.C. Not Connected
— — EP
Exposed Pad (TDFN Only). Solder evenly to the board’s ground plane for proper
operation. Refer to Application Note 3273: Exposed Pads: A Brief Introduction for
additional information.
Detailed DescriptionThe DS28E02 combines 1024 bits of EEPROM orga-
nized as four 256-bit pages, a 64-bit secret, a register
page, a 512-bit SHA-1 engine, and a 64-bit ROM regis-
tration number in a single chip. Data is transferred seri-
ally through the 1-Wire protocol, which requires only a
single data lead and a ground return. The DS28E02
has an additional memory area called the scratchpad
that acts as a buffer when writing to the memory, the
register page, or when installing a new secret. Data is
first written to the scratchpad from where it can be read
back. After the data has been verified, a copy scratch-
pad command transfers the data to its final memory
location, provided that the DS28E02 receives a match-
ing 160-bit MAC. The computation of the MAC involves
the secret and additional data stored in the DS28E02
including the device’s registration number. The
DS28E02 understands a unique command “Refresh
Scratchpad.” Proper use of a refresh sequence after a
copy scratchpad operation reduces the number of
weak bit failures if the device is used in a touch envi-
ronment (see the Writing with Verificationsection). The
refresh sequence also provides a means to restore
functionality in a device with bits in a weak state.
In addition to its important use as a unique data value in
cryptographic SHA-1 computations, the device's 64-bit
ROM ID guarantees unique identification and can be
used to electronically identify the equipment in which it is
used. The ROM ID is also used to address the device for
the case of a multidrop 1-Wire network environment,
where multiple devices reside on a common 1-Wire bus
and operate independently of each other. Applications of
the DS28E02 include reference design license manage-
ment, system intellectual property protection, accessory
TOP VIEW
N.C.
GND
N.C.
N.C.
N.C.
TSOCDS28E02N.C.N.C.ION.C.GNDN.C.
TDFN
(3mm × 3mm)TOP VIEW
DS28E02
ymrrF
Pin Configurations
DS28E02
1-Wire FUNCTION
CONTROL
1-Wire NET
PARASITE POWER
CRC16
GENERATOR
64-BIT
ROM
64-BIT
SCRATCHPAD
512-BIT
SECURE HASH
ALGORITHM ENGINE
REGISTER
PAGE
DATA MEMORY
4 PAGES OF
256 BITS EACH
MEMORY AND
SHA-1 FUNCTION
CONTROL UNIT
Figure 1. Block Diagram
or consumable authentication and calibration, and
printer cartridge configuration and monitoring.
OverviewThe block diagram in Figure 1 shows the relationships
between the major control and memory sections of the
DS28E02. The DS28E02 has six main data compo-
nents: 64-bit ROM, 64-bit scratchpad, four 256-bit
pages of EEPROM, register page, and a 512-bit SHA-1
engine. Figure 2 shows the hierarchic structure of the
1-Wire protocol. The bus master must first provide one
of the seven ROM function commands: Read ROM,
Match ROM, Search ROM, Skip ROM, Resume
Communication, Overdrive-Skip ROM, or Overdrive-
Match ROM. Upon completion of an Overdrive-Skip
ROM or Overdrive-Match ROM command executed at
standard speed, the device enters overdrive mode
speed. The protocol required for these ROM function
commands is described in Figure 10. After a ROM
function command is successfully executed, the mem-
ory and SHA-1 functions become accessible and the
master can provide any one of the 9 available function
commands. The function protocols are described in
Figure 8. All data is read and written least signifi-
cant bit first.
64-Bit ROMEach DS28E02 contains a unique ROM registration num-
ber that is 64 bits long. The first 8 bits are a 1-Wire family
code. The next 48 bits are a unique serial number. The
last 8 bits are a cyclic redundancy check (CRC) of the
first 56 bits. See Figure 3 for details. The 1-Wire CRC is
generated using a polynomial generator consisting of a
shift register and XOR gates as shown in Figure 4. The
polynomial is X8+ X5+ X4+ 1. Additional information
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ABRIDGED DATASHEET
DS28E02
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ABRIDGED DATASHEET
AVAILABLE COMMANDS:DATA FIELD AFFECTED:READ ROM
MATCH ROM
SEARCH ROM
SKIP ROM
RESUME
OVERDRIVE-SKIP ROM
OVERDRIVE-MATCH ROM
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
64-BIT REG. #, RC-FLAG
RC-FLAG
RC-FLAG
RC-FLAG, OD-FLAG
64-BIT REG.#, RC-FLAG, OD-FLAG
1-Wire ROM FUNCTION COMMANDS
(SEE FIGURE 10)
Refer to the full data sheet.
DEVICE-SPECIFIC MEMORY
FUNCTION COMMANDS
(SEE FIGURE 8)
COMMAND LEVEL:DS28E02
Figure 2. Hierarchic Structure for 1-Wire Protocol
MSB
8-BIT
CRC CODE48-BIT SERIAL NUMBER
MSBMSBLSB
LSB
LSB
8-BIT FAMILY CODE
MSBLSB
Figure 3. 64-Bit ROM
27: Understanding and Using Cyclic Redundancy
Checks with Maxim iButton Products.
The shift register bits are initialized to 0. Then, starting
with the least significant bit of the family code, one bit
at a time is shifted in. After the 8th bit of the family code
has been entered, the serial number is entered. After
the 48th bit of the serial number has been entered, the
shift register contains the CRC value. Shifting in the 8
bits of the CRC returns the shift register to all 0s.
Memory AccessThe DS28E02 has four memory areas: data memory,
secrets memory, register page with special function
registers and user bytes, and a volatile scratchpad. The
data memory is organized as four pages of 32 bytes.
1ST
STAGE
2ND
STAGE
3RD
STAGE
4TH
STAGE
7TH
STAGE
8TH
STAGE
6TH
STAGE
5TH
STAGEX1X2X3X4
POLYNOMIAL = X8 + X5 + X4 + 1
INPUT DATAX6X7X8
Figure 4. 1-Wire CRC Generator
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ABRIDGED DATASHEET
Refer to the full data sheet.
DS28E02
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ABRIDGED DATASHEETFigure 6. Memory Protection Matrix
Address Registers and Transfer StatusThe DS28E02 employs three address registers: TA1,
TA2, and E/S (Figure 7). These registers are common to
many other 1-Wire devices, but operate slightly differ-
ently with the DS28E02. Registers TA1 and TA2 must be
loaded with the target address to which the data is writ-
ten or from which data is read. Register E/S is a read-
only transfer-status register used to verify data integrity
with write commands. Since the scratchpad of the
DS28E02 is designed to accept data in blocks of 8
bytes only, the lower 3 bits of TA1 are forced to 0 and
BIT # 7 6 5 4 3 2 1 0
TARGET ADDRESS (TA1) T7 T6 T5 T4 T3 T2
(0)
(0)
(0)
TARGET ADDRESS (TA2) T15 T14 T13 T12 T11 T10 T9 T8
ENDING ADDRESS WITH
DATA STATUS (E/S)
(READ ONLY)
AA 1 PF 1 1 E2
(1)
E1
(1)
E0
(1)
Figure 7. Address Registers
Refer to the full data sheet.
the lower 3 bits of the E/S register (ending offset) always
read 1. This indicates that all the data in the scratchpad
is used for a subsequent copying into main memory or
secret. Bit 5 of the E/S register, called PF or partial byte
flag, is a logic 1 if the number of data bits sent by the
master is not an integer multiple of eight or if the data in
the scratchpad is not valid due to a loss of power. A
valid write to the scratchpad clears the PF bit. Bits 3, 4,
and 6 have no function; they always read 1. The partial
flag supports the master checking the data integrity after
a write command. The highest valued bit of the E/S reg-
ister, called authorization accepted (AA), acts as a flag
to indicate that the data stored in the scratchpad has
already been copied to the target memory address.
Writing data to the scratchpad clears this flag.
Writing with VerificationTo write data to the DS28E02, the scratchpad must be
used as intermediate storage. First, the master issues
the Write Scratchpad command, which specifies the
desired target address and the data to be written to the
scratchpad. Note that writes to data memory must be
performed on 8-byte boundaries with the three LSBs of
the target address T[2:0] equal to 000b. Therefore, if
T[2:0] are sent with nonzero values, the device sets
these bits to 0 and uses the modified address as the
target address. The master should always send eight
complete data bytes. After the 8 bytes of data have
been transmitted, the master can elect to receive an
inverted CRC-16 of the Write Scratchpad command,
the address as sent by the master, and the data as sent
by the master. The master can compare the CRC to the
value it has calculated itself to determine if the commu-
nication was successful. After the scratchpad has been
written, the master should always perform a read
scratchpad to verify that the intended data was in fact
written. During a read scratchpad, the DS28E02
repeats the target address TA1 and TA2 and sends the
contents of the E/S register. The partial flag (bit 5 of the
E/S register) is set to 1 if the last data byte the DS28E02
received during a write scratchpad or refresh scratch-
pad command was incomplete, or if there was a loss of
power since data was last written to the scratchpad.
The authorization-accepted (AA) flag (bit 7 of the E/S
register) is normally cleared by a write scratchpad or
refresh scratchpad; therefore, if it is set to 1, it indicates
that the DS28E02 did not understand the proceeding
write (or refresh) scratchpad command. In either of
these cases, the master should rewrite the scratchpad.
After the master receives the E/S register, the scratch-
pad data is received. The descriptions of write scratch-
pad and refresh scratchpad provide clarification of
what changes can occur to the scratchpad data under
scratchpad command, target address, E/S register, and
scratchpad data follows the scratchpad data. As with
the write scratchpad command, this CRC can be com-
pared to the value the master has calculated to deter-
mine if the communication was successful. After the
master has verified the data, it can send the copy
scratchpad to copy the scratchpad to memory.
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ABRIDGED DATASHEET
Refer to the full data sheet.
DS28E02
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ABRIDGED DATASHEET
Memory and SHA-1 Function
CommandsThis section describes the commands and flowcharts
needed to use the memory and SHA-1 engine of the
device. Refer to the full data sheet for more information.
DS28E02
1-Wire SHA-1 Authenticated 1Kb
EEPROM with 1.8V Operation
ABRIDGED DATASHEET
1-Wire Bus SystemThe 1-Wire bus is a system that has a single bus master
and one or more slaves. In all instances the DS28E02 is
a slave device. The bus master is typically a microcon-
troller. The discussion of this bus system is broken
down into three topics: hardware configuration, trans-
action sequence, and 1-Wire signaling (signal types
and timing). The 1-Wire protocol defines bus transac-
tions in terms of the bus state during specific time slots,
which are initiated on the falling edge of sync pulses
from the bus master.
