DS28DG02E-3C+ ,2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and WatchdogFEATURES The DS28DG02 combines 2Kb (256 x 8) EEPROM 2Kb (256 x 8) EEPROM Organized in Four with ..
DS28DG02EVKIT ,Evaluation Board/Evaluation System for the DS28DG02FeaturesThe DS28DG02 evaluation system (EV system) consists♦ Proven PCB Layoutof an evaluation boar ..
DS28DG02G-3C+ ,2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog 11/09 EV KIT AVAILABLE DS28DG02 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Wat ..
DS28DG02G-3C+T ,2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and WatchdogAPPLICATIONS Registration Number Asset-Tracking Systems Operating Range: 2.2V to 5.25V, Broadban ..
DS28E01P-100+T , 1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine
DS28E01P-100+T , 1K-Bit Protected 1-Wire EEPROM with SHA-1 Engine
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS28DG02E-3C+-DS28DG02G-3C+-DS28DG02G-3C+T
2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
GENERAL DESCRIPTION The DS28DG02 combines 2Kb (256 x 8) EEPROM
with 12 PIO lines, a real-time clock (RTC) and
calendar with alarm function, a CPU reset monitor, a
battery monitor, and a watchdog. Communication
with the device is accomplished with an industry-
standard SPI™ interface. The user EEPROM is
organized as four blocks of 64 bytes each with
single-byte and up to 16-byte page write capability.
Additional registers provide access to PIOs and to
setup functions. Individual PIO lines can be
configured as inputs or outputs. The power-on state
of PIOs programmed as outputs is stored in
nonvolatile (NV) memory. All PIOs may be
reconfigured by the user through the serial interface.
The RTC/calendar operates in the 12/24-hour format
and automatically corrects for leap years. Battery
monitor threshold and watchdog timeout are user-
programmable through NV registers. The reset
monitor generates a reset to the CPU if the voltage at
the VCC pin falls below the factory-set limit. The reset
output includes a debounce circuit for manual
pushbutton reset.
APPLICATIONS Asset-Tracking Systems
Broadband Access Network Equipment
Patient-Monitoring Systems
Home Lighting Control Systems
Holter Heart Monitors
Typical Operating Circuit appears on page 32.
Pin Configuration appears on page 33.
FEATURES
2Kb (256 x 8) EEPROM Organized in Four
64-Byte Blocks
Single Byte and Up to 16-Byte EEPROM Write
Sequences
EEPROM Write-Protect Control Pin Protects
1, 2, or All 4 Blocks
Endurance 200k Cycles per Page at +25°C;
10ms (max) EEPROM Write Cycle
SPI Serial Interface Supporting Modes (0,0)
and (1,1) at Up to 2MHz Clock Frequency
12 PIO Lines with LED Drive Capability
Each PIO is Configured to Input or Output,
Open-Drain/Push-Pull on Startup by Stored
Value
All PIOs are Reconfigurable After Startup
RTC/Calendar/Alarm with BCD Format and
Leap-Year Compensation
RTC Controlled Through 32.768kHz, 12.5pF
Crystal or External TCXO
CPU Reset Through Fast-Response Precision
VCC Monitor with Hysteresis or Pushbutton
Battery Monitor 2.5V, 2.25V, 2.0V, 1.75V, -5%
Watchdog Timer 1.6s, 0.8s, 0.4s, 0.2s (typ)
Unique Factory-Programmed 64-Bit Device
Registration Number
Operating Range: 2.2V to 5.25V,
-40°C to +85°C
±4kV IEC 1000-4-2 ESD Protection Level
(Except Crystal Pins)
Available in 28-Lead, 4.4mm TSSOP or
36-Lead 6mm × 6mm QFN Package
ORDERING INFORMATION
PART TEMP RANGE VCC TRIP PIN-PACKAGE PKG CODE DS28DG02E-3C+ -40°C to +85°C 3.3V -5% 28 TSSOP-EP* (4.4mm) U28E+5
DS28DG02E-3C+T -40°C to +85°C 3.3V -5% 28 TSSOP-EP* T&R U28E+5
DS28DG02G-3C+ -40°C to +85°C 3.3V -5% 36 TQFN-EP* (6mm × 6mm) T3666+3
DS28DG02G-3C+T -40°C to +85°C 3.3V -5% 36 TQFN-EP* T&R T3666+3
*EP = Exposed Paddle.
+Denotes lead-free/RoHS compliant device.
For additional VCC monitor trip points or other device options, contact the factory.
Note: Registers are capitalized for clarity. SPI is a trademark of Motorola, Inc.
DS28DG02
2Kb SPI EEPROM with PIO, RTC,
Reset, Battery Monitor, and Watchdog
11/09
EV KIT AVAILABLE
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.5V, +6V
Maximum Current SO, ALMZ, RSTZ, WDOZ Pins 20mA
Maximum Current Each PIO Pin 50mA
Maximum GND and VCC Current 270mA
Operating Temperature Range -40°C to +85°C
Junction Temperature +150°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS (TA = -40°C to +85°C.)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Battery monitor off 2.2 5.25 Supply Voltage VCC Battery monitor enabled 2.7 5.25 V
Battery Voltage VBAT (Note 1) 1.5 3.0 VCC V
RTC oscillator off 2
RTC oscillator on 0.4 10 Battery Current (VBAT = 3.0V,
Note 1) IBAT
RTC oscillator on, +25°C 4.7
µA
Standby Current (Note 2) ICCS
SPI idle, ALMZ, WDOZ,
RTSZ high, VCC = 5.25V,
RTC oscillator on, all
PIOs grounded
60 100 µA
Operating Current ICCA
Reading EEPROM at 2
Mbps, ALMZ, WDOZ,
RTSZ high, VCC = 5.25V,
RTC oscillator on, all
PIOs grounded
550 800 µA
Programming Current IPROG VCC = 5.25V 600 1000 µA
VCC Monitor Trip Point VTRIP (Note 3) 2.97 3.05 3.14 V
+25°C -1.5 +1.5 VCC Monitor Trip-Point
Tolerance VTRIPTOL -40°C to +85°C -2.5 +2.5 %VTRIP
VCC Monitor Hysteresis VHYST 0.4 0.5 0.6 %VTRIP
Power-Up Wait Time tPOIP 60 µs
EEPROM Programming Time tPROG 10 ms
Endurance NCYCLE At +25°C (Notes 4, 5) 200k —
Data Retention tRET At +85°C (Notes 5, 6) 40 years
REAL-TIME CLOCK Frequency Deviation F (Notes 5, 7) -46 +46 PPM
PIO PINS (See Figures 21, 22, 23) VCC = 2.2V 6 9.5
VCC = 3.3V 12.5 22.0 LOW-Level Output Current at
VOL = 0.5V (Note 8) IOL
VCC = 5.25V 19 30
mA
VOH = 2.4V, VCC = 3.3V 6.5 11.0 HIGH-Level Output Current
(Note 8) IOH VOH = 4.5V, VCC = 5.25V 12.5 18.0 mA
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS LOW-Level Input Voltage VIL 0.8 V
HIGH-Level Input Voltage VIH 0.7 ×
VCC VCC +
0.5V V
Low-current mode
(Note 9) 1
Output Transition Time tOT High-current mode
(Note 10) 25
µs
Power-On Setting Time tPOS High-current mode
(Note 11) 25 µs
PIO Read Setup Time tPS (Note 5) 100 ns
PIO Read Hold Time tPH (Note 5) 100 ns
Leakage Current IL High impedance, at
VCCMAX -1 +1 µA
RSTZ PIN (Note 12) (See Figures 6, 7) LOW-Level Output Voltage VOL At 4mA sink current 0.3 V
LOW-Level Input Voltage VIL 0.3 ×
VCC V
Input Leakage Current IL -1 +1 µA
Minimum VCC for Valid RSTZ VPOR (Notes 5, 13) 2.13 V
RSTZ Pulse Duration tRST 176 328 532 ms
Manual Reset Pulse Width tMPW 1 µs
Manual Reset Release
Threshold VTRMS (Note 14) VIL V
Manual Reset Debounce Time tDEB tRST ms
RSTZ Delay tDEL VCC falling below VTRIP
(Note 15) 90 µs
ALMZ, WDOZ PINS LOW-Level Output Voltage VOL At 4mA sink current 0.3 V
WDI PIN LOW-Level Input Voltage VIL 0.3 ×
VCC V
HIGH-Level Input Voltage VIH 0.7 ×
VCC VCC +
0.5V V
Input Leakage Current IL -1 +1 µA
Minimum Input Pulse Width tMPW 1 µs
Watchdog Timeout tWD User programmable
0.88
0.44
0.22
0.11
1.64
0.82
0.41
0.20
2.66
1.33
0.67
0.33
WPZ, SI, SCK, CSZ PINS LOW-Level Input Voltage VIL 0.3 ×
VCC V
HIGH-Level Input Voltage VIH 0.7 ×
VCC VCC +
0.5V V
Input Leakage Current IL -1 +1 µA
SO PIN LOW-Level Output Voltage VOL At 1mA sink current and
VCCmin 0.2 V
HIGH-Level Output Voltage VOH At 1mA source current 0.7 ×
VCC V
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
BATTERY MONITOR (See Figure 8) VBAT Trip Point VBTP
Measured with VBAT
falling; trip point is user
programmable
2.25
2.03
1.80
1.58
2.31
2.08
1.85
1.62
2.38
2.14
1.90
1.66
+25°C -1.5 +1.5 VBAT Monitor Trip-Point
Tolerance VTRIPTOL -40°C to +85°C -2.5 +2.5 %VBTP
Battery Test Load Current ILOAD 7.5 20 µA
Battery Test Duration tBTPW Load applied to battery
(Notes 5, 16) 2 s
SPI INTERFACE TIMING (See Figures 9, 10) CSZ Setup Time tCSS (Note 5) 0.4 µs
CSZ Hold Time tCSH (Note 5) 0.4 µs
Normal communication 0.25 CSZ Standby Pulse Width
(Note 5) tCPH (Note 17) 2.0 µs
CSZ to High-Z at SO tCHZ 0.25 µs
SCK Clock Frequency fCLK 2 MHz
Data Setup Time tDS (Note 5) 50 ns
Data Hold Time tDH (Note 5) 50 ns
SCK Rise Time tSCKR (Note 5) 1 µs
SCK Fall Time tSCKF (Note 5) 1 µs
Output Valid time tV (Note 5) 0 120 ns
Note 1: If no battery is used, connect the VBAT pin to VCC. The RTC is powered by VBAT if VCC falls below VCCmin.
Note 2: To the first order, this current is independent of the supply voltage value.
Note 3: Nominal values: 3.3V -5%, set at factory. Measured with VCC falling; for VCC rising, the actual threshold is
VTRIP + VHYST.
Note 4: This specification is valid for each 16-byte memory page.
Note 5: Not production tested. Either guaranteed by design (GBD) or guaranteed by a reliability study (EEPROM lifetime
parameters).
Note 6: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-time storage at
elevated temperatures is not recommended; the device can lose its write capability after 10 years at +125°C or 40
years at +85°C.
Note 7: Valid with 32KHz crystal, 12.5pF, ESR 45k, +25°C.
Note 8: Total PIO sink and source currents through all PIO pins must be externally limited to less than the absolute
maximum rating of 270mA minus 1.5mA for EEPROM programming and SPI communication. Exceeding the
absolute maximum rating can cause damage.
Note 9: Assumes the configuration of the system and the part is such that changing GOV
(0 ≤ i ≤ 11) between ‘b1 and
‘b0 switches between sourcing no current and sinking the absolute maximum current at the PIO pin. The limit
refers to the switching time between sinking 20% of the DC current and 80% of the DC current. The same is true
for changing between 'b0 and 'b1 causing the part to switch from sinking no current to sourcing the absolute
maximum current at the PIO pin.
Note 10: Each output pin transitions in 1µs with a pause of 1µs before the next pin transitions.
Note 11: All PIO are tri-stated at beginning of reset prior to setting to power-on values.
Note 12: If the part has battery power (normal case) the active pulldown of RSTZ is supported by the battery.
Note 13: If VBAT is tied to VCC (no battery supply) the state of the RSTZ pulldown transistor is not guaranteed when VCC falls
below VPOR.
Note 14: Threshold refers to the manual reset function obtained by forcing RSTZ low.
Note 15: Transient response to a step on VCC from above VTRIP down to (VTRIP - 1mV). Glitches on VCC that are shorter than
tDELmin are guaranteed to be suppressed, regardless of their amplitude. Glitches on VCC that are longer than tDELmax
are guaranteed not to be suppressed. This parameter is tested at high VCC and guaranteed by design at low.
Note 16: If enabled, this test takes place every hour on the hour. The battery voltage is compared to VBTP during the second
half of the tBTPW window. The timing is controlled by the RTC.
Note 17: Extended duration applies to the following cases:
1) Aborted WREN, WRDI, RDSR, and WRSR command.
2) WRITE command aborted before transmitting the first complete data byte after command and address.
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
PIN DESCRIPTION
PIN NAME TSSOP28 TQFN36 FUNCTION
X1 1 33 32.768kHz Crystal Connection 1 or 32.768kHz Input from TCXO
X2 2 34 32.768kHz Crystal Connection 2
RSTZ 3 36
Open-Drain Output Pin (Active Low) for VCC power-fail reset,
watchdog alarm, and Manual Reset Input. See Multifunction
Control/Setup Register description for more information.
WDI 4 2 Watchdog Input Pin (Active High). See Multifunction Control/Setup
Register description at address 134h for more information.
WDOZ 5 3
Open-Drain Output Pin (Active Low) for (user-choice) watchdog
alarm. See Multifunction Control/Setup Register description for more
information.
WPZ 6 4 Hardware Write-Protect Input Pin (Active Low). See the SPI Interface
description for more information.
PIO0 7 5 PIO Line #0
PIO4 8 6 PIO Line #4
PIO8 9 7 PIO Line #8
GND 10, 19 9, 19 Ground Supply
PIO10 11 10 PIO Line #10
PIO6 12 11 PIO Line #6
PIO2 13 12 PIO Line #2
VCC 14, 15 13, 15 Power Supply Input
PIO3 16 16 PIO Line #3
PIO7 17 17 PIO Line #7
PIO11 18 18 PIO Line #11
PIO9 20 21 PIO Line #9
PIO5 21 22 PIO Line #5
PIO1 22 23 PIO Line #1
ALMZ 23 24
Open-Drain Output Pin (Active Low) for RTC, battery monitor, and
(user-choice) watchdog alarms. See the Multifunction Control/Setup
Register description for more information.
SO 24 25 SPI Serial Data Output (tristate)
SI 25 26 SPI Serial Data Input
SCK 26 28 SPI Serial Clock Input
CSZ 27 30 Chip Select Input (Active Low)
VBAT 28 31 Backup Battery Supply for RTC and RSTZ support.
N.C. —
1, 8, 14,
20, 27,
29, 32, 35
No Connection
GND EP EP Exposed Paddle. Solder evenly to the board’s ground plane for proper
operation. See Application Note 3273 for additional information.
OVERVIEW
The DS28DG02 features 2Kb of EEPROM, 12 bidirectional PIO channels, an RTC with calendar and alarm
function, a watchdog timer, two voltage monitors with precision trip points, and three alarm/reset outputs. Each
DS28DG02 has its own unique registration number, which serves as identification of the product the device is
embedded in. All these resources are accessed through a serial SPI interface, as shown in the block diagram in
Figure 1. The SPI interface automatically adjusts to SPI modes (0,0) and (1,1). The VCC trip point, which controls
the power-fail reset output (RSTZ pin), is set at the factory. The user can set the battery monitor threshold and the
watchdog time-out through software. The RTC uses the common BCD format for time, calendar and day of the
week. The device can be programmed to generate an RTC alarm every second, minute, hour, or day and once a
week or once a month at a user-defined time. RTC, watchdog, and battery alarm can be individually enabled.
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
Figure 1. Block Diagram
SPI
Communication
Interface
64-bit Unique
Registration
Number
Watchdog
Timer
Real-Time
Clock, Calendar
and RTC Alarm
Memory
Function Buffer
and Control PIO Function
Control
2Kb
EEPROM Array
Voltage Monitors
and Power
Distribution
Alarm Control
Logic, RSTZ
Debounce
CSZ
SCK
SI
SO
X1
X2
WDI
ALMZ
WDOZ
RSTZ
VCC
VBAT
GND
PIOn
WPZ
12
BATAVCLA
WDA
CLKA
The PIO configuration and setup of RTC/calendar with alarm are part of the Detailed Register Description. This
section also includes specifics of the Multifunction Control/Setup register, which enables/disables several device
functions, and the Alarm/Status register. For detailed information on the operation of the VCC monitor/power-fail
reset and the battery monitor see the Monitoring Functions section. The SPI Interface description explains the
communication protocol for memory and register access and the use of the watchdog function. The PIO
Read/Write Access section illustrates the behavior of the PIOs, in particular the address generation and timing in
low- and high-current mode.
The DS28DG02 memory map (Figure 2) begins with 256 bytes of general-purpose user EEPROM, organized as
four blocks of 64 bytes. Additional EEPROM is set aside to store power-on defaults for PIO state (high, low, in
output mode), data direction (in, out), read-inversion (true, false), port output type (push-pull, open-drain), and
output mode (high current, low current). Once powered up, the PIO settings can be overwritten through SRAM
registers without affecting the power-on defaults. PIO state, direction, and read-inversion can be set for individual
ports. The output type is set for groups of four PIOs and the selected output mode applies to all PIOs in output
mode. The RTC/calendar, associated Alarm registers and the Multifunction Control/Status registers are kept
nonvolatile through battery backup. Write-protection, if enabled, is available for all four EEPROM blocks, blocks 2
and 3 only, or block 3 only and for all writeable registers from address 120h and higher.
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
Figure 2. Memory Map
ADDRESS TYPE ACCESS DESCRIPTION
000h to 03Fh EEPROM R/W User memory block 0.
040h to 07Fh EEPROM R/W User memory block 1.
080h to 0BFh EEPROM R/W User memory block 2.
0C0h to 0FFh EEPROM R/W User memory block 3.
100h to 109h — — Reserved, contents undefined.
10Ah EEPROM R/W Power-on default for PIO output state (PIO0 to PIO7).
10Bh EEPROM R/W Power-on default for PIO output state (PIO8 to PIO11).
10Ch EEPROM R/W Power-on default for PIO direction (PIO0 to PIO7).
10Dh EEPROM R/W Power-on default for PIO direction (PIO8 to PIO11).
10Eh EEPROM R/W Power-on default for PIO read-inversion (PIO0 to PIO7).
10Fh EEPROM R/W
Power-on default for PIO read-inversion (PIO8 to PIO11),
PIO output type (PIO0 to PIO11 in groups of 4 PIOs), PIO
output mode (same mode for all PIOs).
110h to 117h — — Reserved, contents is undefined.
118h to 11Fh ROM R 64-bit unique registration number.
120h SRAM R/W PIO output state (PIO0 to PIO7).
121h SRAM R/W PIO output state (PIO8 to PIO11).
122h SRAM R/W PIO direction (PIO0 to PIO7).
123h SRAM R/W PIO direction (PIO8 to PIO11).
124h SRAM R/W PIO read-inversion (PIO0 to PIO7).
125h SRAM R/W
PIO read-inversion (PIO8 to PIO11), PIO output type (PIO0
to PIO11 in groups of 4 PIOs), PIO output mode (same
mode for all PIOs).
126h — R PIO read access (PIO0 to PIO7).
127h — R PIO read access (PIO8 to PIO11).
128h — — Reserved, contents undefined.
129h to 12Fh NV SRAM R/W RTC and calendar.
130h to 133h NV SRAM R/W RTC alarm.
134h NV SRAM R/W Multifunction control/setup register.
135h NV SRAM R/Clear Alarm and status register.
136h and above — — Reserved, contents undefined.
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
DETAILED REGISTER DESCRIPTIONS
Power-On Default for PIO Output State
ADDR b7 b6 b5 b4 b3 b2 b1 b0
10Ah POV7 POV6 POV5 POV4 POV3 POV2 POV1 POV0
10Bh X X X X POV11 POV10 POV9 POV8
There is general read and write access to these addresses. Factory default: 10Ah: FFh; 10Bh: 0Fh. The contents of
this register are automatically transferred to address 120h/121h when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
POVn: PIO Power-On
Default State — Power-on default output state of PIO0 to PIO11. POV0 applies to PIO0,
etc.
X: (Not Assigned) — Reserved for future use.
Power-On Default for PIO Direction
ADDR b7 b6 b5 b4 b3 b2 b1 b0
10Ch POD7 POD6 POD5 POD4 POD3 POD2 POD1 POD0
10Dh X X X X POD11 POD10 POD9 POD8
There is general read and write access to these addresses. Factory default: 10Ch: FFh; 10Dh: 0Fh. The contents
of this register are automatically transferred to address 122h/123h when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
PODn: PIO Power-On
Default Direction — Power-on default direction of PIO0 to PIO11. POD0 applies to PIO0, etc.
Legend: 0 output; 1 input
X: (Not Assigned) — Reserved for future use.
Power-On Default for PIO Read Inversion (PIO0 to PIO7)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
10Eh PIM7 PIM6 PIM5 PIM4 PIM3 PIM2 PIM1 PIM0
There is general read and write access to this address. Factory default: 00h. The contents of this register are
automatically transferred to address 124h when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
PIMn: PIO Power-On
Default Read-Inversion —
Power-on default state of the read-inversion bit of PIO0 to PIO7. PIM0
applies to PIO0, etc.
Legend: 0 no inversion; 1 inversion
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
Power-On Default for PIO Read Inversion (PIO8 to PIO11), PIO Output Type and Output Mode
ADDR b7 b6 b5 b4 b3 b2 b1 b0
10Fh POTM POT3 POT2 POT1 PIM11 PIM10 PIM9 PIM8
There is general read and write access to this address. Factory default: 80h. The contents of this register are
automatically transferred to address 125h when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
PIMn: PIO Power-On
Default Read-Inversion b0 to b3
Power-on default state of the read-inversion bit of PIO8 to PIO11. PIM8
applies to PIO8, etc.
Legend: 0 no inversion; 1 inversion
POT1: Power-On
Default Output Type b4 Power-on default output type of PIO0 to PIO3;
Legend: 0 push-pull; 1 open drain
POT2: Power-On
Default Output Type b5 Power-on default output type of PIO4 to PIO7;
Legend: 0 push-pull; 1 open drain
POT3: Power-On
Default Output Type b6 Power-on default output type of PIO8 to PIO11;
Legend: 0 push-pull; 1 open drain
POTM: Power-On
Default Output Mode b7
Power-on default output mode of PIO0 to PIO11;
Legend: 0 low-current, simultaneous switching; 1 high-current,
sequential switching
Unique Registration Number (118h to 11Fh)
Each DS28DG02 has a unique registration number that is 64 bits long, as shown in Figure 3. The registration
number begins with the Cyclic Redundancy Check (CRC) of the subsequent 56 bits at address 118h followed by
the 48-bit serial number (MS-byte at the lower address) and ends at address 11Fh with the family code. This CRC
is generated using the a polynomial X8 + X5 + X4 + 1. Additional information about CRCs is available in Application
Note 27.
Figure 3. 64-Bit Registration Number
Address 118h Addresses 119h (MSB) to 11Eh (LSB) Address 11Fh
8-Bit CRC Code 48-Bit Serial Number 8-Bit Family Code (70h)
MSB LSB MSB LSBMSB LSB
PIO Output State
ADDR b7 b6 b5 b4 b3 b2 b1 b0
120h OV7 OV6 OV5 OV4 OV3 OV2 OV1 OV0
121h X X X X OV11 OV10 OV9 OV8
There is general read and write access to these addresses. These registers are automatically loaded with data
from address 10Ah/10Bh when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
OVn: PIO Output State — Output state of PIO0 to PIO11. OV0 applies to PIO0, etc.
Legend: 0 LOW; 1 HIGH if PIO direction is output
X: (Not Assigned) — Reserved for future use.
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
PIO Direction
ADDR b7 b6 b5 b4 b3 b2 b1 b0
122h DIR7 DIR6 DIR5 DIR4 DIR3 DIR2 DIR1 DIR0
123h X X X X DIR11 DIR10 DIR9 DIR8
There is general read and write access to these addresses. These registers are automatically loaded with data
from address 10Ch/10Dh when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
DIRn: PIO Direction — Direction of PIO0 to PIO11. DIR0 applies to PIO0, etc.
Legend: 0 output; 1 input
X: (Not Assigned) — Reserved for future use.
PIO Read Inversion (PIO0 to PIO7)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
124h IMSK7 IMSK6 IMSK5 IMSK4 IMSK3 IMSK2 IMSK1 IMSK0
There is general read and write access to this address. This register is automatically loaded with data from address
10Eh when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
IMSKn: PIO Read-
Inversion — Read-inversion bit of PIO0 to PIO7. IMSK0 applies to PIO0, etc.
Legend: 0 no inversion; 1 inversion
PIO Read Inversion (PIO8 to PIO11), PIO Output Type and Output Mode
ADDR b7 b6 b5 b4 b3 b2 b1 b0
125h OTM OT3 OT2 OT1 IMSK11 IMSK10 IMSK9 IMSK8
There is general read and write access to this address. This register is automatically loaded with data from address
10Fh when the device powers up.
BIT DESCRIPTION BIT(S) DEFINITION
IMSKn: PIO Read-
Inversion b0 to b3 Read-inversion bit of PIO8 to PIO11. PIM8 applies to PIO8, etc.
Legend: 0 no inversion; 1 inversion
OT1: Output Type b4 Output type of PIO0 to PIO3;
Legend: 0 push-pull; 1 open drain
OT2: Output Type b5 Output type of PIO4 to PIO7;
Legend: 0 push-pull; 1 open drain
OT3: Output Type b6 Output type of PIO8 to PIO11;
Legend: 0 push-pull; 1 open drain
OTM: Output Mode b7
Output mode of PIO0 to PIO11;
Legend: 0 low-current, simultaneous switching; 1 high-current,
sequential switching
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
PIO Read Access
ADDR b7 b6 b5 b4 b3 b2 b1 b0
126h IV7 IV6 IV5 IV4 IV3 IV2 IV1 IV0
127h 0 0 0 0 IV11 IV10 IV9 IV8
There is only read access to these addresses. Bits 4 to 7 of address 127h always read 0. Read access is functional
for all PIOs, regardless of their direction setting. Reported is the logic state of the pin, which may be different from
what the PIO output value register implies.
BIT DESCRIPTION BIT(S) DEFINITION
IVn: Input Value of PIOn — Logic state read from PIO0 to PIO11 pins. IV0 applies to PIO0, etc.
Legend: IVn = PIOn XOR’ed with IMSKn
Figure 4 shows a simplified schematic of a PIO. The flip flops are accessed through the PIO Output State (OVn)
and Read Access (IVn) registers and memory addresses 122h to 125 (DIRn, IMSKn, OTn). They are initialized at
power-up or during Refresh (see the SPI Interface Description) according to the data stored at memory addresses
10Ah to 10Fh. When a PIO is configured as input, the PIO output is tri-stated (high impedance). When a PIO is
configured as output, the PIO input is the same as the output state XORed with the corresponding read inversion
bit. The differences of the PIO behavior in low current and high current mode are explained in the PIO Read/Write
Access section near the end of this document.
Figure 4. PIO Simplified Schematic
D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
DIRn
OVn
OTn
Vcc
D Q
CLK
IMSKn
PIOn Pin
to SPI Interface
IVn
OTn
from SPI Interface
CLK
DIRn
from SPI Interface
OVn
from SPI Interface
IMSKn
from SPI Interface
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
RTC and Calendar Registers
ADDR b7 b6 b5 b4 b3 b2 b1 b0
129h 0 10 Seconds Single Seconds
12Ah 0 10 Minutes Single Minutes
10hrs 12Bh 0 12/24 A/P 10hrs Single Hours
12Ch 0 0 0 0 0 Day of Week
12Dh 0 0 10 Date Single Date
12Eh 0 0 0 Single Months
12Fh 10 Years Single Years
There is general read and write access to these addresses. Bits shown as 0 cannot be written to 1. The RTC and
calendar registers are reset to 00h when the battery voltage ramps up. Writes take effect immediately. To prevent
unexpected increments during write access, first update the seconds; this creates a 1s window to finish updating
the RTC/Calendar registers without any carryover from the Seconds register. Whenever the DS28DG02 receives a
SPI Read command, the RTC and Calendar registers are copied to a buffer. When during a read access the
address counter points to the RTC/Calendar registers, data from the buffer is transmitted. To obtain most accurate
RTC data, start reading at the Seconds register.
The number representation of the RTC/Calendar registers is BCD (binary-coded decimal). The RTC can run in the
12-hour AM/PM and the 24-hour mode. The “12/24” bit (bit 6 of address 12Bh) defines the mode. For 12-hour
AM/PM mode, set this bit to 1; bit 5 of address 12Bh then indicates AM (0b) or PM (1b). In the 24-hour mode, bit 5
and bit 4 together indicate the multiple of 10 hours. The Day of Week register counts from 1 to 7. The calendar
logic is designed to automatically compensate for leap years. For every year value that is either 00 or a multiple of
4 the device will add a 29th of February. This will work correctly up to (but not including) the year 2100.
RTC Alarm Registers
ADDR b7 b6 b5 b4 b3 b2 b1 b0
130h AM1 10 Seconds Single Seconds
131h AM2 10 Minutes Single Minutes
10hrs 132h AM3 12/24 A/P 10hrs Single Hours
0 0 0 Day of Week 133h AM4 DY/DT 10 Date Single Date
There is general read and write access to these addresses. Bits shown as 0 cannot be written to 1. The RTC Alarm
registers are reset to 00h when the battery voltage ramps up. To generate an alarm, there must be a match
between Alarm registers and RTC registers. Alarm register addresses 130h to 132h correspond to RTC register
addresses 129h to 12Bh; bits 6:0 participate in the comparison. The lower 6 bits of register address 133h
correspond to 12Ch if DY/DT is 1 and to 12Dh if DY/DT is 0; the upper 2 bits of this register do not participate in the
comparison. The control bits AM1, AM2, AM3, and AM4 determine the frequency of the alarm, as shown in Table
1. When the alarm occurs, the CLKA bit of the Alarm and Status register at address 135h changes to 1. The RTC
must be running for the device to generate RTC alarms (OSCE at address 134h = 1).
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
Table 1. Alarm Frequency Control
DY/DT AM4 AM3 AM2 AM1 ALARM OCCURRENCE
X X X X 1 Every second X X 1 0 Every minute, when the seconds match X 1 0 0 Every hour, when minutes and seconds match 1 0 0 0 Every day, when hours, minutes, and seconds match 0 0 0 0 Every week, when day, hours, minutes, and seconds match 0 0 0 0 Every month, when date, hours, minutes, and seconds match
Multifunction Control/Setup Register
ADDR b7 b6 b5 b4 b3 b2 b1 b0
134h 0 BME BTRP WDOS WDE OSCE CAE
There is general read and write access to this address. Bit 7 always reads 0; it cannot be written to 1. This register
is reset to 00h when the battery voltage ramps up. See Figure 5 for the use of the CAE, WDE, WDOS, and BME
bits in the generation of the ALMZ, RSTZ, and WDOZ signals.
BIT DESCRIPTION BIT(S) DEFINITION
CAE: Clock Alarm
Enable b0 Enable/disable control of the RTC/Calendar alarm.
Legend: 0 disabled (power-on default); 1 enabled
OSCE: RTC Oscillator
Enable b1 Run/halt control of the RTC’s 32KHz oscillator
Legend: 0 halted (power-on default); 1 running
WDE: Watchdog Enable b2
Enable/disable control of the watchdog and its alarm.
Legend: 0 disabled (power-on default); 1 enabled
The watchdog timer is reset by changing WDE from 0 to 1, VCC ramp up
(Power-on reset) or applying a positive pulse at the WDI pin.
WDOS: Watchdog
Output Selection b3 Pin selection for watchdog alarm signaling.
Legend: 0 WDOZ pin (power-on default); 1 ALMZ pin
BTRP: Battery Monitor
Trip Point b5:b4
Selection of the nominal Battery Monitor Trip Point voltage.
Legend: 00b 1.75V (power-on default); 01b 2.00V;
10b 2.25V; 11b 2.50V
BME: Battery Monitor
Enable b6
Enable/disable control of the Battery Monitor and its alarm.
Legend: 0 disabled (power-on default); 1 enabled
The battery test takes place a) after BME changes to 1, b) after VCC
ramps up, c) every hour on the hour. The RTC must be running (OSCE
= 1) for the battery monitor to function.
Alarm and Status Register
ADDR b7 b6 b5 b4 b3 b2 b1 b0
135h 0 BATA WPZV POR BOR CLKA WDA RST
There is general read access to this address; writing clears all bits to 0. Bit 7 always reads 0. See Figure 5 for the
use of the CLKA, WDA, and BATA bits in the generation of the ALMZ, RSTZ, and WDOZ signals.
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
BIT DESCRIPTION BIT(S) DEFINITION
RST: Reset Flag b0
RSTZ pin activity indicator; set whenever there is a pulse at RSTZ;
cleared by writing to the Alarm and Status register.
VCC ramp up: 1; VBAT attach: 0
WDA: Watchdog Alarm b1
Watchdog Alarm indicator; set whenever the watchdog is enabled AND
the watchdog timer expires; cleared by writing to the Alarm and Status
register.
VCC ramp up: 0; VBAT attach: 0
CLKA: Clock Alarm b2
RTC/Calendar Alarm indicator; set whenever the clock alarm is enabled
AND RTC and RTC Alarm register match; cleared by writing to the
Alarm and Status register.
VCC ramp up: 0; VBAT attach: 0
BOR: Battery-On Reset
Flag b3
Battery attach indicator; set whenever the voltage at VBAT ramps up
above VBATmin; cleared by writing to the Alarm and Status register.
VCC ramp up: not affected; VBAT attach: 1
POR: Power-On Reset
Flag b4
Power-On Reset indicator; set whenever the voltage at VCC ramps up
above VCCmin; cleared by writing to the Alarm and Status register.
VCC ramp up: 1; VBAT attach: 0
WPZV: Hardware Write
Protect Value b5 WPZ pin state readout; reports the logic state at the WPZ pin;
VCC ramp up: WPZ pin state; VBAT attach: not affected.
BATA: Battery Alarm b6
Low Battery indicator; set whenever the battery alarm is enabled AND if,
during a battery test, VBAT is below the selected VBAT trip point; cleared
by writing to the Alarm and Status register.
VCC ramp up: battery test if BME = 1; VBAT attach: 0
Figure 5. ALMZ, WDOZ, and RSTZ Generation
BME, CAE, WDE, WDOS are defined in the Control/Setup register.
BATA, CLKA, WDA are alarm signals readable through the Alarm/Status register.
VCLA is the alarm output of the VCC monitor.
WDE
WDA
WDOS
VCLA
Debounce
BME
BATA
CAE
CLKA
WDOZ
RSTZ
ALMZ
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
MONITORING FUNCTIONS
The DS28DG02 has two voltage monitors: one for the VCC supply voltage and another one for the battery that
supplies the RTC and associated registers if VCC is switched off. If VCC falls below the VTRIP threshold the VCC
monitor activates the open-drain RSTZ output, as shown in Figure 6. There is a delay of tDEL between crossing the
trip point and RSTZ going LOW. As long as VCC is above VPOR or the device has a functioning battery backup, the
logic level at RSTZ does not exceed VOLmax. Without battery support, the state of the RSTZ output is undefined for
VCC values below VPOR. When VCC ramps up, RSTZ remains at LOW until the VTRIP threshold is reached. As VTRIP is
crossed, the voltage at RSTZ rises until it reaches VTRMS, the manual reset release threshold. This activates the
debounce circuit, which holds RSTZ low for tRST. After tRST is expired, the voltage at RSTZ ramps up to the value of
the applied pullup voltage.
Figure 6. RSTZ Power-Fail Reset VCC
VTRIP
VPOR
VCC *
RSTZ
With the VBAT pin tied to VCC, the RSTZ behavior for
VCC < VPOR is undefined. * VCC or the applicable pullup voltage for the RSTZ pin.
tDEL tRST
As VTRIP is crossed, the voltage at
RSTZ starts rising, which triggers
the manual switch debounce
circuit and activates RSTZ for tRST.
The RSTZ pin is internally connected to a debounce circuit, which allows using a manually operated switch to
generate a reset signal. Figure 7 illustrates the timing of the manual reset. As the switch closes, it forces the
voltage at RSTZ to fall below VILmax, which triggers the debounce circuit. Now the voltage at RSTZ is held at logic
LOW by both, the manual switch and the debounce circuit. When the manual switch is opened or tDEB is over,
(whichever occurs later) the voltage at RSTZ rises until it reaches VTRMS. This again triggers the debounce circuit,
which holds RSTZ low for tRST, after which the voltage at RSTZ ramps up to the pullup voltage. The minimum LOW
time of a manually generated reset is tDEB + tRST.
Figure 7. RSTZ Manual Switch Debounce
RSTZ held low by
DS28DG02
Open
Manual
Switch
closed
VCC *
RSTZ
VTRMS tRSTtDEB
RSTZ held low
by manual switch
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
In contrast to the VCC monitor, the battery monitor is active only for two seconds per hour, and only if it is enabled
through the BME bit in the Multifunction Control/Setup register. In addition to this, the DS28DG02 must have
sufficient VCC power and the RTC must be running (OSCE = 1). The battery test takes place a) immediately after
enabling the battery monitor, and, if the battery monitor is enabled, b) every hour on the full hour, and c)
immediately after VCC ramps up above VPOR. Figure 8 shows the details.
The battery test procedure begins with the DS28DG02 internally connecting the test load to the VBAT pin. If the
battery is near the end of its lifetime, this extra load causes the battery voltage to fall below VBTP, the Battery Trip
Point. After the stabilization window is over, the actual comparison of the battery voltage to the battery trip point
takes place. If at the beginning of or during the battery test window the battery voltage falls below VBTP, the battery
alarm flag BATA in the Alarm and Status register is set, which in turn activates the ALMZ output. The BATA flag is
cleared by a) replacing the battery, or b) by writing to the Alarm and Status register. The BATA flag is not cleared if
a subsequent battery test, e.g., one hour later or after power-cycling the DS28DG02, determines that the battery
voltage is above VBTP. Note that replacing the battery resets the RTC and clears the Multifunction Control/Setup
register.
Battery monitoring is only useful when performed regularly. Equipment that is powered-down for excessively long
periods can completely drain its battery without receiving any advanced warning. To prevent such an occurrence,
equipment using the battery-monitoring feature should be switched on periodically, e.g., once a month, to perform a
battery test.
Figure 8. Battery Monitor Operation VBAT
VBTP
ALMZ
Test
Load
On
off
Stabilization
Window
Battery Test
Window 1s
BATA
DS28DG02: 2Kb SPI EEPROM with PIO, RTC, Reset, Battery Monitor, and Watchdog
SPI INTERFACE
The DS28DG02 is a slave device that communicates with its master, a microcontroller, through the serial SPI
interface. This interface uses the signals CSZ (chip select), SCK (bit transfer clock), SI (serial input), and SO (serial
output). Common to SPI devices is a WPZ input (write protect), which can protect the nonvolatile bits in the SPI
Status register from inadvertent changes.
Pin Description
Chip Select (CSZ)
A low level on the CSZ pin selects the device; a high level deselects the device. A low-to-high transition on CSZ
after a valid EEPROM write sequence initiates an internal programming cycle. A programming cycle already
initiated or in progress will be completed, regardless of the CSZ input signal. When the device is deselected, SO
goes to the high-impedance state, allowing multiple parts to share the same SPI bus. After powerup, a low level on
CSZ is required prior to any sequence being initiated. The CSZ pin must remain low while the DS28DG02 is
receiving or transmitting data.
Serial Clock (SCK)
The SCK is used to synchronize the communication between a master and the DS28DG02. Instructions,
addresses, or data present on the SI pin are latched on the rising edge of the clock input, while data on the SO pin
is updated after the falling edge of the clock input.
Serial Input (SI)
The SI pin is used to transfer data into the device. It receives instructions, addresses, and data. Data is latched on
the rising edge of the serial clock.
Serial Output (SO)
The SO pin is used to transfer data out of the DS28DG02. During a read cycle, data is shifted out on this pin after
the falling edge of the serial clock.
Write Protect (WPZ)
The WPZ pin, if enabled, prevents writes to the nonvolatile bits in the SPI Status register. As factory default, the
WPZ pin function is disabled. This allows the user to install the DS28DG02 in a system with WPZ pin grounded and
still being able to write to the Status register. For more details see Principles of Operation.
SPI Modes and Bit Timing
The SPI protocol defines communication in full bytes with the MS bit being transmitted first. Every SPI
communication sequence begins with at least one byte written to the slave device. The first byte that the slave
receives from the master is understood as an instruction. Depending on the instruction the slave may need more
bytes, e.g., address and data; for a read function, after having received the instruction and address, the slave starts
sending data to the master.
The SPI protocol knows four communication modes, which differ in the polarity and phase of the SCK signal. The
DS28DG02 supports modes (0,0) and mode (1,1). These modes have in common that data is clocked into the
slave on the rising edge and clocked out to the master on the falling edge of SCK. The master then clocks in the
data on the rising edge of SCK. The DS28DG02 detects the mode from the logic state of SCK when CSZ gets
active (high to low transition). Therefore, SCK must be stable for the duration of a setup and hold time around the
falling edge of CSZ. Figures 9 and 10 show the timing details.
The read timing of these graphics begins with the first bit that the DS28DG02 transmits to the master and ends
when the master ends the communication by deactivating CSZ (low to high transition). The dotted line indicates the
transition between read and write, with the last bit of the command or address being clocked in on the rising edge
and the first bit of read data appearing at SO after the falling edge of SCK.
