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DS28CZ04G-4+T
4Kb I²C/SMBus EEPROM with Nonvolatile PIO
GENERAL DESCRIPTION The DS28CZ04 combines 4Kb (512 x 8) EEPROM
with 4 PIO lines. Communication with the device is
accomplished with an industry standard I²C and
SMBus™ interface. The memory is organized as two
segments of 256 bytes with single byte and up to 16-
byte block write capability. Individual PIO lines may
be configured as inputs or outputs. The power-on
state of PIO programmed as outputs is stored in non-
volatile memory. All PIO may be reconfigured by the
user through the serial interface.
APPLICATIONS • 4G SFP Copper Modules • SFF-8472, SFP Fiber Modules • RAID Systems • Servers
TYPICAL OPERATING CIRCUIT VCC1 VCC2
MAX3982
PE1 LOS
PE0
OUTLEV
IN+ OUT+
IN- OUT-
TX_DISABLE
LOSLEV
GND EP
VCCT
LOS
(from receiver)
Connect to
VCC or GND
VCC
DS28CZ04 SDA
SCL
MRZ
PIO3
PIO0 PIO2
WP PIO1
A2
A1 GND
MOD-DEF1
MOD-DEF2
VEET
VEET
From SFP
connector
Small Form-factor Pluggable (SFP) Circuit
FEATURES 4Kb (512 x 8) EEPROM Organized in Two 256-
Byte Blocks Single Byte and up to 16-Byte EEPROM Write
Sequences Write-Protect Control Pin for the Entire EEPROM
Array Endurance 200k Cycles per Block at 25°C; 10ms
max EEPROM Write Cycle 4 PIO Lines Each PIO is Configured to Input or Output Mode
on Startup by Stored Value All PIOs are Reconfigurable after Startup Serial Interface User-Programmable for I²C Bus
and SMBus Compatibility Supports 100kHz and 400kHz I²C Communica-
tion Speeds Operating Range: 2.0V to 5.25V, -40°C to +85°C 4mm x 4mm 12-Pin TQFN Package
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS28CZ04G-4+ -40°C to +85°C TQFN12-EP* 4x4mm²
DS28CZ04G-4+T -40°C to +85°C TQFN12-EP* 4x4mm²
Tape-and-Reel
*EP = Exposed Paddle
+Denotes lead-free package.
PIN CONFIGURATION 12 11 10 5 6
PIO3
WP
MRZ
VCC
SDA SCL
Thin 12-Lead 4mm × 4mm QFN (Top View)
Package Outline Drawing 21-0139
Package Code T1244+4
DS28CZ04
4Kb I²C/SMBus EEPROM
with Nonvolatile PIO
SMBus is a trademark of Intel Corp.
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.5V, +6V
Maximum Current SDA, SCL, A2, A1, WP, MRZ Pin ±20mA
Maximum Current each PIO Pin ±20mA
Maximum GND and VCC Current 100mA
Operating Temperature Range -40°C to +85°C
Junction Temperature +150°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS (-40°C to +85°C, see Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC 2.0 5.25 V
Standby Current (Note 2) ICCS Bus idle, VCC = 5.25V 1.5 4 µA
Operating Current ICCA Bus active at 400kHz,
VCC = 5.25V 250 500 µA
Programming Current IPROG VCC = 5.25V 500 1000 µA
Power-up Wait Time tPOIP (Note 3) 100 µs
EEPROM Programming Time tPROG 10 ms
Endurance NCYCLE At +25°C (Notes 4, 5) 200k ⎯
Data Retention tRET At +85°C (Notes 5, 6) 40 years
PIO Pins, See Figures 8, 9 LOW-Level Output Voltage VOL 1mA sink current 0 0.4 V
HIGH-Level Output Voltage VOH 500μA source current VCC -
0.5V V
LOW-Level Input Voltage VIL -0.3 0.3 × VCC V
HIGH-Level Input Voltage VIH 0.7 ×
VCC VCC +
0.3V V
Output Data Valid Time tPV 1 µs
PIO Read Setup Time tPS (Note 5) 150 ns
PIO Read Hold Time tPH (Note 5) 150 ns
Leakage Current IL High Impedance, at
VCCMAX -1 +1 µA
SCL, SDA, A2, A1, WP, MRZ Pins (Note 7), See Figure 6 LOW Level Input Voltage VIL -0.3 0.3 × VCC V
HIGH Level Input Voltage VIH (Note 8) 0.7 ×
VCC VCCmax +
0.3V V
Hysteresis of Schmitt Trigger
Inputs Vhys (Notes 5, 9) 0.05 ×
VCC V
LOW Level Output Voltage VOL At 4mA Sink Current,
open drain 0.4 V
Output Fall Time from VIhmin to
VILmax (Notes 5, 10) tof Bus Capacitance from
10pF to 400pF
20 +
0.1CB 250 ns
Pulse Width of Spikes that are
Suppressed by the Input Filter tSP SDA and SCL pins only
(Note 5) 50 ns
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Input Current with an Input
Voltage Between 0.1VCC and
0.9VCCmax
II (Note 11) -10 10 µA
Input Capacitance CI (Notes 5, 9) 10 pF
SCL Clock Frequency fSCL (Note 12) 400 kHz
Bus Time-Out tTIMEOUT (Note 12) 25 75 ms
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
tHD:STA (Note 13) 0.6 µs
VCC ≥ 2.7V 1.3 LOW Period of the SCL Clock
(Note 13) tLOW VCC < 2.7V 1.5 µs
HIGH Period of the SCL Clock tHIGH (Note 13) 0.6 µs
Setup Time for a Repeated
START Condition tSU:STA (Note 13) 0.6 µs
VCC ≥ 2.7V 0.3 0.9 Data Hold Time (Notes 14, 15) tHD:DAT VCC < 2.7V 0.3 1.1 µs
Data Setup Time tSU:DAT (Notes 13, 16) 100 ns
Setup Time for STOP ConditiontSU:STO (Note 13) 0.6 µs
Bus Free Time Between a
STOP and START Condition tBUF (Note 13) 1.3 µs
Capacitive Load for Each Bus
Line CB (Notes 5, 13) 400 pF
Note 1: Specifications at -40°C are guaranteed by design and characterization only and not production tested.
Note 2: To the first order, this current is independent of the supply voltage value.
Note 3: All PIO are tri-stated at beginning of reset prior to setting to Power-On values.
Note 4: This specification is valid for each 16-byte memory block.
Note 5: Not production tested. Guaranteed by design or characterization.
Note 6: EEPROM writes can become nonfunctional after the data-retention time is exceeded. Long-time
storage at elevated temperatures is not recommended; the device can lose its write capability after 10
years at +125°C or 40 years at +85°C.
Note 7: All values are referenced to VIHmin and VILmax levels.
Note 8: The maximum specification value is guaranteed by design, not production tested.
Note 9: Applies to SDA and SCL.
Note 10: CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
to I²C-Bus Specification v2.1 are allowed.
Note 11: The DS28CZ04 does not obstruct the SDA and SCL lines if VCC is switched off.
Note 12: The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 AND SCL
stays at the same logic level or SDA stays low for this interval, the DS28CZ04 behaves as though it
has sensed a STOP condition.
Note 13: System Requirement
Note 14: The DS28CZ04 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the
SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 15: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL
signal.
Note 16: A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement
tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line trmax + tSU:DAT = 1000 + 250 = 1250ns (according to the
standard-mode I²C-bus specification) before the SCL line is released.
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
PIN DESCRIPTION
PIN NAME FUNCTION A1 Device Address Bit 1 A2 Device Address Bit 2 PIO3 PIO line #3 PIO2 PIO line #2 PIO1 PIO line #1 PIO0 PIO line #0
7 VCC Power Supply Input MRZ Master Reset (active-low). Performs a reset of the serial interface and the PIOs without
power-cycling the device. WP Write Protect input, to be connected to VCC or GND. When connected to VCC, the entire
EEPROM array is write-protected. Normal read/write access when connected to GND.
Changing the pin state during a write access will cause unpredictable results.
10 SCL I²C/SMBus serial clock input; must be tied to VCC through a pullup resistor.
11 SDA I²C/SMBus bidirectional serial data line; must be tied to VCC through a pullup resistor.
12 GND Ground supply for the device.
EP GND Exposed Paddle. Solder evenly to the board’s ground plane for proper operation. See
Application Note 3273 for additional information.
OVERVIEW The DS28CZ04 consists of a serial I²C/SMBus interface, 4Kb of EEPROM and four bidirectional PIO channels, as
shown in the block diagram in Figure 1. The device communicates with a host processor through its I²C interface in
standard-mode or in fast-mode; the user can switch the interface from I²C bus to SMBus mode. Two address pins
allow 4 DS28CZ04 to reside on the same bus segment. A Master reset pin permits a full device reset without power
cycling.
The device has a memory range of 512 bytes, organized as two segments (lower half, upper half) of 256 bytes
(Figure 2). The memory map and device addressing is compatible with SFF-8472 Digital Diagnostic address
assignments. The entire EEPROM can be write-protected by tying the WP pin to VCC. The PIO pins can be
accessed through one address (= single-address mode) or through separate addresses (= multi-address mode).
PIO direct access addressing allows fast generation of data patterns and fast sampling.
The DS28CZ04 includes several EEPROM registers for the user to select whether the device powers up in SFF
mode and to define the power-on default conditions for individual PIO output state (high, low, in output mode),
individual PIO data direction (in, out), individual PIO output type (push-pull, open drain), individual PIO read bit
inversion (true, false). Once powered up, the PIO settings can be overwritten through SRAM registers without
affecting the power-on defaults.
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
Figure 1. Block Diagram Serial
Interface
Control
Power
Distribu-
tion
VCC
GND
SCL
SDA
A2
A1
4-Kbit
EEPROM
PIO
Control
PIO0
PIO1
PIO2
PIO3
WP
MRZ
Figure 2A. Memory Map (Device Address = A0h)
ADDRESS TYPE ACCESS DESCRIPTION 00h to 74h EEPROM R/W User memory
75h EEPROM R/W Special function/user memory; controls whether
device powers-up into SFF Mode
76h EEPROM R/W Power-on default for PIO output state and
direction for all PIOs
77h EEPROM R/W Power-on default for PIO output type and read-
inversion for all PIOs
78h to 79h ⎯ R Reserved (reads FFh)
7Ah SRAM R/W Direction setting for all PIOs and device
control/status register
7Bh SRAM R/W PIO read-inversion and PIO output type for all
PIOs
7Ch to 7Fh SRAM R/W PIO Read/Write Access Registers
80h to FFh EEPROM R/W User memory
Figure 2B. Memory Map (Device Address = A2h)
ADDRESS TYPE ACCESS DESCRIPTION 00h to 6Dh EEPROM R/W User memory
EEPROM R/W SFF Mode off: User memory 6Eh ⎯ R SFF Mode on: SFF Optional Status Register
6Fh to EFh EEPROM R/W User memory
F0h to FFh ⎯ R Reserved (reads FFh)
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
DETAILED REGISTER DESCRIPTIONS
Special Function/User Memory (Device Address = A0h)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
75h 1 0 1 0 1 0 1 0
There is general read and write access to this address. If programmed to AAh, as shown in the bit pattern above,
the SFF Mode bit at memory address 7Ah (Device Address = A0h) will be set to 1 after the next power-up, acti-
vating SFF mode with memory address 6Eh (device address A2h) functioning as the SFF Optional Status Register.
Factory-default: 00h
Power-on Default for PIO Output State and Direction (Device Address = A0h)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
76h POD3 POD2 POD1 POD0 POV3 POV2 POV1 POV0
There is general read and write access to this address. Factory-default: F0h
BIT DESCRIPTION BIT(S) DEFINITION POV0: Power-On State
PIO0 b0 Power-on default output state of PIO0
POV1: Power-On State
PIO1 b1 Power-on default output state of PIO1
POV2: Power-On State
PIO2 b2 Power-on default output state of PIO2
POV3: Power-On State
PIO3 b3 Power-on default output state of PIO3
POD0: Power-On
Direction PIO0 b4 Power-on default direction of PIO0; 0 ⇒ output, 1 ⇒ input
POD1: Power-On
Direction PIO1 b5 Power-on default direction of PIO1; 0 ⇒ output, 1 ⇒ input
POD2: Power-On
Direction PIO2 b6 Power-on default direction of PIO2; 0 ⇒ output, 1 ⇒ input
POD3: Power-On
Direction PIO3 b7 Power-on default direction of PIO3; 0 ⇒ output, 1 ⇒ input
Power-on Default for PIO Output Type and Read Inversion (Device Address = A0h)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
77h POT3 POT2 POT1 POT0 PIM3 PIM2 PIM1 PIM0
There is general read and write access to this address. Factory-default: F0h
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
BIT DESCRIPTION BIT(S) DEFINITION PIM0: Power-On Read
Inversion PIO0 b0 Power-on default state of read-inversion bit of PIO0; 0 ⇒ no inversion,
1 ⇒ inversion
PIM1: Power-On Read
Inversion PIO1 b1 Power-on default state of read-inversion bit of PIO1; 0 ⇒ no inversion,
1 ⇒ inversion
PIM2: Power-On Read
Inversion PIO2 b2 Power-on default state of read-inversion bit of PIO2; 0 ⇒ no inversion,
1 ⇒ inversion
PIM3: Power-On Read
Inversion PIO3 b3 Power-on default state of read-inversion bit of PIO3; 0 ⇒ no inversion,
1 ⇒ inversion
POT0: Power-On Output
Type PIO0 b4 Power-on default output type of PIO0; 0 ⇒ push-pull, 1 ⇒ open drain
POT1: Power-On Output
Type PIO1 b5 Power-on default output type of PIO1; 0 ⇒ push-pull, 1 ⇒ open drain
POT2: Power-On Output
Type PIO2 b6 Power-on default output type of PIO2; 0 ⇒ push-pull, 1 ⇒ open drain
POT3: Power-On Output
Type PIO3 b7 Power-on default output type of PIO3; 0 ⇒ push-pull, 1 ⇒ open drain
Direction and Control/Status Register (Device Address = A0h)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
7Ah ADMD CM BUSY SFF DIR3 DIR2 DIR1 DIR0
There is general read and write access to this address. Bit 5 is read-only. The power-on default of bits 0 to 3 is
copied from memory address 76h (Device Address = A0h) bits 4 to 7, respectively.
BIT DESCRIPTION BIT(S) DEFINITION DIR0: Direction PIO0 b0 Direction of PIO0; 0 ⇒ output, 1 ⇒ input
DIR1: Direction PIO1 b1 Direction of PIO1; 0 ⇒ output, 1 ⇒ input
DIR2: Direction PIO2 b2 Direction of PIO2; 0 ⇒ output, 1 ⇒ input
DIR3: Direction PIO3 b3 Direction of PIO3; 0 ⇒ output, 1 ⇒ input
SFF: SFF Mode Bit b4
SFF Mode control; 0 ⇒ SFF Mode off, 1 ⇒ SFF Mode on.
See Memory Map (Device Address = A2h) and SFF Optional Status
Register description for details. The SFF Mode Bit, when set to 1, does
not change the direction of PIO0 and PIO1 to input.
BUSY: EEPROM Busy
Indicator b5 If this bit reads 1, an EEPROM write cycle (A0h or A2h Device Address)
is in progress. (SMBus mode only; reads 0 in I²C bus mode)
CM: Communication
Mode b6
Selects mode for the serial communication interface. 0: I²C bus mode (power-on default) 1: SMBus mode
ADMD: PIO Address
Mode b7
Selects Address Mode for PIO Read/Write access. See PIO Read/Write
Access Registers for details. 0: Multi-Address Mode (power-on default) 1: Single-Address Mode
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
PIO Read-Inversion and Output Type (Device Address = A0h)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
7Bh OT3 OT2 OT1 OT0 IMSK3 IMSK2 IMSK1 IMSK0
There is general read and write access to this address. The power-on default is copied from memory address 77h
(Device Address = A0h).
BIT DESCRIPTION BIT(S) DEFINITION IMSK0: Read-inversion
control of PIO0 b0 0 ⇒ no inversion, 1 ⇒ data read from PIO0 is inverted
IMSK1: Read-inversion
control of PIO1 b1 0 ⇒ no inversion, 1 ⇒ data read from PIO1 is inverted
IMSK2: Read-inversion
control of PIO2 b2 0 ⇒ no inversion, 1 ⇒ data read from PIO2 is inverted
IMSK3: Read-inversion
control of PIO3 b3 0 ⇒ no inversion, 1 ⇒ data read from PIO3 is inverted
OT0: Output Type of
PIO0 b4 0: ⇒ Push-Pull, 1 ⇒ Open Drain
OT1: Output Type of
PIO1 b5 0: ⇒ Push-Pull, 1 ⇒ Open Drain
OT2: Output Type of
PIO2 b6 0: ⇒ Push-Pull, 1 ⇒ Open Drain
OT3: Output Type of
PIO3 b7 0: ⇒ Push-Pull, 1 ⇒ Open Drain
PIO Read/Write Access Registers (Device Address = A0h)
ADDR b7 b6 b5 b4 b3 b2 b1 b0 PIO Address Mode IV3 IV2 IV1 IV0 OV3 OV2 OV1 OV0 Single
7Ch 1 1 1 IV0 1 1 1 OV0 Multi
00h (no function) Single
7Dh 1 1 1 IV1 1 1 1 OV1 Multi
00h (no function) Single
7Eh 1 1 1 IV2 1 1 1 OV2 Multi
00h (no function) Single
7Fh 1 1 1 IV3 1 1 1 OV3 Multi
There is general read and write access to these registers. Bits shown as 1 have no function; their state cannot be
changed.
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
BIT DESCRIPTION BIT(S) DEFINITION OV0: Output Value of
PIO0 ⎯ Logic output state of PIO0 if DIR0 = 0 (output)
OV1: Output Value of
PIO1 ⎯ Logic output state of PIO1 if DIR1 = 0 (output)
OV2: Output Value of
PIO2 ⎯ Logic output state of PIO2 if DIR2 = 0 (output)
OV3: Output Value of
PIO3 ⎯ Logic output state of PIO3 if DIR3 = 0 (output)
IV0: Input Value of PIO0 ⎯ Logic state read from PIO0 XOR’ed with IMSK0
IV1: Input Value of PIO1 ⎯ Logic state read from PIO1 XOR’ed with IMSK1
IV2: Input Value of PIO2 ⎯ Logic state read from PIO2 XOR’ed with IMSK2
IV3: Input Value of PIO3 ⎯ Logic state read from PIO3 XOR’ed with IMSK3
Figure 3 shows a simplified schematic of a PIO. The flip flops are accessed through the PIO R/W Access Registers
and memory addresses 7Ah and 7Bh (Device Address = A0h). They are initialized at power-up or during reset
according to the data stored at memory addresses 76h and 77h (Device Address = A0h). When a PIO is configured
as input, the PIO output is tri-stated (high impedance). When a PIO is configured as output, the PIO input is the
same as the output state XOR'ed with the corresponding read inversion bit.
Figure 3. PIO Simplified Schematic D Q
CLK
D Q
CLK
D Q
CLK
D Q
CLK
DIRn
OVn
OTn
Vcc
D Q
CLK
IMSKn
PIOn Pin
to Serial Interface
IVn
OTn
from Serial Interface
CLK
DIRn
from Serial Interface
OVn
from Serial Interface
IMSKn
from Serial Interface
Note: OTn, DIRn, OVn and IMSKn are nonvolatile based on power-on register
values (memory addresses 76h and 77h,
device address A0h)
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
SFF Optional Status Register (Device Address = A2h, only if SFF Mode is on)
ADDR b7 b6 b5 b4 b3 b2 b1 b0
6Eh 0 0 0 0 0 TXF LOS 0
This register is read only. The functional assignments of the individual bits are explained in the table below. Bits 0
and 3 to 7 have no function; they always read 0 and cannot be set to 1.
BIT DESCRIPTION BIT(S) DEFINITION LOS: Loss Of Signal b1 Reports the logical state of PIO0; in SFF-8472 compatible modules,
PIO0 is connected to the Loss Of Signal indicator
TXF: TX_FAULT b2 Reports the logical state of PIO1; in SFF-8472 compatible modules,
PIO1 is connected to the TX_FAULT indicator
DEVICE OPERATION The typical use of the DS28CZ04 in an application involves writing to and reading from the memory and accessing
the PIOs. All these activities are controlled through the I²C/SMBus serial interface. Since the DS28CZ04 has
memory areas and registers of different characteristics there are several special cases to consider. See section
Read and Write for details.
Serial Communication Interface
General Characteristics The serial interface uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are
bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no
communication, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain
or open-collector to perform the wired-AND function. Data can be transferred at rates of up to 100kbps in the
Standard-mode, up to 400kbps in the Fast-mode. The DS28CZ04 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The
device that controls the communication is called a “master.” The devices that are controlled by the master are
“slaves.” The DS28CZ04 is a slave device.
Slave Address/Direction Byte To be individually accessed, each device must have a slave address that does not conflict with other devices on
the bus. The slave address to which the DS28CZ04 responds is shown in Figure 4. The slave address is part of the
slave-address/direction byte. The upper 4 bits of the slave address of the DS28CZ04 are set to 1010b. Bits A1 and
A2 correspond to the A1 and A2 pins; to be selected the device must be addressed with A1 and A2 bits matching
the logical state of the respective pins.
Figure 4. DS28CZ04 Slave Address A6 A5 A4 A3 A2 A1 A0 0 1 0 A2 A1 P0 R/W
7-Bit Slave Address
Most Signi-
ficant Bit
Determines
Read or Write
See Text Pin States
DS28CZ04: 4Kb I²C/SMBus EEPROM with Nonvolatile PIO
As a 512 byte memory device, the DS28CZ04 needs 9 address bits to access a memory location. The P0 bit
transmitted in place of the A0 address bit specifies whether the “lower half” (0b) or the “upper half” (1b) of the
memory is addressed. This causes the DS28CZ04 to occupy two logical slave addresses, one for each half of the
memory. Throughout this document, the lower half of the memory is referenced as Device Address A0h and the
upper half as Device Address A2h. The addresses A0h and A2h are correct if the A1 and A2 pins are tied to logic
0. For different conditions at these pins the slave address changes accordingly.
The last bit of the slave-address/direction byte (R/W) defines the data direction. When set to a 0, subsequent data
will flow from master to slave (write access mode); when set to a 1, data will flow from slave to master (read access
mode). Although the P0 bit is also transmitted when accessing the DS28CZ04 in read mode, its value is ignored
(don’t care); instead, the value transmitted in the most recent write access applies.
I²C/SMBus Protocol Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL),
controls the bus access, generates the START and STOP conditions, and determines the number of bytes
transferred on the data line (SDA) between START and STOP. Data is transferred in bytes with the most significant
bit being transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and
slave. During any data transfer, SDA must remain stable whenever the clock line is HIGH. Changes in SDA line
while SCL is high will be interpreted as a START or a STOP. The protocol is illustrated in Figure 5. For detailed
timing references see Figure 6.
Figure 5. I²C/SMBus Protocol Overview SCL
SDA678
ACK9128
MS-bitR/W
Slave Address
ACK
bit
Acknowledgment
from Receiver
ACK
bit
START
Condition
ACK
Repeated if more bytes
are transferred
STOP Condition
Repeated START
Condition
Idle
Bus Idle or Not Busy Both, SDA and SCL, are inactive, i. e., in their logic HIGH states.
START Condition To initiate communication with a slave, the master has to generate a START condition. A START condition is
defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH.
STOP Condition To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as
a change in state of SDA from LOW to HIGH while SCL remains HIGH.
Repeated START Condition Repeated starts are commonly used for read accesses after having specified a memory address to read from in a
preceding write access. The master can use a repeated START condition at the end of a data transfer to
immediately initiate a new data transfer following the current one. A repeated START condition is generated the
same way as a normal START condition, but without leaving the bus idle after a STOP condition.
