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DS28CN01U-A00+-DS28CN01U-A00+T-DS28CN01U-W0D+1T-C
1Kbit I²C/SMBus EEPROM with SHA-1 Engine
General DescriptionThe DS28CN01 combines 1024 bits of EEPROM with
challenge-and-response authentication security imple-
mented with the Federal Information Publications (FIPS)
180-1/180-2 and ISO/IEC 10118-3 Secure Hash
Algorithm (SHA-1). The memory is organized as four
32-byte pages. Data copy protection and EPROM emu-
lation features are supported for each memory page.
Each DS28CN01 has a guaranteed unique factory-pro-
grammed 64-bit registration number. Communicationwith
the DS28CN01 is accomplished through an industry-
standard I2C-compatible and SMBus™-compatible
interface. The SMBus timeout feature resets the
device’s interface if a bus-timeout fault condition is
detected.
ApplicationsPCB Unique Serialization
Accessory and Peripheral Identification
Equipment Registration and License
Management
Network Node Identification
Printer Cartridge Configuration and Monitoring
Medical Sensor Authentication and Calibration
System Intellectual Property Protection
Features1024 Bits of EEPROM Memory Partitioned Into
Four Pages of 256 BitsDedicated Hardware-Accelerated SHA-1 Engine
for Generating SHA-1 MACsEEPROM Memory Pages Can Be Individually
Copy Protected or Put Into EPROM Mode
(Program from 1 to 0 Only)Write Access Requires Knowledge of the Secret
and the Capability of Computing and Transmitting
a 160-Bit MAC as AuthorizationUnique, Factory-Programmed, and Tested 64-Bit
Registration Number Assures Absolute
Traceability Because No Two Parts are AlikeEndurance 200,000 Cycles at +25°CSerial Interface User Programmable for I2C Bus
and SMBus CompatibilitySupports 100kHz and 400kHz I2C Communication
Speeds+5.5V Tolerant Interface PinsOperating Ranges: +1.62V to +5.5V, -40°C to +85°C8-Pin µSOP Package
DS28CN01
1Kb I2C/SMBus EEPROM with SHA-1 EngineμSOP7N.C.AD1VCCAD0
SCLN.C.36
SDAGND45
DS28CN01
TOP VIEW
Pin ConfigurationOrdering InformationRev 2; 11/09
ABRIDGED DATASHEET+Denotes a lead(Pb)-free/RoHS-compliant package.
T = Tape and reel.
PART TEMP RANGE PIN-PACKAGE DS28CN01U-A00+ -40°C to +85°C 8 μSOP
DS28CN01U-A00+T -40°C to +85°C 8 μSOP
Typical Operating Circuit appears at end of data sheet.SMBus is a trademark of Intel Corp.
DS28CN01
1Kb I2C/SMBus EEPROM with SHA-1 Engine
ABRIDGED DATASHEET
ABSOLUTE MAXIMUM RATINGS
ELECTRICAL CHARACTERISTICS(TA= -40°C to +85°C.) (Note 1)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on Any Pin Relative to Ground.........-0.5V to +6V
Maximum Current on Any Pin...........................................±20mA
Operating Temperature Range...........................-40°C to +85°C
Junction Temperature......................................................+150°C
Storage Temperature Range.............................-55°C to +125°C
Soldering Temperature...........................Refer to the IPC/JEDEC
J-STD-020 Specification.
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC 1.62 5.50 V
Standby Current ICCS Bus idle, VCC = +5.5V 5.5 μA
Operating Current ICCA Bus active at 400kHz, VCC = +5.5V 500 μA
Power-Up Wait Time tPOIP (Note 2) 5 μs
EEPROM VCC 2.0V 10 Programming Time tPROG VCC < 2.0V 45 ms
Programming Current IPROG VCC = +5.5V 1.2 mA
At +25°C 200,000 Endurance (Notes 3, 4, 5) NCY At +85°C 50,000 —
Data Retention (Notes 6, 7, 8) tDR At +85°C 40 Years
SHA-1 ENGINE SHA-1 Computation Time tCSHA See full version of the data sheet. ms
SHA-1 Computation Current ILCSHA See full version of the data sheet. mA
SCL, SDA, AD1, AD0 PINS (Notes 9, 10) VCC 2.0V -0.3 0.3 ×
VCC Low-Level Input Voltage VIL
VCC < 2.0V -0.3 0.25 ×
VCC
VCC 2.0V 0.7 ×
VCC VCCMAX
+ 0.3V High-Level Input Voltage VIH
VCC < 2.0V 0.8 ×
VCC VCCMAX
+ 0.3V
VCC 2.0V 0.05 ×
VCC Hysteresis of Schmitt Trigger
Inputs (Note 2) VHYS
VCC < 2.0V 0.1 ×
VCC
VCC 2.0V 0.4 Low-Level Output Voltage at
4mA Sink Current, Open Drain VOL
VCC < 2.0V 0.2 ×
VCC
DS28CN01
Note 1:Specifications at -40°C are guaranteed by design and characterization only and not production tested.
Note 2:Guaranteed by design, characterization, and/or simulation only and not production tested.
Note 3:This specification is valid for each 8-byte memory row.
Note 4:Write-cycle endurance is degraded as TAincreases.
Note 5:Not 100% production tested; guaranteed by reliability monitor sampling.
Note 6:Data retention is degraded as TAincreases.
Note 7:Guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to data
sheet limit at operating temperature range is established by reliability testing.
Note 8:EEPROM writes can become nonfunctional after the data retention time is exceeded. Long-time storage at elevated tem-
peratures is not recommended; the device can lose its write capability after 10 years at +125°C or 40 years at +85°C.
Note 9:All values are referred to VIH(MIN)and VIL(MAX)levels.
Note 10:See Figure 3.
Note 11:CB= Total capacitance of one bus line in pF. If mixed with high-speed-mode devices, faster fall times according to I2C
Bus Specification v2.1 are allowed.
ELECTRICAL CHARACTERISTICS (continued)(TA= -40°C to +85°C.) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC 2.0V 20 +
0.1CB 250 Output Fall Time from VIH(MIN) to
VIL(MAX) with a Bus Capacitance
from 10pF to 400pF (Notes 2, 11)
tOF
VCC < 2.0V 20 +
0.1CB 300
ns
Pulse Width of Spikes that are
Suppressed by the Input Filter tSP (Note 2) 50 ns
Input Current with an Input
Voltage Between 0.1VCC and
0.9VCCMAX
II (Note 12) -10 +10 μA
Input Capacitance CI (Note 2) 10 pF
SCL Clock Frequency fSCL (Note 13) 400 kHz
Bus Timeout tTIMEOUTCM bit = 1 (Note 13) 25 75 ms
Hold-Time (Repeated) START
Condition; After this Period, the
First Clock Pulse is Generated
tHD:STA (Note 14) 0.6 μs
VCC 2.7V 1.3
VCC 2.0V 1.5 Low Period of the SCL Clock
(Note 14) tLOW
VCC < 2.0V 1.9
μs
High Period of the SCL Clock tHIGH (Note 14) 0.6 μs
Setup Time for a Repeated
START Condition tSU:STA (Note 14) 0.6 μs
VCC 2.7V 0.3 0.9
VCC 2.0V 0.3 1.1 Data Hold Time (Notes 15, 16) tHD:DAT
VCC < 2.0V 0.3 1.5
μs
Data Setup Time tSU:DAT (Notes 2, 14, 17) 100 ns
Setup Time for STOP Condition tSU:STO (Note 14) 0.6 μs
Bus Free Time Between a STOP
and START Condition tBUF (Note 14) 1.3 μs
Capacitive Load for Each Bus
Line CB (Notes 2, 14) 400 pF
1Kb I2C/SMBus EEPROM with SHA-1 Engine
ABRIDGED DATASHEET
DS28CN01
Note 12:The DS28CN01 does not obstruct the SDA and SCL lines if Vccis switched off.
Note 13:The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 andSCL stays at the same logic
level or SDA stays low for this interval, the DS28CN01 behaves as though it has sensed a STOP condition.
Note 14:System requirement.
Note 15:The DS28CN01 provides a hold time of at least 300ns for the SDA signal (referred to the VIH(MIN)of the SCL signal) to
bridge the undefined region of the falling edge of SCL.
Note 16:The master can provide a hold time of 0ns minimum when writing to the device. This 0ns minimum is guaranteed by
design, characterization, and/or simulation only, and not production tested.
Note 17:A fast-mode I2C bus device can be used in a standard-mode I2C bus system, but the requirement tSU:DAT≥250ns must
then be met. This is automatically the case if the device does not stretch the low period of the SCL signal. If such a device
does stretch the low period of the SCL signal, it must output the next data bit to the SDA line tRMAX+ tSU:DAT= 1000 + 250
= 1250ns (according to the standard-mode I2C bus specification) before the SCL line is released.
1Kb I2C/SMBus EEPROM with SHA-1 Engine
ABRIDGED DATASHEET
Pin Description
PIN NAME FUNCTION 1 AD0 Device Address Input Pin to Select the Slave Address. Sets slave address bits A[1:0] and must be
connected to either GND, SDA, SCL, or VCC.
2 AD1 Device Address Input Pin to Select the Slave Address. Sets slave address bits A[3:2] and must be
connected to either GND, SDA, SCL, or VCC.
3, 7 N.C. No Connection
4 GND Ground Supply
5 SDA I2C/SMBus Bidirectional Serial Data Line. This pin must be connected to VCC through a pullup resistor.
6 SCL I2C/SMBus Serial Clock Input. This pin must be connected to VCC through a pullup resistor.
8 VCC Power-Supply Input
Detailed DescriptionThe DS28CN01 features a serial I2C/SMBus interface,
1Kb of SHA-1 secure EEPROM, a register page, and a
unique registration number, as shown in the Block
Diagram. The device communicates with a host proces-
sor through its I2C interface in standard mode or in fast
mode. The user can switch the interface from I2C bus
mode to SMBus mode. Two 4-level address pins allow
16 DS28CN01s to reside on the same bus segment.
Device OperationRead and write access to the DS28CN01 is controlled
through the I2C/SMBus serial interface. Since the
DS28CN01 has memory areas and registers of different
characteristics, there are several special cases to con-
sider. See the Read and Writesection in the full data
sheet for details.
Serial Communication InterfaceThe serial interface uses a data line (SDA) plus a clock
signal (SCL) for communication. Both SDA and SCL are
bidirectional lines, connected to a positive supply volt-
age through a pullup resistor. When there is no commu-
nication, both lines are high. The output stages of
devices connected to the bus must have an open-drain
or open-collector output to perform the wired-AND
function. Data can be transferred at rates of up to
100kbps in the standard mode, and up to 400kbps in
the fast mode. The DS28CN01 works in both modes.
A device that sends data on the bus is defined as a
transmitter and a device receiving data is a receiver.
The device that controls the communication is called a
master. The devices that are controlled by the master
are slaves. The DS28CN01 is a slave device.
ELECTRICAL CHARACTERISTICS (continued)(TA= -40°C to +85°C.) (Note 1)
DS28CN01
1Kb I2C/SMBus EEPROM with SHA-1 EngineDS28CN01
I2C/SMBUS
FUNCTION
CONTROL
MEMORY AND
SHA-1 ENGINE
CONTROL
MAC
COMPARATOR
MAC OUTPUT
BUFFER
8-BYTE WRITE
BUFFER
64-BIT UNIQUE
NUMBER
SHA-1
ENGINE
SECRET
MEMORY
REGISTER
PAGE
USER EEPROM
4 PAGES
OF 32 BYTES
SCL
VCC
SDA
AD_
Block Diagram
Slave Address/Direction ByteTo be individually accessed, each device must have a
slave address that does not conflict with other devices
on the bus. The slave address to which the DS28CN01
responds is shown in Figure 1. The slave address is
part of the slave-address/direction byte. The upper 3
bits of the DS28CN01 slave address are set to 101b.
The AD0 pin controls address A0 and A1; AD1 controls
A2 and A3. AD0 and AD1 can be connected to GND,
VCC, SCL, or SDA. Table 1 shows the translation of
these four pin states to binary addresses. To be select-
ed, the device must be addressed with A0 to A3 match-
ing the binary address of the respective pins.
The last bit of the slave-address/direction byte (R/W)
defines the data direction. When set to a 0, subsequent
data flows from master to slave (write-access mode);
when set to a 1, data flows from slave to master (read-
access mode).
MSB
AD1
7-BIT SLAVE ADDRESSA1
AD0
R/W
DETERMINES
READ OR WRITE
4-LEVEL PIN STATES
(SEE THE SLAVE
ADDRESS/DIRECTION
BYTE SECTION)
AD1 A3 A2 AD0 A1 A0 GND 0 0 GND 0 0
VCC 0 1 VCC 0 1
SCL 1 0 SCL 1 0
SDA 1 1 SDA 1 1
Table 1. Pin State to Binary Translation
ABRIDGED DATASHEET
DS28CN01
1Kb I2C/SMBus EEPROM with SHA-1 EngineSDA
SCL
IDLE
START
CONDITION STOP CONDITION
REPEATED START
SLAVE
ADDRESS
R/WACKACKDATAACK/
NACK
DATA
MSB FIRSTMSBLSBMSBLSB
REPEATED IF MORE BYTES
ARE TRANSFERRED
Figure 2. I2C/SMBus Protocol Overview
2C/SMBus ProtocolData transfers can be initiated only when the bus is not
busy. The master generates the SCL, controls the bus
access, generates the START and STOP conditions,
and determines the number of bytes transferred on the
SDA line between START and STOP. Data is transferred
in bytes with the most significant bit being transmitted
first. After each byte, an acknowledge bit follows to
allow synchronization between master and slave.
During any data transfer, SDA must remain stable
whenever the clock line is high. Changes in the SDA
line while SCL is high are interpreted as a START or a
STOP. The protocol is illustrated in Figure 2. See Figure
3 for detailed timing references.
Bus Idle or Not BusyBoth SDA and SCL are inactive, i.e., in their logic-high
states.
START ConditionTo initiate communication with a slave, the master must
generate a START condition. A START condition is
defined as a change in state of SDA from high to low
while SCL remains high.
STOP ConditionTo end communication with a slave the master must
generate a STOP condition. A STOP condition is
defined as a change in state of SDA from low to high
while SCL remains high.
Repeated START ConditionRepeated STARTs are commonly used for read access-
es after having specified a memory address to read
from in a preceding write access. The master can use a
repeated START condition at the end of a data transfer
to immediately initiate a new data transfer following the
current one. A repeated START condition is generated
the same way as a normal START condition, but without
a preceding STOP condition.
Data ValidWith the exception of the START and STOP condition,
transitions of SDA can occur only during the low state
of SCL. The data on SDA must remain valid and
unchanged during the entire high pulse of SCL plus the
required setup and hold time (tHD:DATafter the falling
edge of SCL and tSU:DATbefore the rising edge of
SCL; see Figure 3). There is one clock pulse per bit of
data. Data is shifted into the receiving device during
the rising edge of the SCL pulse.
When finished with writing, the master must release the
SDA line for a sufficient amount of setup time (minimum
tSU:DAT+ tRin Figure 3) before the next rising edge of
SCL to start reading. The slave shifts out each data bit
on SDA at the falling edge of the previous SCL pulse
and the data bit is valid at the rising edge of the current
SCL pulse. The master generates all SCL clock pulses,
including those needed to read from a slave.
ABRIDGED DATASHEET
