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DS28CM00R-A00+T-DS28CM00R-A00+U
I²C/SMBus Silicon Serial Number
GENERAL DESCRIPTION The DS28CM00 is a low-cost, electronic registration
number to provide an absolutely unique identity that
can be determined with the industry standard I²C and
SMBus interface. The registration number is a
factory-lasered, 64-bit ROM that includes a unique
48-bit serial number, an 8-bit CRC, and an 8-bit
family code (70h). In SMBus mode, the DS28CM00
resets its communication interface if it detects a bus
fault condition.
APPLICATIONS Printed Circuit Board Unique Serialization
Accessory and Peripheral Identification
Equipment Registration and License Management
Network Node Identification
TYPICAL OPERATING CIRCUIT VCC
SDA
SCL
μC
GND
VCC
SDA
SCL
DS28CM00
GND
RP RP
VCC
FEATURES Unique, Factory-Lasered and Tested 64-bit
Registration Number (8-bit Family Code + 48-bit
Serial Number + 8-bit CRC) SMBus-Compatible I²C Serial Interface Supports 100kHz and 400kHz Communication
Speeds 5V Tolerant Interface Pins Operating Range: 1.8V ±10% to 5V ±5%, -40°C
to +85°C 5-Pin SOT23 Package
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS28CM00R-A00+T -40°C to +85°C SOT23-5
Tape-and-Reel
+Denotes lead-free package.
PIN CONFIGURATION 4SCL
GND
SDA
VCC
DS28CM00
I²C/SMBus Silicon Serial Number
SOT23
DS28CM00: I²C/SMBus Silicon Serial Number
ABSOLUTE MAXIMUM RATINGS Voltage Range on Any Pin Relative to Ground -0.5V, +6V
Maximum Current Into Any Pin ±20mA
Operating Temperature Range -40°C to +85°C
Junction Temperature +150°C
Storage Temperature Range -55°C to +125°C
Soldering Temperature See IPC/JEDEC J-STD-020
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only,
and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is
not implied. Exposure to the absolute maximum rating conditions for extended periods may affect device.
ELECTRICAL CHARACTERISTICS (-40°C to +85°C, see Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS Supply Voltage VCC 1.62 5.25 V
Standby Current ICCS Bus idle, VCC = 5.25V 3 μA
Operating Current ICCA Bus active at 400kHz, VCC
= 5.25V 200 μA
SCL, SDA Pins (Note 2) See Figure 5 VCC ≥ 2.0V -0.3 0.3 ×
VCC LOW Level Input Voltage VIL
VCC < 2.0V -0.3 0.25 ×
VCC
VCC ≥ 2.0V 0.7 ×
VCC VCCmax +
0.3V HIGH Level Input Voltage
(Note 3) VIH
VCC < 2.0V 0.8 ×
VCC VCCmax +
0.3V
VCC ≥ 2.0V 0.05 ×
VCC Hysteresis of Schmitt Trigger
Inputs (Note 4) Vhys
VCC < 2.0V 0.1 ×
VCC
LOW Level Output Voltage at
4mA Sink Current VOL 0.4 V
VCC ≥ 2.0V 20 +
0.1Cb 250 Output Fall Time from VIhmin to
VILmax with a Bus Capacitance
from 10pF to 400pF (Notes 4,
5)
tof
VCC < 2.0V 20 +
0.1Cb 450
ns
Pulse Width of Spikes that are
Suppressed by the Input Filter tSP SDA and SCL pins only
(Note 4) 50 ns
Input Current with an Input
Voltage Between 0.1VCC and
0.9VCCmax
Ii (Note 6) -10 10 μA
Input Capacitance Ci (Note 4) 10 pF
VCC ≥ 2.0V 400 SCL Clock Frequency (Note 7) fSCL VCC < 2.0V 344 kHz
Bus Time-out tTIMEOUT (Note 7) 25 75 ms
Hold Time (Repeated) START
Condition. After this Period, the
First Clock Pulse is Generated.
tHD:STA (Note 8) 0.6 μs
VCC ≥ 2.7V 1.3
VCC ≥ 2.0V 1.5 LOW Period of the SCL Clock
(Note 8) tLOW
VCC < 2.0V 2.3
μs
HIGH Period of the SCL Clock tHIGH (Note 8) 0.6 μs
DS28CM00: I²C/SMBus Silicon Serial Number
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS VCC ≥ 2.7V 0.3 0.9
VCC ≥ 2.0V 0.3 1.1 Data Hold Time (Notes 9, 10) tHD:DAT
VCC < 2.0V 0.3 1.7
μs
Data Setup Time tSU:DAT (Notes 8, 11) 100 ns
Setup Time for STOP ConditiontSU:STO (Note 8) 0.6 μs
Bus Free Time Between a
STOP and START Condition tBUF (Note 8) 1.3 μs
Capacitive Load for Each Bus
Line Cb (Notes 4, 8) 400 pF
Note 1: Specifications at -40°C are guaranteed by design and characterization only and not production tested.
Note 2: All values are referred to VIHmin and VILmax levels.
Note 3: The maximum specification value is guaranteed by design, not production tested.
Note 4: Not production tested. Guaranteed by design or characterization.
Note 5: CB = total capacitance of one bus line in pF. If mixed with HS-mode devices, faster fall-times according
to I2C-Bus Specification v2.1 are allowed.
Note 6: The DS28CM00 does not obstruct the SDA and SCL lines if VCC is switched off.
Note 7: The minimum SCL clock frequency is limited by the bus timeout feature. If the CM bit is 1 AND SCL
stays at the same logic level or SDA stays low for this interval, the DS28CM00 behaves as though it
has sensed a STOP condition.
Note 8: System Requirement
Note 9: The DS28CM00 provides a hold time of at least 300ns for the SDA signal (referred to the VIHmin of the
SCL signal) to bridge the undefined region of the falling edge of SCL.
Note 10: The maximum tHD:DAT has only to be met if the device does not stretch the low period (tLOW) of the SCL
signal.
Note 11: A Fast-mode I²C-bus device can be used in a standard-mode I²C-bus system, but the requirement
tSU:DAT ≥ 250ns must then be met. This is automatically the case if the device does not stretch the LOW
period of the SCL signal. If such a device does stretch the LOW period of the SCL signal, it must
output the next data bit to the SDA line tr max + tSU:DAT = 1000 + 250 = 1250ns (according to the
standard-mode I²C-bus specification) before the SCL line is released.
PIN DESCRIPTION
PIN NAME FUNCTION 1 SCL Serial interface clock input; must be tied to VCC through a pullup resistor. 5V tolerant input
over 1.62V to 5.25V VCC range. GND Ground supply for the device.
3 SDA Serial interface bi-directional data line; must be tied to VCC through a pullup resistor. 5V
tolerant input/output over 1.62V to 5.25V VCC range.
4 N.C. Not Connected
5 VCC Power Supply Input
OVERVIEW The DS28CM00 consists of a serial interface which provides access to a unique 64-bit Registration number and a
Control Register, as shown in the block diagram in Figure 1. The device communicates with a host processor
through its SMBus compatible I²C bus interface in standard-mode or in fast-mode. Since the network address of
the DS28CM00 is fixed, exactly one device can reside on a bus segment. The Registration Number and Control
Register are located in a linear 9-byte address space (Figure 2).
DS28CM00: I²C/SMBus Silicon Serial Number
Figure 1. Block Diagram SCL
SDA
ROM
Registration
Number
Control
Register
Serial
Interface
VCC
GND
Figure 2. Memory Map
ADDRESS TYPE ACCESS DESCRIPTION 00h ROM Read Device Family Code (70h)
01h ROM Read Serial Number, bits 0 to 7
02h ROM Read Serial Number, bits 8 to 15
03h ROM Read Serial Number, bits 16 to 23
04h ROM Read Serial Number, bits 24 to 31
05h ROM Read Serial Number, bits 32 to 39
06h ROM Read Serial Number, bits 40 to 47
07h ROM Read CRC of Family Code and 48-bit Serial Number
08h SRAM R/W Control Register
Unique Registration Number Each DS28CM00 has a unique Registration Number that is 64 bits long. The registration number begins with the
family code at address 00h followed by the 48-bit serial number (LS-byte at the lower address) and ends at
address 07h with the CRC (Cyclic Redundancy Check) of the first 56 bits. This CRC is generated using the
polynomial X8 + X5 + X4 + 1. Additional information about CRCs is available in Application Note 27. The ROM
Registration Number is not related to the I²C slave address of the device.
Control Register The Control Register at address 08h allows switching between I²C mode and SMBus mode. Only the LS bit of this
register, referred to as the CM bit, has a function. The other 7 bits always read 0 and cannot be changed. When the
CM bit is set to 1 (power-on default), the device is in SMBus mode, which enables the bus timeout function. Setting
the CM bit to 0 puts the device in I²C mode, where the timeout function is disabled. In SMBus mode, the serial
interface times out and is internally reset if SCL is stuck (high or low) or if SDA is stuck low for the duration of
tTIMEOUT or longer. This reset turns the SDA line into an input, ensuring that the device is ready to recognize a
communication start condition.
ADDR b7 b6 b5 b4 b3 b2 b1 b0
08h 0 0 0 0 0 0 0 CM
DS28CM00: I²C/SMBus Silicon Serial Number
DEVICE OPERATION Typically, the DS28CM00 is accessed after power-up to read the 64-bit Registration number, which may serve to
identify the object that the device is embedded in. Write access exists only to the Control Register. Read and write
access are controlled through the I²C/SMBus serial interface. See section Read and Write for details.
Serial Communication Interface
General Characteristics The serial interface uses a data line (SDA) plus a clock signal (SCL) for communication. Both SDA and SCL are
bidirectional lines, connected to a positive supply voltage through a pullup resistor. When there is no
communication, both lines are HIGH. The output stages of devices connected to the bus must have an open-drain
or open-collector to perform the wired-AND function. Data can be transferred at rates of up to 100kbps in the
Standard-mode, up to 400kbps in the Fast-mode. The DS28CM00 works in both modes.
A device that sends data on the bus is defined as a transmitter, and a device receiving data as a receiver. The
device that controls the communication is called a “master.” The devices that are controlled by the master are
“slaves.” The DS28CM00 is a slave device.
Slave Address/Direction Byte To be individually accessed, each device must have a slave address that does not conflict with other devices on
the bus. The slave address to which the DS28CM00 responds is shown in Figure 3. The slave address is part of
the slave-address/direction byte. The last bit of the slave-address/direction byte (R/W) defines the data direction.
When set to a 0, subsequent data will flow from master to slave (write access mode); when set to a 1, data will flow
from slave to master (read access mode).
Figure 3. DS28CM00 Slave Address A6 A5 A4 A3 A2 A1 A0 0 1 0 0 0 0 R/W
7-Bit Slave Address
Most Signi-
ficant Bit
Determines
Read or Write
I²C/SMBus Protocol Data transfers may be initiated only when the bus is not busy. The master generates the serial clock (SCL),
controls the bus access, generates the START and STOP conditions, and determines the number of bytes
transferred between START and STOP (Figure 4). Data is transferred in bytes with the most significant bit being
transmitted first. After each byte follows an acknowledge bit to allow synchronization between master and slave.
During any data transfer, SDA must remain stable whenever the clock line is HIGH. Changes in SDA line while
SCL is high will be interpreted as a START or a STOP. The protocol is illustrated in Figure 4. For detailed timing
references see Figure 5.
DS28CM00: I²C/SMBus Silicon Serial Number
Figure 4. I²C/SMBus Protocol Overview SCL
SDA678
ACK9128
MS-bitR/W
Slave Address
ACK
bit
Acknowledgment
from Receiver
ACK
bit
START
Condition
ACK
Repeated if more bytes
are transferred
STOP Condition
Repeated START
Condition
Idle
Bus Idle or Not Busy Both, SDA and SCL, are inactive, i. e., in their logic HIGH states.
START Condition To initiate communication with a slave, the master has to generate a START condition. A START condition is
defined as a change in state of SDA from HIGH to LOW while SCL remains HIGH.
STOP Condition To end communication with a slave, the master has to generate a STOP condition. A STOP condition is defined as
a change in state of SDA from LOW to HIGH while SCL remains HIGH.
Repeated START Condition Repeated starts are commonly used for read accesses to select a specific data source or address to read from.
The master can use a repeated START condition at the end of a data transfer to immediately initiate a new data
transfer following the current one. A repeated START condition is generated the same way as a normal START
condition, but without leaving the bus idle after a STOP condition.
Data Valid With the exception of the START and STOP condition, transitions of SDA may occur only during the LOW state of
SCL. The data on SDA must remain valid and unchanged during the entire high pulse of SCL plus the required
setup and hold time (tHD:DAT after the falling edge of SCL and tSU:DAT before the rising edge of SCL, see Figure 5).
There is one clock pulse per bit of data. Data is shifted into the receiving device during the rising edge of the SCL
pulse.
When finished with writing, the master must release the SDA line for a sufficient amount of setup time (minimum
tSU:DAT + tR in Figure 5) before the next rising edge of SCL to start reading. The slave shifts out each data bit on
SDA at the falling edge of the previous SCL pulse and the data bit is valid at the rising edge of the current SCL
pulse. The master generates all SCL clock pulses, including those needed to read from a slave.
Acknowledged Usually, a receiving device, when addressed, is obliged to generate an acknowledge after the receipt of each byte.
The master must generate a clock pulse that is associated with this acknowledge bit. A device that acknowledges
must pull SDA LOW during the acknowledge clock pulse in such a way that SDA is stable LOW during the HIGH
period of the acknowledge-related clock pulse plus the required setup and hold time (tHD:DAT after the falling edge of
SCL and tSU:DAT before the rising edge of SCL).
