DS2761BE+ ,High-Precision Li+ Battery MonitorPIN DESCRIPTION Range CC - Charge Control Output Current Accumulation: DC - Discharge Control ..
DS2761BE+025 ,High-Precision Li+ Battery Monitorapplications including remaining capacity estimation, safety monitoring, and battery-specific data ..
DS2762BE+ ,High-Precision Li+ Battery Monitor with Alertsapplications including remaining Internal 25m Sense Resistor capacity estimation, safety monitori ..
DS2762BE+025 ,High-Precision Li+ Battery Monitor with AlertsAPPLICATIONS V V SS IS1 INPROBE PDAs E Cell Phones/Smartphones V PIO ..
DS2762K ,Li+battery monitor evaluation kit DS2762K Li+ Battery Monitor Evaluation Kit
DS2764A ,High-Precision Li+ Battery Monitor with 2-Wire InterfaceELECTRICAL CHARACTERISTICS (2.5V V 5.5V, T = -20°C to +70°C.) DD A PARAMETER SYMBOL CONDITIONS ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5T ,COMPACT AND LIGHTWEIGHTDATA SHEETMINIATURE SIGNAL RELAYEA2 SERIESCOMPACT AND LIGHTWEIGHTDESCRIPTIONThe EA2 series has red ..
DS2761AE+025-DS2761BE+-DS2761BE+025
High-Precision Li+ Battery Monitor
FEATURES Lithium-Ion (Li+) Safety Circuit Overvoltage Protection Overcurrent/Short-Circuit Protection
- Undervoltage Protection
Zero Volt Battery Recovery Charge
Available in Two Configurations:
- Internal 25m Sense Resistor External User-Selectable Sense Resistor
Current Measurement 12-Bit Bidirectional Measurement Internal Sense Resistor Configuration:
0.625mA LSB and ±1.9A Dynamic Range External Sense Resistor Configuration:
15.625V LSB and ±64mV Dynamic
Range
Current Accumulation: Internal Sense Resistor: 0.25mAhr LSB External Sense Resistor: 6.25Vhr LSB
Voltage Measurement with 4.88mV
Resolution
Temperature Measurement Using Integrated
Sensor with 0.125C Resolution
System Power Management and Control
Feature Support
32 Bytes of Lockable EEPROM
16 Bytes of General-Purpose SRAM
Dallas 1-Wire® Interface with Unique 64-bit
Device Address
Low Power Consumption:
- Active Current: 60A typ, 90A max
- Sleep Current: 1A typ, 2A max
PIN CONFIGURATION
PIN DESCRIPTION - Charge Control Output - Discharge Control Output
DQ - Data Input/Output
PIO - Programmable I/O Pin
PLS - Battery Pack Positive Terminal Input - Power Switch Sense Input
VIN - Voltage-Sense Input
VDD - Power-Supply Input (2.5V to 5.5V)
VSS - Device Ground
SNS - Sense Resistor Connection
IS1 - Current-Sense Input
IS2 - Current-Sense Input
SNS Probe - Do Not Connect
VSS Probe - Do Not Connect
DS2761
High-Precision Li+ Battery Monitor
VIN
VDD
PIO
VSS
VSS
VSS
PS
IS1
DS2761
16-Pin TSSOP Package
IS2
SNS
SNS3
SNS
PLS
DS2761
Flip-Chip Packaging*
Top View
PLS DC DQ
CC IS2
VIN IS1
VDD PIO PS
SNS
VSS
1 2 3 4
SNS
Probe
VSS
Probe
* Mechanical drawing for the 16-pin TSSOP and DS2761 flip-chip package can be found at:
http://pdfserv.maxim-ic.com/arpdf/Packages/16tssop.pdf
http://pdfserv.maxim-ic.com/arpdf/Packages/chips/2761x.pdf
DS2761
ORDERING INFORMATION
PART MARKING DESCRIPTION DS2761AE+ D2761EA TSSOP, External Sense Resistor, 4.275V VOV, Lead-Free
DS2761BE+ D2761EB TSSOP, External Sense Resistor, 4.35V VOV, Lead-Free
DS2761AE+T&R D2761EA DS2761AE+ on Tape-and-Reel, Lead-Free
DS2761BE+T&R D2761EB DS2761BE+ on Tape-and-Reel, Lead-Free
DS2761AE+025 2761A25 TSSOP, 25m Sense Resistor, 4.275V VOV, Lead-Free
DS2761BE+025 2761B25 TSSOP, 25m Sense Resistor, 4.35V VOV, Lead-Free
DS2761AE+025/T&R 2761A25 DS2761AE+025 in Tape-and-Reel, Lead-Free
DS2761BE+025/T&R 2761B25 DS2761BE+025 in Tape-and-Reel, Lead-Free
DS2761AX-025/T&R DS2761AR Flip-Chip, 25m Sense Resistor, Tape-and-Reel, 4.275V VOV
DS2761BX-025/T&R DS2761BR Flip-Chip, 25m Sense Resistor, Tape-and-Reel, 4.35V VOV
DS2761AX/T&R DS2761A Flip-Chip, External Sense Resistor, Tape-and-Reel, 4.275V VOV
DS2761BX/T&R DS2761B Flip-Chip, External Sense Resistor, Tape-and-Reel, 4.35V VOV
DS2761AE D2761EA TSSOP, External Sense Resistor, 4.275V VOV
DS2761BE D2761EB TSSOP, External Sense Resistor, 4.35V VOV
DS2761AE/T&R D2761EA DS2761AE on Tape-and-Reel
DS2761BE/T&R D2761EB DS2761BE on Tape-and-Reel
DS2761AE-025 2761A25 TSSOP, 25m Sense Resistor, 4.275V VOV
DS2761BE-025 2761B25 TSSOP, 25m Sense Resistor, 4.35V VOV
DS2761AE-025/T&R 2761A25 DS2761AE-025 in Tape-and-Reel
DS2761BE-025/T&R 2761B25 DS2761BE-025 in Tape-and-Reel
Note: Additional VOV options are available, contact Maxim/Dallas Semiconductor sales.
DESCRIPTION The DS2761 high-precision Li+ battery monitor is a data-acquisition, information-storage, and safety-
protection device tailored for cost-sensitive battery pack applications. This low-power device integrates
precise temperature, voltage, and current measurement, nonvolatile (NV) data storage, and Li+ protection
into the small footprint of either a TSSOP package or flip-chip package. The DS2761 is a key component
in applications including remaining capacity estimation, safety monitoring, and battery-specific data
storage.
Through its 1-Wire interface, the DS2761 gives the host system read/write access to status and control
registers, instrumentation registers, and general-purpose data storage. Each device has a unique factory-
programmed 64-bit net address that allows it to be individually addressed by the host system, supporting
multibattery operation.
The DS2761 is capable of performing temperature, voltage, and current measurement to a resolution
sufficient to support process monitoring applications such as battery charge control, remaining capacity
estimation, and safety monitoring. Temperature is measured using an on-chip sensor, eliminating the need
for a separate thermistor. Bidirectional current measurement and accumulation are accomplished using
either an internal 25m sense resistor or an external device. The DS2761 also features a programmable
I/O pin that allows the host system to sense and control other electronics in the pack, including switches,
vibration motors, speakers, and LEDs.
DS2761
Three types of memory are provided on the DS2761 for battery information storage: EEPROM, lockable
EEPROM, and SRAM. EEPROM memory saves important battery data in true NV memory that is
unaffected by severe battery depletion, accidental shorts, or ESD events. Lockable EEPROM becomes
ROM when locked to provide additional security for unchanging battery data. SRAM provides
inexpensive storage for temporary data.
Figure 1. BLOCK DIAGRAM 1-WIRE
INTERFACE
AND
ADDRESS
THERMAL
SENSE
MUX
VOLTAGE
REFERENCE
ADC
REGISTERS AND
USER MEMORY
25m
CHIP GROUND
LOCKABLE EEPROM
SRAM
TEMPERATURE
VOLTAGE
CURRENT
ACCUM. CURRENT
STATUS / CONTROL
LI-ION PROTECTION
VIN
IS1
IS2
SNS
IS2IS1
VSS
PLS
PIO
TIMEBASE
INTERNAL SENSE RESISTOR CONFIGURATION ONLY
ITST
ITST
IRC
VDD
PLS
TEST CURRENT AND RECOVERY CHARGE DETAIL
DS2761
Table 1. DETAILED PIN DESCRIPTION
SYMBOL TSSOP FLIP
CHIP
DESCRIPTION 1 C1
Charge Protection Control Output. Controls an external p-channel high-side charge protection FET.
DC 3 B2
Discharge Protection Control Output. Controls an external p-channel high-side discharge protection FET.
DQ 7 B4
Data Input/Out. 1-Wire data line. Open-drain output driver. Connect this pin to the DATA terminal of the battery pack. Pin has an internal
1A pull-down for sensing disconnection.
PIO 14 E2
Programmable I/O Pin. Used to control and monitor user-defined
external circuitry. Open drain to VSS.
PLS 2 B1
Battery Pack Positive Terminal Input. The DS2761 monitors the pack plus terminal through PLS to detect overcurrent and overload conditions,
as well as the presence of a charge source. Additionally, a charge path to
recover a deeply depleted cell is provided from PLS to VDD. In sleep
mode (with SWEN = 0), any capacitance or voltage source connected to
PLS is discharged internally to VSS through 200A (nominal) to assure
reliable detection of a valid charge source. For details of other internal
connections to PLS and associated conditions see the Li+ Protection
Circuitry section. 10 E4
Power Switch Sense Input. The device wakes up from Sleep Mode when it senses the closure of a switch to VSS on this pin. Pin has an
internal 1A pull-up to VDD.
VIN 16 D1
Voltage Sense Input. The voltage of the Li+ cell is monitored via this input pin. This pin has a weak pullup to VDD.
VDD 15 E1
Power Supply Input. Connect to the positive terminal of the Li+ cell through a decoupling network.
VSS 13,14,
15
F3
Device Ground. Connect directly to the negative terminal of the Li+ cell. For the external sense resistor configuration, connect the sense resistor
between VSS and SNS.
SNS 4,5,6 A3
Sense Resistor Connection. Connect to the negative terminal of the battery pack. In the internal sense resistor configuration, the sense resistor
is connected between VSS and SNS.
IS1 9 D4
Current Sense Input. This pin is internally connected to VSS through a 4.7k resistor. Connect a 0.1F capacitor between IS1 and IS2 to
complete a low-pass input filter.
IS2 8 C4
Current Sense Input. This pin is internally connected to SNS through a 4.7k resistor.
SNS
Probe
N/A C2
Do Not Connect. VSS
N/A D2
Do Not Connect.
DS2761
Figure 2. APPLICATION EXAMPLE
1) RSNS is present for external sense resistor configurations only.
2) RSNS-INT is present for internal sense resistor configurations only.
CC
PLS
DC
SNS
SNS
SNS
DQ
IS2
VIN
VDD
PIO
VSS
VSS
VSS
PS
IS1
DS2761
104
102 x 2
SNS
DS2761
VSS
IS2IS1
voltage sense
PACK+
PACK-
DATA
150
150 1k
150
1k 1k
102
BAT+
BAT-
RSNS(1)
RSNS-INT(2)
RKSRKS
4.7k
DS2761
POWER MODES
The DS2761 has two power modes: active and sleep. While in active mode, the DS2761 continually
measures current, voltage, and temperature to provide data to the host system and to support current
accumulation and Li+ safety monitoring. In sleep mode, the DS2761 ceases these activities. The DS2761
enters sleep mode when any of the following conditions occurs:
The PMOD bit in the Status Register has been set to 1 and the DQ line is low for longer than
2s (pack disconnection)
The voltage on VIN drops below undervoltage threshold VUV for tUVD (cell depletion)
The pack is disabled through the issuance of a SWAP command (SWEN bit = 1)
The DS2761 returns to active mode when any of the following occurs:
The PMOD bit has been set to 1 and the SWEN bit is set to 0 and the DQ line is pulled high
(pack connection)
The PS pin is pulled low (power switch)
The voltage on PLS becomes greater than the voltage on VIN (charger connection) with the SWEN bit
set to 0
The pack is enabled through the issuance of a SWAP command (SWEN bit = 1)
The DS2761 defaults to sleep mode when power is first applied.
Li+ PROTECTION CIRCUITRY
During active mode, the DS2761 constantly monitors cell voltage and current to protect the battery from
overcharge (overvoltage), overdischarge (undervoltage), and excessive charge and discharge currents
(overcurrent, short circuit). Conditions and DS2761 responses are described in the sections below and
summarized in Table 2 and Figure 3.
Table 2. Li+ PROTECTION CONDITIONS AND DS2761 RESPONSES
ACTIVATION CONDITION
NAME THRESHOLD DELAYRESPONSE
RELEASE
THRESHOLD
Overvoltage VIN > VOV tOVD CC high VIN < VCE, or
VIS ≤ -2mV
Undervoltage VIN < VUV tUVD CC, DC high,
Sleep Mode
VPLS > VDD (1)
(charger connected)
Overcurrent, Charge VIS > VOC(2) tOCD CC, DC high VPLS < VDD - VTP (3)
Overcurrent, Discharge VIS < -VOC(2) tOCD DC high VPLS > VDD - VTP (4)
Short Circuit VSNS > VSC tSCD DC high VPLS > VDD - VTP (4)
VIS = VIS1 - VIS2. Logic high = VPLS for CC and VDD for DC. All voltages are with respect to VSS. ISNS references current
delivered from pin SNS.
1) If VDD < 2.2V, release is delayed until the recovery charge current (IRC) passed from PLS to VDD charges the battery and
allows VDD to exceed 2.2V.
2) For the internal sense resistor configuration, the overcurrent thresholds are expressed in terms of current: ISNS > IOC for
charge direction and ISNS < -IOC for discharge direction
3) With test current ITST flowing from PLS to VSS (pulldown on PLS)
4) With test current ITST flowing from VDD to PLS (pullup on PLS)
Overvoltage. If the cell voltage on VIN exceeds the overvoltage threshold, VOV, for a period longer than
overvoltage delay, tOVD, the DS2761 shuts off the external charge FET and sets the OV flag in the
DS2761
charge FET back on (unless another protection condition prevents it). Discharging remains enabled
during overvoltage, and the DS2761 re-enables the charge FET before VIN < VCE if a discharge current of
-80mA (VIS ≤ -2mV) or less is detected.
Undervoltage. If the voltage of the cell drops below undervoltage threshold VUV for a period longer than
undervoltage delay tUVD, the DS2761 shuts off the charge and discharge FETs, sets the UV flag in the
protection register, and enters sleep mode. The DS2761 provides a current-limited recovery charge path
from PLS to VDD to gently charge severely depleted cells during sleep mode.
Overcurrent, Charge Direction. The voltage difference between the IS1 pin and the IS2 pin (VIS = VIS1 -
VIS2) is the filtered voltage drop across the current-sense resistor. If VIS exceeds overcurrent threshold
VOC for a period longer than overcurrent delay tOCD, the DS2761 shuts off both external FETs and sets the
COC flag in the protection register. The charge current path is not re-established until the voltage on the
PLS pin drops below VDD - VTP. The DS2761 provides a test current of value ITST from PLS to VSS to pull
PLS down in order to detect the removal of the offending charge current source.
Overcurrent, Discharge Direction. If VIS is less than -VOC for a period longer than tOCD, the DS2761
shuts off the external discharge FET and sets the DOC flag in the protection register. The discharge
current path is not re-established until the voltage on PLS rises above VDD - VTP. The DS2761 provides a
test current of value ITST from VDD to PLS to pull PLS up in order to detect the removal of the offending
low-impedance load.
Short Circuit. If the voltage on the SNS pin with respect to VSS exceeds short-circuit threshold VSC for a
period longer than short-circuit delay tSCD, the DS2761 shuts off the external discharge FET and sets the
DOC flag in the protection register. The discharge current path is not re-established until the voltage on
PLS rises above VDD - VTP. The DS2761 provides a test current of value ITST from VDD to PLS to pull
PLS up in order to detect the removal of the short circuit.
Figure 3. Li+ PROTECTION CIRCUITRY EXAMPLE WAVEFORMS
SLEEP
MODE
VOV
VCE
VUV
VCELL
VIS
CHARGE
DISCHARGE
-VSC
VOC
-VOC
0
tSCDtOCD
tOCD
tUVD
tOVDVPLS
VDD
ACTIVE
VSS
VSS
INACTIVE
tOVD
(1)
DS2761
Summary. All of the protection conditions described above are OR'ed together to affect the CC and DC
outputs. DC = (Undervoltage) or (Overcurrent, Either Direction) or (Short Circuit) or
(Protection Register Bit DE = 0) or (Sleep Mode) = (Overvoltage) or (Undervoltage) or (Overcurrent, Charge Direction) or (Protection Register
bit CE = 0) or (Sleep Mode)
CURRENT MEASUREMENT
In the active mode of operation, the DS2761 continually measures the current flow into and out of the
battery by measuring the voltage drop across a current-sense resistor. The DS2761 is available in two
configurations: 1) internal 25m current-sense resistor, and 2) external user-selectable sense resistor. In
either configuration, the DS2761 considers the voltage difference between pins IS1 and IS2 (VIS = VIS1 -
VIS2) to be the filtered voltage drop across the sense resistor. A positive VIS value indicates current is
flowing into the battery (charging), while a negative VIS value indicates current is flowing out of the
battery (discharging).
VIS is measured with a signed resolution of 12-bits. The current register is updated in two’s-complement
format every 88ms (128/fsample) with an average of 128 readings. Currents outside the range of the
register are reported at the limit of the range. The format of the current register is shown in Figure 4.
For the internal sense resistor configuration, the DS2761 maintains the current register in units of amps,
with a resolution of 0.625mA and full-scale range of no less than 1.9A (see Note 7 on IFS spec for more
details). The DS2761 automatically compensates for internal sense resistor process variations and
temperature effects when reporting current.
For the external sense resistor configuration, the DS2761 writes the measured VIS voltage to the current
register, with a resolution of 15.625V and a full-scale range of 64mV.
Figure 4. CURRENT REGISTER FORMAT MSB—Address 0E LSB—Address 0F
S 211 210 29 28 27 26 25 2423 22 21 20 X X X
MSb LSb MSb LSb
Units: 0.625mA for Internal Sense Resistor
15.625V for External Sense Resistor
CURRENT ACCUMULATOR
The current accumulator facilitates remaining capacity estimation by tracking the net current flow into
and out of the battery. Current flow into the battery increments the current accumulator while current
flow out of the battery decrements it. Data is maintained in the current accumulator in two’s-complement
format. The format of the current accumulator is shown in Figure 5.
DS2761
When the internal sense resistor is used, the DS2761 maintains the current accumulator in units of amp-
hours, with a resolution of 0.25mAhrs and full-scale range of 8.2Ahrs. When using an external sense
resistor, the DS2761 maintains the current accumulator in units of volt-hours, with a resolution of
6.25Vhrs and a full scale range of 205mVhrs.
The current accumulator is a read/write register that can be altered by the host system as needed.
Figure 5. CURRENT ACCUMULATOR FORMAT MSB—Address 10 LSB—Address 11
S 214 213 212 211 210 29 28 2726 25 24 23 22 21 20
MSb LSb MSb LSb
Units: 0.25mAhrs for Internal Sense Resistor
6.25Vhrs for External Sense Resistor
CURRENT OFFSET COMPENSATION
Current measurement and current accumulation are both internally compensated for offset on a continual
basis minimizing error resulting from variations in device temperature and voltage. Additionally, a
constant bias can be utilized to alter any other sources of offset. This bias resides in EEPROM address
33h in two’s-complement format and is subtracted from each current measurement. The current offset
bias is applied to both the internal and external sense resistor configurations. The factory default for the
current offset bias is a value of 0.
Figure 6. CURRENT OFFSET BIAS Address 33
S 26 25 24 23 22 21 20
MSb LSb
Units: 0.625mA for Internal Sense Resistor
15.625V for External Sense Resistor
VOLTAGE MEASUREMENT
The DS2761 continually measures the voltage between pins VIN and VSS over a range of 0 to 4.75V. The
voltage register is updated in two’s-complement format every 3.4ms with a resolution of 4.88mV.
Voltages above the maximum register value are reported as the maximum value. The voltage register
format is shown in Figure 7.
DS2761
Figure 7. VOLTAGE REGISTER FORMAT MSB—Address 0C LSB—Address 0D
S 29 28 27 26 25 24 23 2221 20 X X X X X
MSb LSb MSb LSb
Units: 4.88mV
TEMPERATURE MEASUREMENT
The DS2761 uses an integrated temperature sensor to continually measure battery temperature.
Temperature measurements are placed in the temperature register every 220ms in two’s-complement
format with a resolution of 0.125°C over a range of 127°C. The temperature register format is shown in
Figure 8.
Figure 8. TEMPERATURE REGISTER FORMAT MSB—Address 18 LSB—Address 19
S 29 28 27 26 25 24 23 2221 20 X X X X X
MSb LSb MSb LSb
Units: 0.125C
PROGRAMMABLE I/O
To use the PIO pin as an output, write the desired output value to the PIO bit in the special feature
register. Writing a 0 to the PIO bit enables the PIO output driver, pulling the PIO pin to VSS. Writing a 1
to the PIO bit disables the output driver, allowing the PIO pin to be pulled high or used as an input. To
sense the value on the PIO pin, read the PIO bit. The DS2761 turns off the PIO output driver and sets the
PIO bit high when in sleep mode or when DQ is low for more than 2s, regardless of the state of the
PMOD bit.
POWER SWITCH INPUT
The DS2761 provides a power control function that uses the discharge protection FET to gate battery
power to the system. The PS pin, internally pulled to VDD through a 1A current source, is continuously
monitored for a low-impedance connection to VSS. If the DS2761 is in sleep mode, the detection of a low
on the PS pin causes the device to transition into active mode, turning on the discharge FET. If the
DS2761 is already in active mode, activity on PS has no effect other than the latching of its logic low
level in the PS bit in the special feature register. The reading of a 0 in the PS bit should be immediately
followed by writing a 1 to the PS bit to ensure that a subsequent low forced on the PS pin is latched into
the PS bit.
DS2761
MEMORY
The DS2761 has a 256-byte linear address space with registers for instrumentation, status, and control in
the lower 32 bytes, with lockable EEPROM and SRAM memory occupying portions of the remaining
address space. All EEPROM and SRAM memory is general purpose except addresses 30h, 31h, and 33h,
which should be written with the default values for the protection register, status register, and current
offset register, respectively. When the MSB of any two-byte register is read, both the MSB and LSB are
latched and held for the duration of the read data command to prevent updates during the read and ensure
synchronization between the two register bytes. For consistent results, always read the MSB and the LSB
of a two-byte register during the same read data command sequence.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allow
the data to be verified by the host system before being copied to EEPROM. All reads and writes to/from
EEPROM memory actually access the shadow RAM. In unlocked EEPROM blocks, the write data
command updates shadow RAM. In locked EEPROM blocks, the write data command is ignored. The
copy data command copies the contents of shadow RAM to EEPROM in an unlocked block of EEPROM
but has no effect on locked blocks. The recall data command copies the contents of a block of EEPROM
to shadow RAM regardless of whether the block is locked or not.
Table 3. MEMORY MAP
ADDRESS (HEX)
DESCRIPTION
READ/WRITE
00 Protection Register R/W
01 Status Register R
02–06 Reserved
07 EEPROM Register R/W
08 Special Feature Register R/W
09–0B Reserved
0C Voltage Register MSB R
0D Voltage Register LSB R
0E Current Register MSB R
0F Current Register LSB R
10 Accumulated Current Register MSB R/W
11 Accumulated Current Register LSB R/W
12–17 Reserved
18 Temperature Register MSB R
19 Temperature Register LSB R
1A–1F Reserved
20–2F EEPROM, block 0 R/W*
30–3F EEPROM, block 1 R/W*
40–7F Reserved
80–8F SRAM R/W
90–FF Reserved
* Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
DS2761
PROTECTION REGISTER
The protection register consists of flags that indicate protection circuit status and switches that give
conditional control over the charging and discharging paths. Bits OV, UV, COC, and DOC are set when
corresponding protection conditions occur and remain set until cleared by the host system. The default
values of the CE and DE bits of the protection register are stored in lockable EEPROM in the
corresponding bits in address 30h. A recall data command for EEPROM block 1 recalls the default values
into CE and DE. The format of the protection register is shown in Figure 9. The function of each bit is
described in detail in the following paragraphs.
Figure 9. PROTECTION REGISTER FORMAT
Address 00
Bit 7 Bit 6 Bit 5 Bit 4Bit 3Bit 2Bit 1 Bit 0
OV UV COC DOC CC DC CE DE
OV—Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltage
condition. This bit must be reset by the host system.
UV—Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an
undervoltage condition. This bit must be reset by the host system.
COC—Charge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a
charge-direction overcurrent condition. This bit must be reset by the host system.
DOC—Discharge Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced a
discharge-direction overcurrent condition. This bit must be reset by the host system. —CC Pin Mirror. This read-only bit mirrors the state of the CC output pin. —DC Pin Mirror. This read-only bit mirrors the state of the DC output pin.
CE—Charge Enable. Writing a 0 to this bit disables charging (CC output high, external charge FET off)
regardless of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by the
presence of any protection conditions. The DS2761 automatically sets this bit to 1 when it transitions
from sleep mode to active mode.
DE—Discharge Enable. Writing a 0 to this bit disables discharging (DC output high, external discharge
FET off) regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject to
override by the presence of any protection conditions. The DS2761 automatically sets this bit to 1 when it
transitions from sleep mode to active mode.
STATUS REGISTER
The default values for the status register bits are stored in lockable EEPROM in the corresponding bits of
address 31h. A recall data command for EEPROM block 1 recalls the default values into the status
register bits. The format of the status register is shown in Figure 10. The function of each bit is described
