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DS2740BU+
High-Precision Coulomb Counter
DS2740
High-Precision Coulomb Counter
FEATURES 15-Bit Bidirectional Current Measurement
(DS2740U) 1.56μV LSB and ±51.2mV Dynamic
Range 78μA LSB and ±2.56A Dynamic
Range with External 20mΩ Sense
Resistor (RSNS) 156μA LSB and ±5.12A Dynamic
Range with External 10mΩ Sense
Resistor (RSNS) 13-Bit Bidirectional Current Measurement
(DS2740BU) 6.25μV LSB and ±51.2mV Dynamic
Range 312μA LSB and ±2.56A Dynamic
Range with External 20mΩ Sense
Resistor (RSNS) 625μA LSB and ±5.12A Dynamic
Range with External 10mΩ Sense
Resistor (RSNS) Analog Input Filter (IS1, IS2) Extends
Dynamic Range for Pulse-Load
Applications Current Accumulation Register
Resolution 6.25μVhr (Both DS2740U and
DS2740BU) 0.3125mAhr with External 20mΩ
RSNS 0.6250mAhr with External 10mΩ
RSNS Dallas 1-Wire® Interface Unique 64-Bit Device Address Standard and Overdrive Timings
(OVD) Low Power Consumption: Active Current: 65μA max Sleep Current: 1μA max
PIN CONFIGURATION PIO
VDD
DQ
VSS
IS1 IS2
PIN DESCRIPTION OVD - 1-Wire Bus Speed Select
PIO - Programmable I/O Pin
SNS - Sense Resistor Input
IS2 - Current-Sense Input
IS1 - Current-Sense Input
VSS - Device Ground, Current-Sense Resistor
Return
DQ - Data Input/Output
VDD - Power-Supply Input (2.7V to 5.5V)
μMAX
(DS2740U, DS2740BU)
SNS12 4
See Table 1 for Ordering Information.
See Table 2 for Detailed Pin Descriptions.
DS2740
Table 1. ORDERING INFORMATION
PART MARKING DESCRIPTION DS2740U D2740 15-Bit Current Resolution, 8-Pin μMAX
DS2740U+ D2740 (see note) 15-Bit Current Resolution, Lead-Free 8-Pin μMAX
DS2740U/T&R D2740 15-Bit Current Resolution, 8-Pin μMAX, Tape-and-Reel
DS2740U+T&R D2740 (see note) 15-Bit Current Resolution, Lead-Free 8-Pin μMAX, Tape-
and-Reel
DS2740BU 2740B 13-Bit Current Resolution, 8-Pin μMAX
DS2740BU+ 2740B (see note) 13-Bit Current Resolution, Lead-Free 8-Pin μMAX
DS2740BU/T&R 2740B 13-Bit Current Resolution, 8-Pin μMAX, Tape-and-Reel
DS2740BU+T&R 2740B (see note) 13-Bit Current Resolution, Lead-Free 8-Pin μMAX, Tape-
and-Reel
Note: A “+” will also be marked on the package next to the pin 1 indicator.
DESCRIPTION The DS2740 provides high-precision current-flow measurement data to support battery-capacity
monitoring in cost-sensitive applications. Current is measured bidirectionally over a dynamic range of 15
bits (DS2740U) or 13 bits (DS2740BU), with the net flow accumulated in a separate 16-bit register.
Through its 1-Wire interface, the DS2740 allows the host system read/write access to status and current
measurement registers. Each device has a unique factory-programmed 64-bit net address that allows it to
be individually addressed by the host system, supporting multibattery slot operation. The interface can be
operated with standard or overdrive timing.
Although the DS2740 is primarily intended for location on the host system, it is also suited for mounting
in the battery pack. The DS2740 and FuelPack™ algorithms, along with host measurements of
temperature and voltage, form a complete and accurate solution for estimating remaining capacity.
FuelPack is a trademark of Dallas Semiconductor.
DS2740
Figure 1. BLOCK DIAGRAM 1-WIRE
INTERFACE
AND
ADDRESS
DQ
PIO
TIMEBASE
CURRENT
ACCUMULATED
CURRENT
STATUS/CONTROL
CHIP
GROUND
SNSIS2VSSIS1
15-Bit + Sign
ADCIS 10 k Ω IS10 kΩ
VDD
RSNS
CF
DS2740
Table 2. DETAILED PIN DESCRIPTIONS
PIN SYMBOL DESCRIPTION OVD 1
1-Wire Bus Speed Control. Input logic level selects the speed of the 1-Wire bus. Logic 1 selects overdrive (OVD) and Logic 0 selects standard
timing (STD). On a multidrop bus, all devices must operate at same
speed.
PIO 2
Programmable I/O Pin. Programmed as input or output through internal registers. Open-drain output sufficient for LED or vibrator activation.
SNS 3
Current-Sense Resistor Input IS2 4
Current-Sense Input. Connected to SNS through a 10kΩ resistor to
allow filtering of the current waveform by an external capacitor.
IS1 5
Current-Sense Input. Connected to VSS through a 10kΩ resistor to allow filtering of the current waveform through an external capacitor.
VSS6
Device Ground, Current-Sense Resistor Return. Connect directly to the negative terminal of the battery cell.
DQ 7
Data I/O Pin. Operates bidirectionally with open-drain output driver. Internal 1µA pulldown aids in sensing pack removal and Sleep-mode
activation.
VDD8
Power-Supply Input. Connects to system voltage supply or positive terminal of battery cell.
Figure 2. APPLICATION EXAMPLE
DS2740VDD
VSS
PIO
DATA
2.7V to 5.5V
System Supply or
Battery Pack Positive
Connection
Battery
Negative
SNS
PIO
IS1IS2
150
330 SNS
104System
GND
OVD*
* 5.6V zener recommended for ESD protection when DATA or PIO
contacts exposed, such as a removable battery pack application
150
DS2740
POWER MODES The DS2740 has two power modes: Active and Sleep. While in Active mode, the DS2740 operates as a
high-precision coulomb counter with current and accumulated current measurement blocks operating
continuously and the resulting values updated in the measurement registers. Read and write access is
allowed to all registers. PIO pin is active. In Sleep mode, the DS2740 operates in a low-power mode with
no current measurement activity. Serial access to current, accumulated current, and status/control
registers is allowed if VDD > 2V.
The DS2740 operating mode transitions from SLEEP to ACTIVE when:
1) DQ > VIH, and VDD > UV threshold, or
2) VDD rises from below UV threshold to above UV threshold.
The DS2740 operating mode transitions from ACTIVE to SLEEP when:
1) VDD falls to UV threshold, or
2) SMOD = 1 and DQ < VIL for 2s.
CURRENT MEASUREMENT In the Active mode of operation, the DS2740 continually measures the current flow into and out of the
battery by measuring the voltage drop across a low-value current-sense resistor, RSNS. To extend the input
range for pulse-type load currents, the voltage signal can be filtered by adding a capacitor between the
IS1 and IS2 pins. The external capacitor and two internal resistors form a lowpass filter at the input of the
ADC. The voltage-sense range at IS1 and IS2 is ±51.2mV. The input converts peak signal amplitudes up
to 102mV as long as the continuous or average signal level (post filter) does not exceed ±51.2mV over
the conversion cycle period. The ADC samples the input differentially at IS1 and IS2 with an 18.6kHz
sample clock and updates the current register at the completion of each conversion cycle. Conversion
times for each resolution option are listed in the tables below. Two resolution options are available.
Figure 3 describes the current measurement register format and resolution for each option. “S” indicates
the sign bit(s).
Figure 3. CURRENT REGISTER FORMAT
DS2740U: Units: 1.5625μV/RSNS, 15-bit + sign resolution, 3.5s conversion period.
DS2740BU: Units: 6.250μV/RSNS, 13-bit + sign resolution, 0.875s conversion period. MSB—Address 0Eh LSB—Address 0Fh
S 2142132122112102928 2726252423222120
MSb LSb MSb LSb
Full-scale magnitude: ±51.2mV
DS2740
CURRENT RESOLUTION (1 LSB) RSNS
PART CONVERSION
TIME VIS1 - VIS220mΩ 15mΩ 10mΩ 5mΩ
DS2740U 3.515s 1.5625μV 78.13μA104.2μA 156.3μA 312.5μA
DS2740BU 0.878s 6.250μV 312.5μA416.7μA 625μA 1.250mA
Every 1024th conversion, the ADC measures its input offset to facilitate offset correction. Offset
correction occurs approximately once per hour in the DS2740U and four times per hour in the
DS2740BU. The resulting correction factor is applied to the subsequent 1023 measurements. During the
offset correction conversion, the ADC does not measure the IS1 to IS2 signal. A maximum error of
1/1024 in the accumulated current register (ACR) is possible, however, to reduce the error, the current
measurement just prior to the offset conversion is displayed in the current register and is substituted for
the dropped current measurement in the current accumulation process. The typical error due to offset
correction is much less than 1/1024.
CURRENT ACCUMULATOR Current measurements are internally summed, or accumulated, at the completion of each conversion
period with the results displayed in the ACR. The accuracy of the ACR is dependent on both the current
measurement and the conversion timebase. The ACR has a range of ±204.8mVh with a LSb of
6.25μVh. Additional registers hold fractional results of each accumulation, however, these bits are not
user accessible.
Read and write access is allowed to the ACR. Whenever the ACR is written, fractional accumulation
results are cleared. Also, a write forces the ADC to measure its offset and update the offset correction
factor. The current measurement and accumulation begin with the second conversion following a write to
the ACR. Figure 4 describes the ACR address, format, and resolution.
Figure 4. CURRENT ACCUMULATOR FORMAT MSB—Address 10h LSB—Address 11h
S 2142132122112102928 2726252423222120
MSb LSb MSb LSb
Units: 6.25μVh/RSNS
ACR LSB RSNS
PART UPDATE
INTERVAL VIS1 - VIS220mΩ 15mΩ 10mΩ 5mΩ
DS2740U 3.515s
DS2740BU 0.878s 6.25μVh 312.5μAh 416.7μAh 625μAh 1.250mAh
DS2740
ACR RANGE RSNS
PART VIS1 - VIS220mΩ 15mΩ 10mΩ 5mΩ
DS2740U
DS2740BU ±204.8mVh ±10.24Ah ±13.65Ah ±20.48Ah ±40.96Ah
MEMORY The DS2740 has memory space with registers for instrumentation, status, and control. When the MSB of
a two-byte register is read, both the MSB and LSB are latched and held for the duration of the Read Data
command to prevent updates during the read and ensure synchronization between the two register bytes.
For consistent results, always read the MSB and the LSB of a two-byte register during the same Read
Data command sequence.
Table 3. MEMORY MAP
ADDRESS (HEX) DESCRIPTION READ/WRITE 00 Reserved —
01 Status Register R/W
02 to 07 Reserved —
08 Special Feature Register R/W
09 to 0D Reserved —
0E Current Register MSB R
0F Current Register LSB R
10 Accumulated Current Register MSB R/W
11 Accumulated Current Register LSB R/W
12 to FF Reserved —
STATUS REGISTER The format of the status register is shown in Figure 5. The function of each bit is described in detail in the
following paragraphs.
Figure 5. STATUS REGISTER FORMAT ADDRESS 01h
BIT 7 BIT 6 BIT 5 BIT 4BIT 3BIT 2BIT 1 BIT 0 SMOD X RNAOPX X X X
SMOD—SLEEP Mode Enable. A value of 1 allows the DS2740 to enter Sleep mode when DQ is low for 2s. A value of 0 disables DQ related transitions to Sleep mode. The power-up default of SMOD = 0.
RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the Read Net Address command to 33h, while a 1 sets the opcode to 39h. The power-up default of RNAOP = 0.
X—Reserved bits.
DS2740
SPECIAL FEATURE REGISTER The format of the special feature register is shown in Figure 6. The function of each bit is described in
detail in the following paragraphs.
Figure 6. SPECIAL FEATURE REGISTER FORMAT ADDRESS 08h
BIT 7 BIT 6 BIT 5 BIT 4BIT 3BIT 2BIT 1 BIT 0 PIO X X X X X X
PIO—PIO Pin Sense and Control. This bit is read and write enabled. Writing a 0 to the PIO bit enables the PIO open-drain output driver, forcing the PIO pin low. Writing a 1 to the PIO bit disables the output
driver, allowing the PIO pin to be pulled high or used as an input. Reading the PIO bit returns the logic
level forced on the PIO pin. Note that if PIO is left floating, the weak pulldown brings the pin low. PIO
resets to a 1 at initial power up, when the DS2740 enters Sleep mode, or DQ low > tSLEEP (independent of
the SMOD pin).
X—Reserved Bits.
1-Wire BUS SYSTEM The 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a
1-Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the
DS2740 is a slave device. The bus master is typically a microprocessor in the host system. The discussion
of this bus system consists of four topics: 64-bit net address, hardware configuration, transaction
sequence, and 1-Wire signaling.
64-BIT NET ADDRESS Each DS2740 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first
eight bits are the 1-Wire family code (36h for DS2740). The next 48 bits are a unique serial number. The
last eight bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 7). The 64-bit net
address and the 1-Wire I/O circuitry built into the device enable the DS2740 to communicate through the
1-Wire protocol detailed in the 1-Wire Bus System section of this data sheet.
Figure 7. 1-Wire NET ADDRESS FORMAT 8-BIT CRC 48-BIT SERIAL NUMBER 8-BIT FAMILY
CODE (36h)
MSb LSb
CRC GENERATION The DS2740 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure
error-free transmission of the address, the host system can compute a CRC value from the first 56 bits of
the address and compare it to the CRC from the DS2740. The host system is responsible for verifying the
CRC value and taking action as a result. The DS2740 does not compare CRC values and does not prevent
a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC can result
