DS2740BU ,High-Precision Coulomb CounterPin Descriptions.(DS2740B) 6.25V LSB and ±51.2mV Dynamic
DS2740BU ,High-Precision Coulomb CounterBLOCK DIAGRAMVDDPIOSTATUS/CONTROL1-WIREACCUMULATEDDQINTERFACETIMEBASECURRENTANDADDRESSCURRENT15-Bit ..
DS2740BU ,High-Precision Coulomb CounterFEATURES 15-Bit Bidirectional Current Measurement(DS2740)1 8 VOVD DD 1.56V LSB and ±51.2mV Dynam ..
DS2740BU+ ,High-Precision Coulomb Counterapplications. Current is measured bidirectionally over a dynamic range of 15 bits (DS2740U) or 13 b ..
DS2740U ,High-Precision Coulomb CounterApplications Current Accumulation RegisterResolution 6.25Vhr (Both DS2740 andDS2740B) 0.3125mAh ..
DS2745 ,Low-Cost I²C Battery Monitorapplications. The DS2745 can be mounted on either the host side or 70A typical, 100A max pack sid ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS2740B-DS2740BU-DS2740U
High-Precision Coulomb Counter
FEATURES15-Bit Bidirectional Current Measurement
(DS2740)1.56�V LSB and ±51.2mV Dynamic
Range78�A LSB and ±2.56A Dynamic
Range with External 20m� SenseResistor (RSNS)156�A LSB and ±5.12A Dynamic
Range with External 10m� Sense
Resistor (RSNS)13-Bit Bidirectional Current Measurement
(DS2740B)6.25�V LSB and ±51.2mV Dynamic
Range312�A LSB and ±2.56A Dynamic
Range with External 20m� Sense
Resistor (RSNS)625�A LSB and ±5.12A Dynamic
Range with External 10m� Sense
Resistor (RSNS)Analog Input Filter (IS1, IS2) Extends
Dynamic Range for Pulse-Load
ApplicationsCurrent Accumulation Register
Resolution6.25�Vhr (Both DS2740 and
DS2740B)0.3125mAhr with External 20m�
RSNS0.6250mAhr with External 10m�
RSNSDallas 1-Wire® InterfaceUnique 64-Bit Device AddressStandard and Overdrive Timings
(OVD)Low Power Consumption:Active Current: 65�A maxSleep Current: 1�A max
PIN CONFIGURATION
PIN DESCRIPTIONOVD- 1-Wire Bus Speed Select
PIO- Programmable I/O Pin
SNS-Sense Resistor Input
IS2-Current-Sense Input
IS1-Current-Sense InputVSS-Device Ground, Current-Sense Resistor
Return-Data Input/Output
VDD-Power-Supply Input (2.7V to 5.5V)
DS2740
High-Precision Coulomb CounterPIOIS2
SNS
See Table 1 for Ordering Information.
See Table 2 for Detailed Pin Descriptions.
DS2740
Table 1. ORDERING INFORMATION
DESCRIPTIONThe DS2740 provides high-precision current-flow measurement data to support battery-capacity
monitoring in cost-sensitive applications. Current is measured bidirectionally over a dynamic range of 15
bits (DS2740U) or 13 bits (DS2740UB), with the net flow accumulated in a separate 16-bit register.
Through its 1-Wire interface, the DS2740 allows the host system read/write access to status and current
measurement registers. Each device has a unique factory-programmed 64-bit net address that allows it tobe individually addressed by the host system, supporting multibattery slot operation. The interface can be
operated with standard or overdrive timing.
Although the DS2740 is primarily intended for location on the host system, it is also suited for mounting
in the battery pack. The DS2740 and FuelPack™ algorithms, along with host measurements oftemperature and voltage, form a complete and accurate solution for estimating remaining capacity.
Figure 1. BLOCK DIAGRAMVDD
DS2740
Table 2. DETAILED PIN DESCRIPTION
Figure 2. APPLICATION EXAMPLEBattery Pack Return
150 SNS
104System
* 5.6V zener recommended for ESD protection when DATA or PIO
contacts exposed, such as a removable battery pack application
DS2740
POWER MODESThe DS2740 has two power modes: active and sleep. While in active mode, the DS2740 operates as a
high-precision coulomb counter with current and accumulated current measurement blocks operating
continuously and the resulting values updated in the measurement registers. Read and write access is
allowed to all registers. PIO pin is active. In sleep mode, the DS2740 operates in a low-power mode with
no current measurement activity. Serial access to current, accumulated current, and status/controlregisters is allowed if VDD > 2V.
The DS2740 operating mode transitions from SLEEP to ACTIVE when:DQ > VIH, and VDD > UV threshold, orVDD rises from below UV threshold to above UV threshold.The DS2740 operating mode transitions from ACTIVE to SLEEP when:
1) VDD falls to UV threshold, or
2) SMOD = 1 and DQ < VIL for 2s.
CURRENT MEASUREMENTIn the active mode of operation, the DS2740 continually measures the current flow into and out of the
battery by measuring the voltage drop across a low-value current-sense resistor, RSNS. To extend the input
range for pulse-type load currents, the voltage signal can be filtered by adding a capacitor between the
IS1 and IS2 pins. The external capacitor and two internal resistors form a lowpass filter at the input of the
ADC. The voltage-sense range at IS1 and IS2 is ±51.2mV. The input converts peak signal amplitudes upto 75mV as long as the continuous or average signal level (post filter) does not exceed ±51.2mV over the
conversion cycle period. The ADC samples the input differentially at IS1 and IS2 with an 18.6kHz
sample clock and updates the current register at the completion of each conversion cycle. Conversion
times for each resolution option are listed in the tables below. Two resolution options are available.
Figure 3 describes the current measurement register format and resolution for each option. “S” indicatesthe sign bit(s).
Figure 3. CURRENT REGISTER FORMATS
DS2740: 15-bit + sign resolution, 3.5s conversion period.MSB—Address 0ELSB—Address 0F
MSbLSbMSbLSb
Units:1.5625�V/Rsns
DS2740B: 13-bit + sign resolution, 0.875s conversion period.MSB—Address 0ELSB—Address 0F
MSbLSbMSbLSb
Units:6.250�V/Rsns
DS2740
Every 1024th conversion, the ADC measures its input offset to facilitate offset correction. Offset
correction occurs approximately once per hour in the DS2740 and four times per hour in the DS2740B.The resulting correction factor is applied to the subsequent 1023 measurements. During the offset
correction conversion, the ADC does not measure the IS1 to IS2 signal. A maximum error of 1/1024 in
the accumulated current register (ACR) is possible, however, to reduce the error, the current measurement
just prior to the offset conversion is displayed in the current register and is substituted for the dropped
current measurement in the current accumulation process. The typical error due to offset correction ismuch less than 1/1024.
CURRENT ACCUMULATORCurrent measurements are internally summed, or accumulated, at the completion of each conversion
period with the results displayed in the ACR. The accuracy of the ACR is dependent on both the current
measurement and the conversion timebase. The ACR has a range of ±204.8mVh with an LSb of
6.25µVh��Additional registers hold fractional results of each accumulation, however, these bits are not
user accessible.
Read and write access is allowed to the ACR. Whenever the ACR is written, fractional accumulation
results are cleared. Also, a write forces the ADC to measure its offset and update the offset correction
factor. The current measurement and accumulation begin with the second conversion following a write to
the ACR. Figure 4 describes the ACR address, format, and resolution.
Figure 4. CURRENT ACCUMULATOR FORMATMSB—Address 10LSB—Address 11
MSbLSbMSbLSb
Units:6.25�Vh/Rsns
DS2740
MEMORYThe DS2740 has memory space with registers for instrumentation, status, and control. When the MSB of
a two-byte register is read, both the MSB and LSB are latched and held for the duration of the read data
command to prevent updates during the read and ensure synchronization between the two register bytes.
For consistent results, always read the MSB and the LSB of a two-byte register during the same read datacommand sequence.
Table 3. MEMORY MAP
STATUS REGISTERThe format of the status register is shown in Figure 5. The function of each bit is described in detail in the
following paragraphs.
Figure 5. STATUS REGISTER FORMATADDRESS 01
BIT 7BIT 6BIT 5BIT 4BIT 3BIT 2BIT 1BIT 0
SMOD—SLEEP Mode Enable. A value of 1 allows the DS2740 to enter sleep mode when DQ is low for2s. A value of 0 disables DQ related transitions to sleep mode. The power-up default of SMOD = 0.
RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the read net address
command to 33h, while a 1 sets the opcode to 39h. The power-up default of RNAOP = 0.
X—Reserved bits.
DS2740
SPECIAL FEATURE REGISTERThe format of the special feature register is shown in Figure 6. The function of each bit is described in
detail in the following paragraphs.
Figure 6. SPECIAL FEATURE REGISTER FORMATADDRESS 08BIT 7 BIT 6 BIT 5BIT 4BIT 3BIT 2BIT 1 BIT 0
PIO—PIO Pin Sense and Control. This bit is read and write enabled. Writing a 0 to the PIO bit enablesthe PIO open-drain output driver, forcing the PIO pin low. Writing a 1 to the PIO bit disables the output
driver, allowing the PIO pin to be pulled high or used as an input. Reading the PIO bit returns the logic
level forced on the PIO pin. Note that if PIO is left floating, the weak pulldown brings the pin low.
X—Reserved Bits.
1-WIRE BUS SYSTEMThe 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a
1-Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the
DS2740 is a slave device. The bus master is typically a microprocessor in the host system. The discussion
of this bus system consists of four topics: 64-bit net address, hardware configuration, transactionsequence, and 1-Wire signaling.
64-BIT NET ADDRESSEach DS2740 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first
eight bits are the 1-Wire family code (36h for DS2740). The next 48 bits are a unique serial number. The
last eight bits are a cyclic redundancy check (CRC) of the first 56 bits (see Figure 7). The 64-bit net
address and the 1-Wire I/O circuitry built into the device enable the DS2740 to communicate through the1-Wire protocol detailed in the 1-Wire Bus System section of this data sheet.
Figure 7. 1-WIRE NET ADDRESS FORMATMSbLSb
CRC GENERATIONThe DS2740 has an 8-bit CRC stored in the most significant byte of its 1-Wire net address. To ensure
error-free transmission of the address, the host system can compute a CRC value from the first 56 bits of
the address and compare it to the CRC from the DS2740. The host system is responsible for verifying the
CRC value and taking action as a result. The DS2740 does not compare CRC values and does not prevent
a command sequence from proceeding as a result of a CRC mismatch. Proper use of the CRC can resultin a communication channel with a very high level of integrity.
DS2740
CRC is available in Application Note 27, Understanding and Using Cyclic Redundancy Checks with
Dallas Semiconductor Touch Memory Products. (This application note can be found on the Maxim/Dallas
Semiconductor website at .)
In the circuit in Figure 8, the shift register bits are initialized to 0. Then, starting with the least significant
bit of the family code, one bit at a time is shifted in. After the 8th bit of the family code has been entered,
then the serial number is entered. After the 48th bit of the serial number has been entered, the shift
register contains the CRC value.
Figure 8. 1-WIRE CRC GENERATION BLOCK DIAGRAM
HARDWARE CONFIGURATIONBecause the 1-Wire bus has only a single line, it is important that each device on the bus be able to drive
it at the appropriate time. To facilitate this, each device attached to the 1-Wire bus must connect to the
bus with open-drain or tri-state output drivers. The DS2740 uses an open-drain output driver as part of the
bidirectional interface circuitry shown in Figure 9. If a bidirectional pin is not available on the bus master,
separate output and input pins can be connected together.
The 1-Wire bus must have a pullup resistor at the bus-master end of the bus. For short line lengths, the
value of this resistor should be approximately 5k�. The idle state for the 1-Wire bus is high. If, for any
reason, a bus transaction must be suspended, the bus must be left in the idle state to properly resume thetransaction later. If the bus is left low for more than 120�s (16�s for overdrive speed), slave devices on
the bus begin to interpret the low period as a reset pulse, effectively terminating the transaction.
The DS2740 can operate in two communication speed modes, standard and overdrive. The speed mode is
determined by the input logic level of the OVD pin with a logic 0 selecting standard speed and a logic 1selecting overdrive speed. The OVD pin must be at a stable logic level of 0 or 1 before initializing a
transaction with a reset pulse. All 1-Wire devices on a multinode bus must operate at the same
communication speed for proper operation. 1-Wire timing for both standard and overdrive speeds are
listed in the Electrical Characteristics: 1-Wire Interface tables.
