DS2726G+ ,5-Cell to 10-Cell Li+ Protector with Cell BalancingELECTRICAL CHARACTERISTICS(T = -20°C to +85°C.)APARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITSI Prot ..
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DS2726G+
5-Cell to 10-Cell Li+ Protector with Cell Balancing
General DescriptionThe DS2726 provides full charge and discharge protection
for 5- to 10-cell lithium-ion (Li+) battery packs. The protec-
tion circuit monitors individual cell voltages to detect over-
voltage and undervoltage conditions. Protection against
discharge overcurrent and short-circuit current is provided
with user-selectable thresholds using external resistors.
P-channel protection FETs are employed high side and
driven from on-chip 10V FET drivers. Cell balancing can
be enabled to ensure that all cells are equally charged.
ApplicationsPower Tools
Electric Bikes
Home Appliances
FeaturesComplete Protection for 5-Cell to 10-Cell Li+ PacksPin Programmable for 5 to 10 CellsInternal Cell-Balancing Circuit, Shunts Up to 300mAPin-Programmable VOVThresholdPin-Programmable Cell-Balance VoltageOverdischarge Current and Short-Circuit Current
Set with External ResistorsOverdischarge Current and Short-Circuit Current
Timeout Delay Set with External CapacitorsLow Power Consumption: 60µA (typ)Low Shutdown Power Consumption: 5µA (typ)7mm x 7mm, 32-Pin TQFN Lead-Free Package
DS2726
5-Cell to 10-Cell Li+ Protector with
Cell Balancing
Ordering InformationDS2726
VCC
SEL0
SEL1
OVS0
OVS1
CBS0
CBS1
CBCFG
SLEEP
RSC
RDOC
SLEEP
PKP-
CSCD
VCC
PKP+
V10
GND
PKP
CDOCD
VINSNS
V09
V08
V07
V06
V05
V04
V03
V02
V01
V00
VINDC
Simplified Typical Application
Circuit19-5482; Rev 3; 8/10
+Denotes a lead(Pb)-free/RoHS-compliant package.
T&R = Tape and reel.
*EP = Exposed pad.
Pin Configuration appears at end of data sheet.
PARTTEMP RANGEPIN-PACKAGE DS2726G+ -20°C to +85°C 32 TQFN-EP*
DS2726G+T&R -20°C to +85°C 32 TQFN-EP*
DS2726
5-Cell to 10-Cell Li+ Protector with
Cell Balancing
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS(TA= -20°C to +85°C.)
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
Voltage Range on V00–V10, PKP,
RDOC, RSC Pins Relative to GND.....................-0.3V to +60V
Voltage Range on DC Pin Relative to VIN..............-12V to +0.3V
Voltage Range on CC Pin Relative to PKP.............-12V to +0.3V
Voltage Range on CSCD, SEL0, SEL1,
OVS0, OVS1, CBS0, CBS1, SLEEP,
CBCFG, VCCPins Relative to GND...................-0.3V to +6.0V
Human Body Model (HBM) ESD Limit of
V05–V09, PKP, CC, DC..................................................±500V
All Other Pins...................................................................±2kV
Voltage Range on Any Vxto Vx-1(V10 to V09).......-0.3V to +12V
Continuous Power Dissipation (TA= +70°C)
TQFN (derate 37mW/°C above +70°C).....................2963mW
Junction Temperature......................................................+150°C
Operating Temperature Range...........................-20°C to +85°C
Storage Temperature Range.............................-55°C to +125°C
Lead Temperature (soldering, 10s).................................+300°C
Soldering Temperature (reflow).......................................+260°C
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSSupply Range VIN (Notes 1, 2, 3, 4) 5 50 V
Input Range: SEL0, SEL1, OVS0,
OVS1, CBS0, CBS1, CSCD,
CDOCD, SLEEP, CBCFG
(Note 1) -0.3 VCC +
0.3 V
DC ELECTRICAL CHARACTERISTICS(TA= -20°C to +85°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSIDD Protector mode, no fault (Notes 4, 9) 70 90
IDD_BAL Load balancing (Note 11) 400 Supply Current
ISLEEP Sleep mode 5.0 7.5
μA
V00–V10 Leakage Current All cell voltages = 4.2V (Note 10) -2 +2 μA
Input Logic-High: SEL0, SEL1,
OVS0, OVS1, CBS0, CBS1,
SLEEP
VIH ILOAD = 2μA (Notes 1, 5) VCC -
0.4 V
Input Logic-Mid: SEL0, SEL1,
OVS0, OVS1, CBS0, CBS1,
SLEEP
VIM ILOAD = 0 (Notes 1, 5) 1.30 1.65 2.00 V
Input Logic-Low: SEL0, SEL1,
OVS0, OVS1, CBS0, CBS1,
SLEEP
VIL ILOAD = -2μA (Notes 1, 5) VGND +
0.4 V
VCC Output Voltage ILOAD = 1mA (Notes 1, 5, 8) 4.75 5.00 5.25 V
VCC Dropout Voltage (Note 6) 5.5 V
Output Low: CC VOLCC IOL = -100μA, VPKP 13V (Notes 3, 5) VPKP - 12 VPKP - 8 V
CC = VOLCC + 2V -3 -1 Output Low: CC Driver Current mA
DS2726
5-Cell to 10-Cell Li+ Protector with
Cell Balancing
DC ELECTRICAL CHARACTERISTICS (continued)(TA= -20°C to +85°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOutput High: CC VOHCC IOH = 100μA VPKP -
0.5
VPKP +
0.3 V
CC = VOLCC + 2V 7 15 Output High: CC Driver Current CC = VOHCC - 1V 0.5 1.5 mA
Output Low: DC VOLDC IOL = -100μA, VIN 13V (Notes 3, 5) VIN -
VIN - V
DC = VOLDC + 2V -3 -1 Output Low: DC Driver Current DC = VOHDC - 1V -15 -7 mA
Output High: DC VOHDC IOH = 100μA VIN -
0.5
VIN +
0.3 V
DC = VOLDC + 2V 7 15 Output High: DC Driver Current DC = VOHDC - 1V 0.5 1.5 mA
Maximum Balancing Current IBAL 300 mA
Balance FET: On-Resistance IBAL = 180mA 1.7 3.2 7.0
ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUIT(TA= 0°C to +50°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOVS1 = GND, OVS0 = GND 4.05 4.10 4.15
OVS1 = GND, OVS0 = N.C. 4.10 4.15 4.20
OVS1 = GND, OVS0 = VCC 4.15 4.20 4.25
OVS1 = N.C., OVS0 = GND 4.20 4.25 4.30
OVS1 = N.C., OVS0 = N.C. 4.25 4.30 4.35
OVS1 = N.C., OVS0 = VCC 4.30 4.35 4.40
OVS1 = VCC, OVS0 = GND 4.35 4.40 4.45
OVS1 = VCC, OVS0 = N.C. 4.40 4.45 4.50
Overvoltage Detect VOV
OVS1 = VCC, OVS0 = VCC 4.45 4.50 4.55
Charge-Enable Voltage VCEVOVMIN -
0.15
VOVMAX -
0.15 V
Charge-Balance Voltage VBALVBAL lowest typical set point limited to
3.75V
VOVMIN -
Cell-
Balancing
Threshold
VOVMAX -
Cell-
Balancing
Threshold
Undervoltage Release VUVREL 2.7 2.8 2.9 V
Undervoltage Detect VUV 2.2 2.3 2.4 V
RDOC, RSC Output Current VIN - VRDOC = VIN - VRSC = 2V 0.95 1.00 1.05 μA
RDOC, RSC Input Offset Voltage -3 +3 mV
DS2726
5-Cell to 10-Cell Li+ Protector with
Cell Balancing
Note 1:All voltages relative to GND.
Note 2:Voltages below this level cannot be monitored; therefore, CC and DC are off below this value.
Note 3:Full-gate drive is not achieved until the voltage source for the gate driver (VPKPor VVIN) is above 13V.
Note 4:With 10µF decoupling capacitor.
Note 5:ILOADis the current load on the pin specified in the parameter.
Note 6:VCCcannot meet specification if VVINis below this value.
Note 7:Capacitance tolerance introduces additional error.
Note 8:With ≥0.1µF decoupling capacitor.
Note 9:Current is an average. Spikes up to 200µA when measuring cell voltages.
Note 10:Current is an average. Spikes up to 15µA when measuring cell voltages.
Note 11:Current depends on the number of cells being balanced.
Note 12:Includes switching time and comparator delay with 25mV overdrive.
ELECTRICAL CHARACTERISTICS: PROTECTION CIRCUIT (continued)(TA= 0°C to +50°C.)
PARAMETERSYMBOLCONDITIONSMINTYPMAXUNITSOvervoltage Delay tOVD128 x
tDOCDMIN
128 x
tDOCDMAXms
Undervoltage Delay tUVD128 x
tDOCDMIN
128 x
tDOCDMAXms
CDOCD = 100pF (Notes 7, 12) 2.56 3.20 3.84 Discharge Overcurrent Delay tDOCDCDOCD = 1000pF (Notes 7, 12) 25.6 32.0 38.4 ms
CSCD = 100pF (Notes 7, 12) 45 58 72 Short-Circuit Delay tSCDCSCD = 1000pF (Notes 7, 12) 405 508 612 μs
Charger-Detect Threshold
(VPKP - VVIN)VCDET 3 17 mV
Test Threshold VTP DOC conditions 0.8 1.2 1.7 V
DOC condition, VIN - VPKP = 2V 68 120 200 μA Test Current ITSTDOC condition, VIN - VPKP = 50V 0.5 1.20 1.8 mA
DS2726
5-Cell to 10-Cell Li+ Protector with
Cell Balancing
Typical Operating Characteristics(TA = +25°C, unless otherwise noted.)
OV ACCURACY vs. TEMPERATUREDS2726 toc01
TEMPERATURE (°C)
OV ACCURACY (V)3510-15
UV ACCURACY vs. TEMPERATURE
DS2726 toc02
TEMPERATURE (°C)
UV ACCURACY (V)35-1510
TEST CURRENT vs. (VVIN - VPKP)
DS2726 toc03
(VVIN - VPKP) (V)
ITST
(mA)40302010
VTP = 1.16V
DISCHARGE OVERCURRENT DELAY
(CDOCD = 1000pF, RDOC = 110kΩ
WITH RDS_ON = 2.75kΩ)TIME (ms)
VGS DISCHARGE FET (V)
LOAD CURRENT (A)302010
DS2726 toc04
DOC CONDITION
VGS DISCHARGE FET
DISCHARGE OVERCURRENT
THRESHOLD
LOAD CURRENT
SHORT-CIRCUIT DELAY
(CDOCD = 1000pF, RSC = 247.5kΩ
WITH RDS_ON = 2.75MΩ)TIME (μs)
VGS DISCHARGE FET (V)
LOAD CURRENT (A)
DS2726 toc05
LOAD CURRENT
SHORT-CIRCUIT CONDITION
SHORT-CIRCUIT
THRESHOLD
VGS DISCHARGE FET
FET TURN-OFF TIME
(WITH 460nC TOTAL GATE CHARGE)DS2726 toc06
5V/div
200
DS2726
5-Cell to 10-Cell Li+ Protector with
Cell BalancingVOV, VBAL,
VCE, VUV
V10
VIN
VIN
DS2726
SNS
10V10V
V09
VOV, VBAL,
VCE, VUV
V08
VOV, VBAL,
VCE, VUV
V07
VOV, VBAL,
VCE, VUV
V06
VOV, VBAL,
VCE, VUV
V05
VOV, VBAL,
VCE, VUV
V04
VOV, VBAL,
VCE, VUV
V03RSC
CSCD
SNS
RDOC
CDOCD
VOV, VBAL,
VCE, VUV
V02
VOV, VBAL,
VCE, VUV
V01
VOV, VBAL,
VCE, VUV
V00
VCCVCC
PKP
PKP+
RTST
LOGIC
VIN
SEL0
SEL1
OVS0
OVS1
CBS0
CBS1
CBCFG
SLEEP
PKP-
GND
VREG
tSCD
tDOCD
VCDET
DS2726
5-Cell to 10-Cell Li+ Protector with
Cell Balancing
Pin Description
PINNAMEFUNCTION1 RSC Short-Circuit Voltage Threshold. The resistor from this pin to the positive terminal of the cell stack
selects the threshold voltage for a short-circuit condition in the discharge direction.
2 RDOC Discharge Overcurrent Voltage Threshold. The resistor from this pin to the positive terminal of the cell
stack selects the threshold voltage for an overcurrent condition in the discharge direction.
3 VCCRegulator Supply Output. VCC supplies power to internal circuits and can be used to pull configuration
pins to VIH. It should be bypassed to GND with at least a 0.1μF ceramic capacitor.
4, 5 SEL0,
SEL1
Select Number of Cells in the Battery Stack. This input is a three-level input. Connect to ground or VCC
for a logic-low or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table
2 for how to drive this pin for a particular number of cells.
6 CDOCD Discharge Overcurrent Delay Time. Connect a capacitor from this pin to GND to select the amount of
time for which a discharge overcurrent condition must persist before shutting off the DC FET.
7 SLEEP
Sleep-Mode Select Input. Driving this pin to a logic-low level forces the part into the lowest power state.
The part exits Sleep Mode once a charge voltage is applied. When CBCFG is high, a logic-high on this
pin enables cell balancing.
8 CSCD Short-Circuit Current Delay Time. Connect a capacitor from this pin to GND to select the amount of time
for which a short-circuit current condition must persist before shutting off the DC FET.
9 CBCFG
Charge-Balance Configuration Input. When this pin is at a logic-low, charge balancing is enabled if
VPKP > VVIN + VCDET. When this pin is at a logic-high, charge balancing is enabled if the SLEEP pin is
at a logic-high.
10, 11 CBS0,
CBS1
Select Cell-Balancing Voltage. This input is a three-level input. Connect to ground or VCC for a logic-low
or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 4 for how to
drive this pin for a particular cell-balancing voltage threshold.
12, 13 OVS0,
OVS1
Select Overvoltage Threshold. This input is a three-level input. Connect to ground or VCC for a logic-low
or logic-high, respectively. Leave unconnected to achieve the midthreshold. See Table 3 for how to
drive this pin for a particular overvoltage threshold.
14, 30 N.C. No Connection. Not internally connected.
15 GND Ground. Connect to the negative terminal of the lowest voltage cell.
16 V00 Negative Terminal Voltage Sense. Connect to the negative terminal of the 1st cell in the battery stack.
17 V01 Cell 01 Voltage Sense. Connect to the positive terminal of the 1st cell in the battery stack.
18 V02 Cell 02 Voltage Sense. Connect to the positive terminal of the 2nd cell in the battery stack.
19 V03 Cell 03 Voltage Sense. Connect to the positive terminal of the 3rd cell inf the battery stack.
20 V04 Cell 04 Voltage Sense. Connect to the positive terminal of the 4th cell in the battery stack.
21 V05 Cell 05 Voltage Sense. Connect to the positive terminal of the 5th cell in the battery stack.
22 V06 Cell 06 Voltage Sense. Connect to the positive terminal of the 6th cell in the battery stack.
23 V07 Cell 07 Voltage Sense. Connect to the positive terminal of the 7th cell in the battery stack.
24 V08 Cell 08 Voltage Sense. Connect to the positive terminal of the 8th cell in the battery stack.
25 V09 Cell 09 Voltage Sense. Connect to the positive terminal of the 9th cell in the battery stack.
26 V10 Cell 10 Voltage Sense. Connect to the positive terminal of the 10th cell in the battery stack.
27 VIN Connect to the Most Positive Cell Terminal
28 DC Discharge Control Output. DC controls the gate of the discharge FET. Driven from VIN to VOLDC to turn
on and turn off the discharge FET.
DS2726
5-Cell to 10-Cell Li+ Protector with
Cell Balancing
Pin Description (continued)
PINNAMEFUNCTION29 SNS Sense Input. Connect to the drains of the charge and discharge FETs. Used as a voltage reference for
detecting short-circuit and discharge overcurrent conditions.
31 CC Charge Control Output. CC controls the gate of the charge FET. Driven from PKP to VOLCC to turn on and
turn off the charge FET.
32 PKP Pack Positive. The voltage on PKP is used to detect charger-attach and protection-release conditions. EP Exposed Pad. Connect to the negative terminal of the lowest voltage potential cell.
RSC
RDOC
SEL0
VCC
V08
V07
V06
V05
V04
V03
V02
V01
CBCFGV00GNDN.C.OVS1OVS0CBS1CBS0
PKP
N.C.SNSV
V10V09
150Ω
150Ω
150Ω15Ω
VIN
205kΩ
SEL1
CDOCD
CSCD
SLEEP
82.5kΩ
150Ω
60V
1μF
0.1μF
1μF
1μF
10μF
1μF
V10
1kΩ1kΩ1kΩ1kΩ1kΩ1kΩ
VCC
150Ω
0.1μF
10kΩ1kΩ
6.2V
150kΩ
SLEEP
PKP-
PKP+
DS2726
V09
V08
V07
V06
V05
V04
V03
V02
V01
V00
Figure 2. Typical Application Circuit