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DS2720
Efficient, Addressable Single-Cell Rechargeable Lithium Protection IC
FEATURESRechargeable Lithium-Ion (Li+) SafetyCircuitOvervoltage ProtectionOvercurrent/Short-Circuit ProtectionUndervoltage ProtectionOvertemperature ProtectionControls High-Side N-Channel Power
MOSFETs Driven from 9V Charge PumpSystem Power Management and Control
Feature SupportEight Bytes of Lockable EEPROMDallas 1-Wire® Interface with Unique 64-Bit
Device Address8-Pin ��SOP PackageLow Power Consumption:Active Current: 12.5�A typSleep Current:1.5�A typ
PIN CONFIGURATION
PIN DESCRIPTIONPLS-Battery-Pack Positive Terminal Input-Power-Switch Sense Input-Data Input/OutputVSS-Device Ground
VDD-Power-Supply Input-Reservoir Capacitor-Charge Control Output-Discharge Control Output
DESCRIPTIONThe DS2720 single-cell rechargeable Li+ protection IC provides electronic safety functions required for
rechargeable Li+ applications including protecting the battery during charge, protection of the circuit
from damage during periods of excess current flow and maximization of battery life by limiting the level
of cell depletion. Protection is facilitated by electronically disconnecting the charge and discharge
conduction path with switching devices such as low-cost N-channel power MOSFETs.
Since the DS2720 provides high-side drive to external N-channel protection MOSFETs from a 9V charge
pump, superior on-resistance performance results compared to common low-side protector circuits using
the same FETs. The FET on-resistance actually decreases as the battery discharges.
Adding to the uniqueness of the DS2720 is the ability of the system to control the FETs from either the
data interface or a dedicated input thereby eliminating the power-switch control redundancy of
rechargeable Li+ battery systems.
Through its 1-Wire interface, the DS2720 gives the host system read/write access to status and controlregisters, instrumentation registers, and general-purpose data storage. Each device has a factory-
programmed 64-bit net address that allows it to be individually addressed by the host system.
DS2720U
�SOPPLS
VSSVDD
DS2720
Efficient, Addressable Single-Cell
Rechargeable Lithium Protection IC
DS2720
Two types of user-memory are provided on the DS2720 for battery information storage: EEPROM and
lockable EEPROM. EEPROM memory saves important battery data in true nonvolatile (NV) memory
that is unaffected by severe battery depletion, accidental shorts, or ESD events. Lockable EEPROM
becomes ROM when locked to provide additional security for unchanging battery data.
ORDERING INFORMATION
DS2720
Figure 1. BLOCK DIAGRAM1) Normally open, closed to enable test current, ITST
2) Normally open, closed to enable test current, ITST, and recovery charge
(See Rechargeable Li+ Protection Circuitry section for more information.)
(1)
DS2720
Table 1. DETAILED PIN DESCRIPTION
Figure 2. APPLICATION EXAMPLE
DS2720
POWER MODESThe DS2720 has two power modes: active and sleep. While in active mode, the DS2720 continuouslyperforms safety monitoring. In sleep mode, the DS2720 ceases monitoring activities and drives both the
charge and discharge protection FETs to an “off state”. Upon returning to the active mode from the sleep
mode, DS2720 resumes safety monitoring and conditionally turns on the protection FETs.
Table 2. POWER MODE TRANSITION CONDITIONS(1) DS2720 does not transition to Active Mode if VDD < VSC.
RECHARGEABLE Li+ PROTECTION CIRCUITRYDuring active mode, the DS2720 constantly monitors cell voltage and voltage drop across the FETs to
protect the battery from overcharge (overvoltage), overdischarge (undervoltage), and excessive discharge
currents (overcurrent, short circuit). Conditions and DS2720 responses are described in the sectionsbelow and summarized in Table 3 and Figure 3.
Table 3. PROTECTION CONDITIONS AND DS2720 RESPONSESAll voltages are with respect to VSS.(1) During transition from sleep to active, tOVD = 0.
(2) Recovery charge current is limited by RTST and forward voltage of blocking diode, which prevents discharging throughRTST when recovery charge enabled.
(3) With test current ITST flowing from VDD to PLS (pullup on PLS).
DS2720
Overvoltage. If the cell voltage sensed at VDD exceeds overvoltage threshold VOV for a period longer
than overvoltage delay tOVD, the DS2720 shuts off the external charge FET and sets the OV flag in the
protection register. Discharging remains enabled during overvoltage. The charge FET is re-enabled
(unless another protection condition prevents it), when the cell voltage falls below charge enablethreshold VCE, or a discharge causes VDD - VPLS > VOC.
Undervoltage. If the cell voltage sensed at VDD drops below undervoltage threshold VUV for a period
longer than undervoltage delay tUVD, the DS2720 shuts off the charge and discharge FETs, sets the UV
flag in the protection register, and enters sleep mode. The DS2720 turns on both the charge and dischargeFETs after the cell voltage rises above VUV and a charger is present.
Short Circuit. If the cell voltage sensed at VDD drops below depletion threshold VSC for a period of tSCD,the DS2720 shuts off the charge and discharge FETs and sets the DOC flag in the protection register. The
current path through the charge and discharge FETs is not re-established until the voltage on PLS risesabove VDD - VOC. The DS2720 provides a test current through internal resistor RTST from VDD to PLS to
pull up PLS when VDD rises above VSC. The test current allows the DS2720 to detect the removal of the
offending low-impedance load. Additionally, a recovery charge path through RTST from PLS to VDD is
enabled.
Overcurrent. If the voltage across the protection FETs (VDD - VPLS) is greater than VOC for a period
longer than tOCD, the DS2720 shuts off the external charge and discharge FETs and sets the DOC flag in
the protection register. The current path is not re-established until the voltage on PLS rises above VDD -
VOC. The DS2720 provides a test current through internal resistor RTST from VDD to PLS to detect the
removal of the offending low-impedance load.
Overtemperature. If the device temperature exceeds TMAX, the DS2720 immediately shuts off the
external discharge and charge FETs. The FETs are not turned back on until the cell temperature drops
below TMAX AND the host resets the OT bit.
DS2720
Figure 3. Li+ PROTECTION CIRCUITRY EXAMPLE WAVEFORMSNotes:
IOC = Current that produces a voltage drop across FETs equal to VOC threshold.ISC = Current drawn from the battery during short-circuit event. (Collapses the cell terminal voltage to VSC.)
Above example assumes FET on-resistance values such that the overcurrent threshold, VOC, is reached before theshort-circuit threshold, VSC.
POWERMODE
VOV
VCE
VUV
VDD
VPLS - VDD
-VOC 0
VOHCP
VOHCP
ACTIVE
VOLCC
VOLDC
SLEEP
OVER-CURRENT OR
SHORT TEST
ACTIVE
INACTIVE
VSC
ICELL
CHARGE
DISCHARGE-ISC -IOC 0
VCH
ENABLED
DISABLED
RECOVERYCHARGE
SHORT-CIRCUIT
EVENT
UNDERVOLTAGE
EVENT
OVERVOLTAGE
EVENT
OVERCURRENT
EVENT
UNDERVOLTAGE
EVENT
SEVERE
DEPLETION
DS2720
MEMORYThe DS27xx family of products is organized into a 256-byte linear address space with registers for
instrumentation, status, and control in the lower 32 bytes, with lockable EEPROM memory occupying
portions of the remaining address space. All EEPROM memory is general purpose except address 31h,
which should be written with the default values for the status register.
EEPROM memory is shadowed by RAM to eliminate programming delays between writes and to allowthe data to be verified by the host system before being copied to EEPROM. All reads and writes to/from
EEPROM memory in fact access the shadow RAM. In unlocked EEPROM blocks, the write data
command updates shadow RAM. In locked EEPROM blocks, the write data command is ignored. The
copy data command copies the contents of shadow RAM to EEPROM in an unlocked block of EEPROM
but has no effect on locked blocks. The recall data command copies the contents of a block of EEPROMto shadow RAM regardless of whether the block is locked or not.
Table 4. MEMORY MAP(1)Each EEPROM block is read/write until locked by the LOCK command, after which it is read-only.
PROTECTION REGISTERThe protection register consists of flags that indicate protection circuit status and switches that give
conditional control over the charging and discharging paths. Bits OV, UV, and DOC are set when
corresponding protection conditions occur and remain set until cleared by the host system. The format ofthe protection register is shown in Figure 4. The function of each bit is described in detail in the following
paragraphs.
Figure 4. PROTECTION REGISTER FORMATAddress 00Bit 7 Bit 6 Bit 5Bit 4Bit 3Bit 2Bit 1 Bit 0
DS2720
OV—Overvoltage Flag. When set to 1, this bit indicates the battery pack has experienced an overvoltagecondition. This bit does not clear itself after the overvoltage state is corrected, and thus must be reset by
the host system. A reset of this bit should be issued after the battery voltage falls below VCE in order todetect future events. The OV bit is a volatile R/W bit, initialized to 0 upon power-on-reset (POR).
UV—Undervoltage Flag. When set to 1, this bit indicates the battery pack has experienced an
undervoltage condition. This bit does not clear itself after the undervoltage state is corrected, and thus
should be reset by the host system in order to detect future events. The UV bit is a volatile R/W bit,initialized to 1 upon POR.
DOC—Overcurrent Flag. When set to 1, this bit indicates the battery pack has experienced an
overcurrent (or short-circuit) condition. This bit does not clear itself after the over/shortcurrent state is
corrected, and thus should be reset by the host system in order to detect future events. The DOC bit is avolatile R/W bit, initialized to 1 upon POR.
CC—CC Pin Mirror. This read-only bit mirrors the state of the CC output pin. The CC bit is a 1 when theCC pin is driven high (VOHCC). The CC bit is a 0 when the CC pin is driven low (VOLCC).
DC—DC Pin Mirror. This read-only bit mirrors the state of the DC output pin. The DC bit is a 1 whenthe DC pin is driven high (VOHDC). The DC bit is a 0 when the DC pin is driven low (VOLDC).
CE—Charge Enable. Writing a 0 to this bit disables charging (CC output low, external charge FET off)regardless of cell or pack conditions. Writing a 1 to this bit enables charging, subject to override by thepresence of any protection conditions. The DS2720 automatically sets this bit to 1 when it transitions
from sleep mode to active mode. The CE bit is a volatile R/W bit, initialized to 1 upon POR.
DE—Discharge Enable. Writing a 0 to this bit disables discharging (DC output low, external dischargeFET off) regardless of cell or pack conditions. Writing a 1 to this bit enables discharging, subject tooverride by the presence of any protection conditions. The DS2720 automatically sets this bit to 1 when it
transitions from sleep mode to active mode. The DE bit is a volatile R/W bit, initialized to 1 upon POR.
STATUS REGISTERThe default values for the status register bits are stored in lockable EEPROM in the corresponding bits of
address 31h. A recall data command for EEPROM block 1 recalls the default values into the status
register bits. The format of the status register is shown in Figure 5. The function of each bit is described
in detail in the following paragraphs.
Figure 5. STATUS REGISTER FORMATAddress 01Bit 7 Bit 6 Bit 5Bit 4Bit 3Bit 2Bit 1 Bit 0
DS2720
BIT 5—This bit is read only. The value of this bit is set by bit 5 of address 31h and is factory set to 0.The value of address 31h bit 5 must not be changed.
RNAOP—Read Net Address Opcode. A value of 0 in this bit sets the opcode for the read net address
command to 33h, while a 1 sets the opcode to 39h. This bit is read-only. The desired default value should
be set in bit 4 of address 31h. The factory default for RNAOP is 0.
BIT 3—This bit is read only. The value of this bit is set by bit 3 of address 31h and is factory set to 0.The value of address 31h bit 3 must not be changed.
X—Reserved Bits.
EEPROM REGISTERThe format of the EEPROM register is shown in Figure 6. The function of each bit is described in detail
in the following paragraphs.
Figure 6. EEPROM REGISTER FORMATAddress 07Bit 7 Bit 6 Bit 5Bit 4Bit 3Bit 2Bit 1 Bit 0
EEC—EEPROM Copy Flag. A 1 in this read-only bit indicates that a copy data command is in progress.While this bit is high, writes to EEPROM addresses are ignored. A 0 in this bit indicates that data can bewritten to unlocked EEPROM blocks if the DS2720 is in the active mode of operation.
LOCK—EEPROM Lock Enable. When this bit is 0, the lock command is ignored. Writing a 1 to this bitenables the lock command. After the lock command is executed, the LOCK bit is reset to 0. The LOCK
bit is a volatile R/W bit, initialized to 0 upon POR.
BL1—EEPROM Block 1 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 1 (addresses30 to 33h) is locked (read-only) while a 0 indicates block 1 is unlocked (read/write).
BL0—EEPROM Block 0 Lock Flag. A 1 in this read-only bit indicates that EEPROM block 0 (addresses20 to 23h) is locked (read-only) while a 0 indicates block 0 is unlocked (read/write).
X—Reserved Bits.
DS2720
SPECIAL FEATURE REGISTERThe format of the special feature register is shown in Figure 7. The function of each bit is described in
detail in the following paragraphs.
Figure 7. SPECIAL FEATURE REGISTER FORMATAddress 08Bit 7 Bit 6 Bit 5Bit 4Bit 3Bit 2Bit 1 Bit 0
PSF—PS Flag. This bit is reset to 0 when the DS2720 detects the PS pin is pulled to VSS. This bit does
not set itself to a 1 after the PS pin returns to a high logic level, and thus must be set by the host system
to detect future events. This bit is initialized to a 1 upon POR.
OT—Overtemperature Flag. When set to 1, this bit indicates the battery pack has experienced an
overtemperature condition. This bit does not clear itself after the overtemperature state is corrected, and
thus must be reset by the host system after the temperature decreases below TMAX to re-enable the charge
and discharge FETs. Writing a 1 to this bit disables the FETs, but this is not recommended. The OT bit isa volatile R/W bit, initialized to 0 upon POR.
X—Reserved Bits. INPUT PINThe PS pin is internally pulled to VDD through a high-value resistance. PS is continuously monitored for
a low-impedance connection to VSS. Connecting PS to VSS wakes up the DS2720 if it was in sleep mode.
If the DS2720 was in active mode, PS has no effect.
1-WIRE BUS SYSTEMThe 1-Wire bus is a system that has a single bus master and one or more slaves. A multidrop bus is a 1-
Wire bus with multiple slaves. A single-drop bus has only one slave device. In all instances, the DS2720
is a slave device. The bus master is typically a microprocessor in the host system. The discussion of this
bus system consists of four topics: 64-bit net address, hardware configuration, transaction sequence, and
1-Wire signaling.
64-BIT NET ADDRESSEach DS2720 has a unique, factory-programmed 1-Wire net address that is 64 bits in length. The first
eight bits are the 1-Wire family code (31h for DS2720). The next 48 bits are a unique serial number. The
last eight bits are a CRC of the first 56 bits (see Figure 8). The 64-bit net address and the 1-Wire I/O
circuitry built into the device enable the DS2720 to communicate through the 1-Wire protocol detailed inthe 1-Wire Bus System section of this data sheet.
