DS26528G+ ,Octal T1/E1/J1 TransceiverFEATURES Eight Complete T1, E1, or J1 Long-Haul/Short-The DS26528 is a single-chip 8-port framer ..
DS26528G+ ,Octal T1/E1/J1 TransceiverApplications Routers Crystal-Less Jitter Attenuator can be Selected Channel Service Units (CSUs) ..
DS26528GN ,Octal T1/E1/J1 TransceiverTABLE OF CONTENTS 1. DETAILED DESCRIPTION.......9 1.1 MAJOR OPERATING MODES.9 2. FEATURE HIGHLIGHTS ..
DS26528GN ,Octal T1/E1/J1 TransceiverFeatures Continued in Section 2. DS26528GN+ 256 TE-CSBGA -40°C to +85°C + Denotes lead-free/RoHS c ..
DS26528GN+ ,Octal T1/E1/J1 Transceiverapplications. Each channel is independently Independent T1, E1, or J1 Selections for Each configu ..
DS26528GNA4 ,Octal T1/E1/J1 TransceiverAPPLICATIONS ...13 4. SPECIFICATIONS COMPLIANCE..14 5. ACRONYMS AND GLOSSARY ......16 6.
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26528G+-DS26528GN-DS26528GN+-DS26528GNA4
Octal T1/E1/J1 Transceiver
GENERAL DESCRIPTION The DS26528 is a single-chip 8-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each channel is independently
configurable, supporting both long-haul and short-haul
lines.
APPLICATIONS Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
DS26528
T1/J1/E1
TransceiverT1/E1/J1
NETWORK
BACKPLANE
TDM
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS26528G 0°C to +70°C 256 TE-CSBGA
DS26528G+ 0°C to +70°C 256 TE-CSBGA
DS26528GN -40°C to +85°C 256 TE-CSBGA
DS26528GN+ -40°C to +85°C 256 TE-CSBGA
+ Denotes lead-free/RoHS compliant device.
FEATURES �
Eight Complete T1, E1, or J1 Long-Haul/Short-
Haul Transceivers (LIU plus Framer) �
Independent T1, E1, or J1 Selections for Each
Transceiver �
Internal Software-Selectable Transmit- and
Receive-Side Termination for 100Ω T1 Twisted
Pair, 110Ω J1 Twisted Pair, 120Ω E1 Twisted
Pair, and 75Ω E1 Coaxial Applications �
Crystal-Less Jitter Attenuator can be Selected
for Transmit or Receive Path; Jitter Attenuator
Meets ETS CTR 12/13, ITU-T G.736, G.742,
G.823, and AT&T Pub 62411 �
External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted for
T1 or E1 Usage in the Host Mode �
Receive-Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments �
Transmit Open- and Short-Circuit Detection �
LIU LOS in Accordance with G.775, ETS 300
233, and T1.231 �
Transmit Synchronizer �
Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port �
Alarm Detection and Insertion �
T1 Framing Formats of D4, SLC-96, and ESF �
J1 Support �
E1 G.704 and CRC-4 Multiframe �
T1-to-E1 Conversion
Features Continued in Section 2.
DS26528
Octal T1/E1/J1 Transceiver
DS26528 Octal T1/E1/J1 Transceiver
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................9 1.1 MAJOR OPERATING MODES.............................................................................................................9
2. FEATURE HIGHLIGHTS..................................................................................................10 2.1 GENERAL......................................................................................................................................10
2.2 LINE INTERFACE............................................................................................................................10
2.3 CLOCK SYNTHESIZER....................................................................................................................10
2.4 JITTER ATTENUATOR.....................................................................................................................10
2.5 FRAMER/FORMATTER....................................................................................................................10
2.6 SYSTEM INTERFACE......................................................................................................................11
2.7 HDLC CONTROLLERS...................................................................................................................12
2.8 TEST AND DIAGNOSTICS................................................................................................................12
2.9 CONTROL PORT............................................................................................................................12
3. APPLICATIONS...............................................................................................................13
4. SPECIFICATIONS COMPLIANCE...................................................................................14
5. ACRONYMS AND GLOSSARY.......................................................................................16
6. BLOCK DIAGRAMS.........................................................................................................17
7. PIN DESCRIPTIONS........................................................................................................19 7.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................19
8. FUNCTIONAL DESCRIPTION.........................................................................................27 8.1 PROCESSOR INTERFACE................................................................................................................27
8.2 CLOCK STRUCTURE.......................................................................................................................27
8.2.1 Backplane Clock Generation...............................................................................................................27
8.3 RESETS AND POWER-DOWN MODES..............................................................................................29
8.4 INITIALIZATION AND CONFIGURATION..............................................................................................30
8.4.1 Example Device Initialization Sequence..............................................................................................30
8.5 GLOBAL RESOURCES....................................................................................................................30
8.6 PER-PORT RESOURCES................................................................................................................30
8.7 DEVICE INTERRUPTS.....................................................................................................................30
8.8 SYSTEM BACKPLANE INTERFACE...................................................................................................32
8.8.1 Elastic Stores.......................................................................................................................................32
8.8.2 IBO Multiplexer.....................................................................................................................................35
8.8.3 H.100 (CT Bus) Compatibility..............................................................................................................42
8.8.4 Receive and Transmit Channel Blocking Registers.............................................................................43
8.8.5 Transmit Fractional Support (Gapped Clock Mode)............................................................................43
8.8.6 Receive Fractional Support (Gapped Clock Mode).............................................................................43
8.9 FRAMERS......................................................................................................................................44
8.9.1 T1 Framing...........................................................................................................................................44
8.9.2 E1 Framing...........................................................................................................................................47
8.9.3 T1 Transmit Synchronizer....................................................................................................................49
8.9.4 Signaling..............................................................................................................................................50
8.9.5 T1 Data Link.........................................................................................................................................54
8.9.6 E1 Data Link.........................................................................................................................................56
8.9.7 Maintenance and Alarms.....................................................................................................................57
8.9.8 E1 Automatic Alarm Generation..........................................................................................................60
8.9.9 Error-Count Registers..........................................................................................................................61
DS26528 Octal T1/E1/J1 Transceiver
8.9.12 Receive Per-Channel Idle Code Insertion............................................................................................64
8.9.13 Per-Channel Loopback........................................................................................................................64
8.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)...................................................................64
8.9.15 T1 Programmable In-Band Loop Code Generator...............................................................................65
8.9.16 T1 Programmable In-Band Loop Code Detection................................................................................66
8.9.17 Framer Payload Loopbacks.................................................................................................................67
8.10 HDLC CONTROLLERS................................................................................................................68
8.10.1 Receive HDLC Controller.....................................................................................................................68
8.10.2 Transmit HDLC Controller....................................................................................................................71
8.11 LINE INTERFACE UNITS (LIUS)....................................................................................................73
8.11.1 LIU Operation.......................................................................................................................................76
8.11.2 Transmitter...........................................................................................................................................77
8.11.3 Receiver...............................................................................................................................................80
8.11.4 Jitter Attenuator....................................................................................................................................83
8.11.5 LIU Loopbacks.....................................................................................................................................84
8.12 BIT-ERROR-RATE TEST (BERT) FUNCTION................................................................................86
8.12.1 BERT Repetitive Pattern Set...............................................................................................................87
8.12.2 BERT Error Counter.............................................................................................................................87
9. DEVICE REGISTERS.......................................................................................................88 9.1 REGISTER LISTINGS......................................................................................................................88
9.1.1 Global Register List..............................................................................................................................90
9.1.2 Framer Register List.............................................................................................................................91
9.1.3 LIU and BERT Register List.................................................................................................................98
9.2 REGISTER BIT MAPS......................................................................................................................99
9.2.1 Global Register Bit Map.......................................................................................................................99
9.2.2 Framer Register Bit Map....................................................................................................................100
9.2.3 LIU Register Bit Map..........................................................................................................................108
9.2.4 BERT Register Bit Map......................................................................................................................108
9.3 GLOBAL REGISTER DEFINITIONS..................................................................................................109
9.4 FRAMER REGISTER DEFINITIONS.................................................................................................124
9.4.1 Receive Register Definitions..............................................................................................................124
9.4.2 Transmit Register Definitions.............................................................................................................183
9.5 LIU REGISTER DEFINITIONS.........................................................................................................218
9.6 BERT REGISTER DEFINITIONS.....................................................................................................227
10. FUNCTIONAL TIMING...................................................................................................235 10.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................235
10.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................240
10.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................245
10.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................247
11. OPERATING PARAMETERS.........................................................................................250 11.1 THERMAL CHARACTERISTICS....................................................................................................251
11.2 LINE INTERFACE CHARACTERISTICS..........................................................................................251
12. AC TIMING CHARACTERISTICS..................................................................................252 12.1 MICROPROCESSOR BUS AC CHARACTERISTICS........................................................................252
12.2 JTAG INTERFACE TIMING.........................................................................................................261
12.3 SYSTEM CLOCK AC CHARACTERISTICS....................................................................................262
13. JTAG BOUNDARY SCAN AND TEST ACCESS PORT................................................263 13.1 TAP CONTROLLER STATE MACHINE.........................................................................................264
13.1.1 Test-Logic-Reset................................................................................................................................264
13.1.2 Run-Test-Idle.....................................................................................................................................264
DS26528 Octal T1/E1/J1 Transceiver
13.1.5 Shift-DR..............................................................................................................................................264
13.1.6 Exit1-DR.............................................................................................................................................264
13.1.7 Pause-DR...........................................................................................................................................264
13.1.8 Exit2-DR.............................................................................................................................................264
13.1.9 Update-DR.........................................................................................................................................264
13.1.10 Select-IR-Scan...............................................................................................................................264
13.1.11 Capture-IR......................................................................................................................................265
13.1.12 Shift-IR............................................................................................................................................265
13.1.13 Exit1-IR...........................................................................................................................................265
13.1.14 Pause-IR.........................................................................................................................................265
13.1.15 Exit2-IR...........................................................................................................................................265
13.1.16 Update-IR.......................................................................................................................................265
13.2 INSTRUCTION REGISTER...........................................................................................................267
13.2.1 SAMPLE:PRELOAD..........................................................................................................................267
13.2.2 BYPASS.............................................................................................................................................267
13.2.3 EXTEST.............................................................................................................................................267
13.2.4 CLAMP...............................................................................................................................................267
13.2.5 HIGHZ................................................................................................................................................267
13.2.6 IDCODE.............................................................................................................................................267
13.3 JTAG ID CODES......................................................................................................................268
13.4 TEST REGISTERS.....................................................................................................................268
13.4.1 Boundary Scan Register....................................................................................................................268
13.4.2 Bypass Register.................................................................................................................................268
13.4.3 Identification Register.........................................................................................................................268
14. PIN CONFIGURATION...................................................................................................273
15. PACKAGE INFORMATION............................................................................................274 15.1 256-BALL TE-CSBGA (56-G6028-001)...................................................................................274
16. DOCUMENT REVISION HISTORY................................................................................275
DS26528 Octal T1/E1/J1 Transceiver
LIST OF FIGURES Figure 6-1. Block Diagram.........................................................................................................................................17
Figure 6-2. Detailed Block Diagram...........................................................................................................................18
Figure 8-1. Backplane Clock Generation...................................................................................................................28
Figure 8-2. Device Interrupt Information Flow Diagram.............................................................................................31
Figure 8-3. IBO Multiplexer Equivalent Circuit—4.096MHz......................................................................................36
Figure 8-4. IBO Multiplexer Equivalent Circuit—8.192MHz......................................................................................37
Figure 8-5. IBO Multiplexer Equivalent Circuit—16.384MHz....................................................................................38
Figure 8-6. RSYNC Input in H.100 (CT Bus) Mode...................................................................................................42
Figure 8-7. TSSYNCIO (Input Mode) Input in H.100 (CT Bus) Mode.......................................................................43
Figure 8-8. CRC-4 Recalculate Method....................................................................................................................64
Figure 8-9. Receive HDLC Example..........................................................................................................................70
Figure 8-10. HDLC Message Transmit Example.......................................................................................................72
Figure 8-11. Basic Balanced Network Connections..................................................................................................74
Figure 8-12. T1/J1 Transmit Pulse Templates..........................................................................................................78
Figure 8-13. E1 Transmit Pulse Templates...............................................................................................................79
Figure 8-14. Typical Monitor Application...................................................................................................................81
Figure 8-15. Jitter Attenuation...................................................................................................................................83
Figure 8-16. Analog Loopback...................................................................................................................................84
Figure 8-17. Local Loopback.....................................................................................................................................84
Figure 8-18. Remote Loopback.................................................................................................................................85
Figure 8-19. Dual Loopback......................................................................................................................................85
Figure 9-1. Register Memory Map for the DS26528..................................................................................................89
Figure 10-1. T1 Receive-Side D4 Timing................................................................................................................235
Figure 10-2. T1 Receive-Side ESF Timing..............................................................................................................235
Figure 10-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)...............................................................236
Figure 10-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..............................................236
Figure 10-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..............................................237
Figure 10-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode..................................................................238
Figure 10-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode..............................................................239
Figure 10-8. T1 Transmit-Side D4 Timing...............................................................................................................240
Figure 10-9. T1 Transmit-Side ESF Timing.............................................................................................................240
Figure 10-10. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................241
Figure 10-11. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...........................................241
Figure 10-12. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...........................................242
Figure 10-13. T1 Transmit-Side Interleave Bus Operation—BYTE Mode...............................................................243
Figure 10-14. T1 Transmit Interleave Bus Operation—FRAME Mode....................................................................244
Figure 10-15. E1 Receive-Side Timing....................................................................................................................245
Figure 10-16. E1 Receive-Side Boundary Timing (Elastic Store Disabled)............................................................245
Figure 10-17. E1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)............................................246
Figure 10-18. E1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)............................................246
Figure 10-19. E1 Transmit-Side Timing...................................................................................................................247
Figure 10-20. E1 Transmit-Side Boundary Timing (Elastic Store Disabled)...........................................................247
Figure 10-21. E1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...........................................248
Figure 10-22. E1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...........................................248
Figure 10-23. E1 G.802 Timing...............................................................................................................................249
Figure 12-1. Intel Bus Read Timing (BTS = 0)........................................................................................................253
