DS26528 ,Octal T1/E1/J1 TransceiverFeatures continued in Section 2. ORDERING INFORMATION PART TEMP RANGE PIN-PACKAGE DS26528 -40°C t ..
DS26528 ,Octal T1/E1/J1 TransceiverApplications Routers Crystal-Less Jitter Attenuators can be Selected Channel Service Units (CSUs ..
DS26528G+ ,Octal T1/E1/J1 TransceiverFEATURES Eight Complete T1, E1, or J1 Long-Haul/Short-The DS26528 is a single-chip 8-port framer ..
DS26528G+ ,Octal T1/E1/J1 TransceiverApplications Routers Crystal-Less Jitter Attenuator can be Selected Channel Service Units (CSUs) ..
DS26528GN ,Octal T1/E1/J1 TransceiverTABLE OF CONTENTS 1. DETAILED DESCRIPTION.......9 1.1 MAJOR OPERATING MODES.9 2. FEATURE HIGHLIGHTS ..
DS26528GN ,Octal T1/E1/J1 TransceiverFeatures Continued in Section 2. DS26528GN+ 256 TE-CSBGA -40°C to +85°C + Denotes lead-free/RoHS c ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26528
Octal T1/E1/J1 Transceiver
GENERAL DESCRIPTION The DS26528 is a single-chip 8-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each port is independently configurable,
supporting both long-haul and short-haul lines.
APPLICATIONS Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
FEATURES ��Eight Complete T1, E1, or J1 Long-Haul/Short-
Haul Transceivers (LIU plus Framer)
��Independent T1, E1, or J1 Selections for Each
Transceiver
��Internal Software-Selectable Transmit- and
Receive-Side Termination for 100� T1 Twisted
Pair, 110� J1 Twisted Pair, 120� E1 Twisted
Pair, and 75� E1 Coaxial Applications
��Crystal-Less Jitter Attenuators can be Selected
for Transmit or Receive Path. The Jitter Attenuator meets ETSI CTR 12/13, ITU G.736,
G.742, G.823, and AT&T PUB 62411.
��External Master Clock can be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1 operation. This Clock is Internally Adapted for T1
or E1 Usage in the Host Mode.
��Receive Signal Level Indication from -2.5dB to
-36dB in T1 Mode and -2.5dB to -44dB in E1 Mode in Approximate 2.5dB Increments
��Transmit Open and Short Circuit Detection
��LIU LOS in Accordance with G.775, ETSI
300233, and T1.231
��Transmit Synchronizer
��Flexible Signaling Extraction and Insertion Using Either the System Interface or Microprocessor
Port
��Alarm Detection and Insertion
��T1 Framing Formats of D4, SLC-96, and ESF
��J1 Support
��E1 G.704 and CRC-4 Multiframe
��T1 to E1 Conversion
Features continued in Section 2.
ORDERING INFORMATION
DS26528
DS26528 Octal T1/E1/J1 Transceiver
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................8
2. FEATURE HIGHLIGHTS....................................................................................................9 2.1 GENERAL.....................................................................................................................................9 2.2 LINE INTERFACE...........................................................................................................................9
2.3 CLOCK SYNTHESIZER...................................................................................................................9
2.4 JITTER ATTENUATOR....................................................................................................................9 2.5 FRAMER/FORMATTER...................................................................................................................9
2.6 SYSTEM INTERFACE...................................................................................................................10
2.7 HDLC CONTROLLERS................................................................................................................10 2.8 TEST AND DIAGNOSTICS.............................................................................................................11
2.9 CONTROL PORT.........................................................................................................................11
3. APPLICATIONS...............................................................................................................11
4. SPECIFICATIONS COMPLIANCE...................................................................................12
5. ACRONYMS AND GLOSSARY.......................................................................................14
6. MAJOR OPERATING MODES.........................................................................................15
7. BLOCK DIAGRAMS.........................................................................................................15
8. PIN DESCRIPTIONS........................................................................................................17 8.1 PIN FUNCTIONAL DESCRIPTION...................................................................................................17
9. FUNCTIONAL DESCRIPTION.........................................................................................24 9.1 PROCESSOR INTERFACE.............................................................................................................24 9.2 CLOCK STRUCTURE....................................................................................................................24
9.3 RESETS AND POWER-DOWN MODES...........................................................................................26
9.4 INITIALIZATION AND CONFIGURATION...........................................................................................27 9.5 GLOBAL RESOURCES..................................................................................................................27
9.6 PER-PORT RESOURCES..............................................................................................................27
9.7 DEVICE INTERRUPTS..................................................................................................................28 9.8 SYSTEM BACKPLANE INTERFACE.................................................................................................30
9.8.1 Elastic Stores.......................................................................................................................................30 9.8.2 IBO Multiplexer.....................................................................................................................................33
9.8.3 H.100 (CT-Bus) Compatibility..............................................................................................................40 9.8.4 Transmit and Receive Channel Blocking Registers.............................................................................41
9.8.5 Transmit Fractional Support (Gapped Clock Mode)............................................................................41 9.8.6 Receive Fractional Support (Gapped Clock Mode).............................................................................41
9.9 FRAMERS...................................................................................................................................42
9.9.1 T1 Framing...........................................................................................................................................42 9.9.2 E1 Framing...........................................................................................................................................45
9.9.3 T1 Transmit Synchronizer....................................................................................................................47 9.9.4 Signaling..............................................................................................................................................48
9.9.5 T1 Datalink...........................................................................................................................................53 9.9.6 E1 Datalink...........................................................................................................................................55
9.9.7 Maintenance and Alarms.....................................................................................................................56 9.9.8 E1 Automatic Alarm Generation..........................................................................................................59
9.9.9 Error Count Registers..........................................................................................................................60 9.9.10 DS0 Monitoring Function......................................................................................................................62
9.9.11 Transmit Per-Channel Idle Code Insertion...........................................................................................63 9.9.12 Receive Per-Channel Idle Code Insertion............................................................................................63
9.9.13 Per-Channel Loopback........................................................................................................................63
DS26528 Octal T1/E1/J1 Transceiver
9.9.16 Framer Payload Loopbacks.................................................................................................................66
9.10 HDLC CONTROLLERS.............................................................................................................67 9.10.1 Receive HDLC Controller.....................................................................................................................67
9.10.2 Transmit HDLC Controller....................................................................................................................70 9.10.3 FIFO Information..................................................................................................................................70
9.10.4 HDLC Transmit Example.....................................................................................................................70 9.11 LINE INTERFACE UNITS (LIU)...................................................................................................72
9.11.1 LIU Operation.......................................................................................................................................75 9.11.2 Transmitter...........................................................................................................................................76
9.11.3 Receiver...............................................................................................................................................79 9.11.4 Jitter Attenuator....................................................................................................................................81
9.11.5 LIU Loopbacks.....................................................................................................................................83 9.12 BIT ERROR RATE TEST FUNCTION (BERT)...............................................................................86
9.12.1 BERT Repetitive Pattern Set...............................................................................................................87 9.12.2 BERT Error Counter.............................................................................................................................87
10. DEVICE REGISTERS.......................................................................................................88 10.1 REGISTER LISTINGS................................................................................................................88 10.1.1 Global Register List..............................................................................................................................90
10.1.2 Framer Register List.............................................................................................................................90 10.1.3 LIU and BERT Register List.................................................................................................................97
10.2 REGISTER BIT MAPS...............................................................................................................98
10.2.1 Global Register Bit Map.......................................................................................................................98 10.2.2 Framer Register Bit Map......................................................................................................................99
10.2.3 LIU Register Bit Map..........................................................................................................................105 10.2.4 BERT Register Bit Map......................................................................................................................106
10.3 GLOBAL REGISTER DEFINITIONS............................................................................................107 10.4 FRAMER REGISTER DEFINITIONS............................................................................................121
10.4.1 Receive Register Definitions..............................................................................................................121 10.4.2 Transmit Register Definitions.............................................................................................................179
10.5 LIU REGISTER DEFINITIONS...................................................................................................214
10.6 BERT REGISTER DEFINITIONS...............................................................................................223
11. FUNCTIONAL TIMING...................................................................................................231 11.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS........................................................................231
11.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS..................................................................236 11.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS........................................................................241
11.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS..................................................................243
12. OPERATING PARAMETERS.........................................................................................246 12.1 LINE INTERFACE CHARACTERISTICS.......................................................................................247
13. AC TIMING CHARACTERISTICS..................................................................................248 13.1 MICROPROCESSOR BUS AC CHARACTERISTICS......................................................................248
13.2 JTAG INTERFACE TIMING......................................................................................................257 13.3 SYSTEM CLOCK AC CHARACTERISTICS..................................................................................258
14. JTAG-BOUNDARY SCAN AND TEST ACCESS PORT................................................259 14.1 INSTRUCTION REGISTER........................................................................................................263 14.2 JTAG ID CODES...................................................................................................................264
14.3 TEST REGISTERS..................................................................................................................264
14.4 BOUNDARY SCAN REGISTER..................................................................................................264 14.5 BYPASS REGISTER................................................................................................................264
14.6 IDENTIFICATION REGISTER.....................................................................................................264
15. DOCUMENT REVISION HISTORY................................................................................268
DS26528 Octal T1/E1/J1 Transceiver
LIST OF FIGURES Figure 7-1. Block Diagram.....................................................................................................................15
Figure 7-2. Detailed Block Diagram.......................................................................................................16
Figure 8-1. BGA Pinout.........................................................................................................................23 Figure 9-1. Backplane Clock Generation...............................................................................................25
Figure 9-2. Device Interrupt Information Flow Diagram..........................................................................29 Figure 9-3. IBO Multiplexer Equivalent Circuit4.096MHz....................................................................34
Figure 9-4. IBO Multiplexer Equivalent Circuit8.192MHz....................................................................35
Figure 9-5. IBO Multiplexer Equivalent Circuit16.384MHz..................................................................36 Figure 9-6. RSYNC Input In H.100 (Ct-Bus) Mode................................................................................40
Figure 9-7. TSSYNCIO(Input Mode) Input In H.100 (CT-Bus) Mode......................................................41
Figure 9-8. CRC-4 Recalculate Method.................................................................................................63 Figure 9-9. Receive HDLC Example......................................................................................................69
Figure 9-10. HDLC Message Transmit Example....................................................................................71
Figure 9-11. Basic Balanced Network Connections...............................................................................73 Figure 9-12. Recommended Supply Decoupling....................................................................................75
Figure 9-13. T1/J1 Transmit Pulse Templates.......................................................................................77
Figure 9-14. E1 Transmit Pulse Templates............................................................................................78 Figure 9-15. Typical Monitor Application................................................................................................80
Figure 9-16. Jitter Attenuation...............................................................................................................83 Figure 9-17. Analog Loopback...............................................................................................................83
Figure 9-18. Local Loopback.................................................................................................................84
Figure 9-19. Remote Loopback.............................................................................................................84 Figure 9-20. Dual Loopback..................................................................................................................85
Figure 10-1. Register Memory Map for the DS26528.............................................................................89
Figure 11-1. T1 Receive Side D4 Timing.............................................................................................231 Figure 11-2. T1 Receive Side ESF Timing...........................................................................................231
Figure 11-3. T1 Receive Side Boundary Timing (elastic store disabled)..............................................232
Figure 11-4. T1 Receive Side 1.544MHz Boundary Timing (e-store enabled)......................................232 Figure 11-5. T1 Receive Side 2.048MHz Boundary Timing (e-store enabled)......................................233
Figure 11-6. T1 Receive Side Interleave Bus Operation, BYTE Mode.................................................234
Figure 11-7. T1 Receive Side Interleave Bus Operation, FRAME Mode..............................................235 Figure 11-8. T1 Transmit Side D4 Timing............................................................................................236
Figure 11-9. T1 Transmit Side ESF Timing..........................................................................................236
Figure 11-10. T1 Transmit Side Boundary Timing (e-store disabled)...................................................237 Figure 11-11. T1 Transmit Side 1.544MHz Boundary Timing (e-store enabled)...................................237
Figure 11-12. T1 Transmit Side 2.048MHz Boundary Timing (e-store enabled)...................................238 Figure 11-13. T1 Transmit Side Interleave Bus Operation, BYTE Mode..............................................239
Figure 11-14. T1 Transmit Interleave Bus Operation, FRAME Mode...................................................240
Figure 11-15. E1 Receive Side Timing................................................................................................241
Figure 11-16. E1 Receive Side Boundary Timing (elastic store disabled)............................................241 Figure 11-17. E1 Receive Side 1.544MHz Boundary Timing (e-store enabled)...................................242
Figure 11-18. E1 Receive Side 2.048MHz Boundary Timing (e-store enabled)...................................242 Figure 11-19. E1 Transmit Side Timing...............................................................................................243
Figure 11-20. E1 Transmit Side Boundary Timing (elastic store disabled)...........................................243
Figure 11-21. E1 Transmit Side 1.544MHz Boundary Timing (e-store enabled)..................................244 Figure 11-22. E1 Transmit Side 2.048MHz Boundary Timing (e-store enabled)..................................244
Figure 11-23. E1 G.802 Timing...........................................................................................................245
Figure 13-1. Intel Bus Read Timing (BTS = 0).....................................................................................249 Figure 13-2. Intel Bus Write Timing (BTS = 0).....................................................................................249
Figure 13-3. Motorola Bus Read Timing (BTS = 1)..............................................................................250
DS26528 Octal T1/E1/J1 Transceiver
Figure 13-5. Receive Framer TimingBackplane (T1 Mode)..............................................................252
Figure 13-6. Receive Side Timing, Elastic Store Enabled (T1 Mode)...................................................253
Figure 13-7. Receive Framer TimingLine Side.................................................................................253 Figure 13-8. Transmit Formatter TimingBackplane..........................................................................255
Figure 13-9. Transmit Formatter Timing, Elastic Store Enabled...........................................................256 Figure 13-10. Transmit Formatter TimingLine Side..........................................................................256
Figure 13-11. JTAG Interface Timing Diagram....................................................................................257
Figure 14-1. JTAG Functional Block Diagram......................................................................................259 Figure 14-2. Tap Controller State Diagram..........................................................................................262
