DS26519 ,16-Port T1/E1/J1 TransceiverApplications Routers Channel Service Units (CSUs) Hitless Protection Switching Data Service Unit ..
DS26521 ,Single T1/E1/J1 TransceiverFeatures Continued in Section 2. DS26521LN+ -40°C to +85°C 64 LQFP + Denotes lead-free/RoHS compli ..
DS26521DK ,Single T1/E1/J1 Transceiver Design Kit DS26521DK Single T1/E1/J1 Transceiver Design Kit
DS26521L+ ,Single T1/E1/J1 Transceiverapplications. Each channel is independently Internal Software-Selectable Transmit- and configurab ..
DS26521LN ,Single T1/E1/J1 TransceiverFEATURES Complete T1, E1, or J1 Long-Haul/Short-Haul The DS26521 is a single-channel framer and l ..
DS26521LN+ ,Single T1/E1/J1 TransceiverTABLE OF CONTENTS 1. DETAILED DESCRIPTION.....9 1.1 MAJOR OPERATING MODES.9 2. FEATURE HIGHLIGHTS . ..
E53NA50 ,NABSOLUTE MAXIMUM RATINGSSymbol Parameter Value UnitV Drain-source Voltage (V =0) 500 VDS GSV 500 VD ..
EA2-12 ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-12NU ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12S ,COMPACT AND LIGHTWEIGHTFEATURESª Low power consumptionª Compact and light weightª 2 form c contact arrangementª Low magnet ..
EA2-12TNU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
EA2-4.5NU ,COMPACT AND LIGHTWEIGHTAPPLICATIONSElectronic switching systems, PBX, key telephone systems, automatic test equipment and ..
DS26519
16-Port T1/E1/J1 Transceiver
DS26519
16-Port T1/E1/J1 Transceiver
DEMO KIT AVAILABLE
GENERAL DESCRIPTION The DS26519 is a single-chip 16-port framer and line
interface unit (LIU) combination for T1, E1, and J1
applications. Each port is independently configurable,
supporting both long-haul and short-haul lines. The
DS26519 is nearly software compatible with the
DS26528 and its derivatives.
APPLICATIONS Routers
Channel Service Units (CSUs)
Data Service Units (DSUs)
Muxes
Switches
Channel Banks
T1/E1 Test Equipment
FUNCTIONAL DIAGRAM
DS26519
T1/J1/E1
TransceiverT1/E1/J1
NETWORK
BACKPLANE
TDM
x16
ORDERING INFORMATION
PART TEMP RANGE PIN-PACKAGE DS26519G 0°C to +70°C 484 HSBGA
DS26519G+ 0°C to +70°C 484 HSBGA
DS26519GN -40°C to +85°C 484 HSBGA
DS26519GN+ -40°C to +85°C 484 HSBGA
+ Denotes a lead-free/RoHS compliant device.
FEATURES � 16 Complete T1, E1, or J1 Long-Haul/
Short-Haul Transceivers (LIU Plus Framer) � Independent T1, E1, or J1 Selections for Each
Transceiver � Software-Selectable Transmit- and Receive-
Side Termination for 100Ω T1 Twisted Pair,
110Ω J1 Twisted Pair, 120Ω E1 Twisted Pair,
and 75Ω E1 Coaxial Applications � Hitless Protection Switching � Crystal-Less Jitter Attenuators Can Be
Selected for Transmit or Receive Path; Jitter
Attenuator Meets ETS CTR 12/13, ITU-T
G.736, G.742, G.823, and AT&T Pub 62411 � External Master Clock Can Be Multiple of
2.048MHz or 1.544MHz for T1/J1 or E1
Operation; This Clock is Internally Adapted
for T1 or E1 Usage in the Host Mode � Receive-Signal Level Indication from -2.5dB
to -36dB in T1 Mode and -2.5dB to -44dB in E1
Mode in Approximate 2.5dB Increments � Transmit Open- and Short-Circuit Detection � LIU LOS in Accordance with G.775, ETS 300
233, and T1.231 � Transmit Synchronizer � Flexible Signaling Extraction and Insertion
Using Either the System Interface or
Microprocessor Port � Alarm Detection and Insertion � T1 Framing Formats of D4, SLC-96, and ESF � J1 Support � E1 G.704 and CRC-4 Multiframe �
T1-to-E1 Conversion
Features continued in Section 2.
DS26519 16-Port T1/E1/J1 Transceiver
TABLE OF CONTENTS
1. DETAILED DESCRIPTION.................................................................................................9
2. FEATURE HIGHLIGHTS..................................................................................................10 2.1 GENERAL......................................................................................................................................10
2.2 LINE INTERFACE............................................................................................................................10
2.3 CLOCK SYNTHESIZERS..................................................................................................................10
2.4 JITTER ATTENUATOR.....................................................................................................................10
2.5 FRAMER/FORMATTER....................................................................................................................11
2.6 SYSTEM INTERFACE......................................................................................................................11
2.7 HDLC CONTROLLERS...................................................................................................................12
2.8 TEST AND DIAGNOSTICS................................................................................................................12
2.9 MICROCONTROLLER PARALLEL PORT.............................................................................................12
2.10 SLAVE SERIAL PERIPHERAL INTERFACE (SPI) FEATURES............................................................12
3. APPLICATIONS...............................................................................................................13
4. SPECIFICATIONS COMPLIANCE...................................................................................14
5. ACRONYMS AND GLOSSARY.......................................................................................16
6. MAJOR OPERATING MODES.........................................................................................17
7. BLOCK DIAGRAMS.........................................................................................................18
8. PIN DESCRIPTIONS........................................................................................................20 8.1 PIN FUNCTIONAL DESCRIPTION......................................................................................................20
9. FUNCTIONAL DESCRIPTION.........................................................................................33 9.1 PROCESSOR INTERFACE................................................................................................................33
9.1.1 SPI Serial Port Mode............................................................................................................................33
9.1.2 SPI Functional Timing Diagrams.........................................................................................................33
9.2 CLOCK STRUCTURE.......................................................................................................................35
9.2.1 Backplane Clock Generation...............................................................................................................35
9.2.2 CLKO Output Clock Generation...........................................................................................................37
9.3 RESETS AND POWER-DOWN MODES..............................................................................................38
9.4 INITIALIZATION AND CONFIGURATION..............................................................................................39
9.4.1 Example Device Initialization and Sequence.......................................................................................39
9.5 GLOBAL RESOURCES....................................................................................................................40
9.5.1 General-Purpose I/O Pins....................................................................................................................40
9.6 PER-PORT RESOURCES................................................................................................................40
9.7 DEVICE INTERRUPTS.....................................................................................................................41
9.8 SYSTEM BACKPLANE INTERFACE...................................................................................................43
9.8.1 Elastic Stores.......................................................................................................................................43
9.8.2 IBO Multiplexing...................................................................................................................................46
9.8.3 H.100 (CT Bus) Compatibility..............................................................................................................55
9.8.4 Transmit and Receive Channel Blocking Registers.............................................................................57
9.8.5 Transmit Fractional Support (Gapped Clock Mode)............................................................................57
9.8.6 Receive Fractional Support (Gapped Clock Mode).............................................................................57
9.9 FRAMERS......................................................................................................................................58
9.9.1 T1 Framing...........................................................................................................................................58
9.9.2 E1 Framing...........................................................................................................................................61
9.9.3 T1 Transmit Synchronizer....................................................................................................................63
DS26519 16-Port T1/E1/J1 Transceiver
9.9.7 Maintenance and Alarms.....................................................................................................................72
9.9.8 Alarms..................................................................................................................................................75
9.9.9 Error Count Registers..........................................................................................................................77
9.9.10 DS0 Monitoring Function......................................................................................................................79
9.9.11 Transmit Per-Channel Idle Code Generation......................................................................................80
9.9.12 Receive Per-Channel Idle Code Insertion............................................................................................80
9.9.13 Per-Channel Loopback........................................................................................................................80
9.9.14 E1 G.706 Intermediate CRC-4 Updating (E1 Mode Only)...................................................................80
9.9.15 T1 Programmable In-Band Loop Code Generator...............................................................................81
9.9.16 T1 Programmable In-Band Loop Code Detection................................................................................82
9.9.17 Framer Payload Loopbacks.................................................................................................................83
9.10 HDLC CONTROLLERS................................................................................................................84
9.10.1 Receive HDLC Controller.....................................................................................................................84
9.10.2 Transmit HDLC Controller....................................................................................................................87
9.11 POWER-SUPPLY DECOUPLING....................................................................................................89
9.12 LINE INTERFACE UNITS (LIUS)....................................................................................................90
9.12.1 LIU Operation.......................................................................................................................................92
9.12.2 Transmitter...........................................................................................................................................93
9.12.3 Receiver...............................................................................................................................................97
9.12.4 Hitless Protection Switching (HPS)....................................................................................................101
9.12.5 Jitter Attenuator..................................................................................................................................102
9.12.6 LIU Loopbacks...................................................................................................................................103
9.13 BIT ERROR-RATE TEST FUNCTION (BERT)...............................................................................106
9.13.1 BERT Repetitive Pattern Set.............................................................................................................107
9.13.2 BERT Error Counter...........................................................................................................................107
10. DEVICE REGISTERS.....................................................................................................108 10.1 REGISTER LISTINGS.................................................................................................................108
10.1.1 Global Register List............................................................................................................................109
10.1.2 Framer Register List...........................................................................................................................110
10.1.3 LIU and BERT Register List...............................................................................................................117
10.2 REGISTER BIT MAPS................................................................................................................118
10.2.1 Global Register Bit Map.....................................................................................................................118
10.2.2 Framer Register Bit Map....................................................................................................................119
10.2.3 LIU Register Bit Map..........................................................................................................................128
10.2.4 BERT Register Bit Map......................................................................................................................129
10.3 GLOBAL REGISTER DEFINITIONS...............................................................................................130
10.4 FRAMER REGISTER DESCRIPTIONS...........................................................................................156
10.4.1 Receive Register Descriptions...........................................................................................................156
10.4.2 Transmit Register Descriptions..........................................................................................................214
10.5 LIU REGISTER DEFINITIONS.....................................................................................................250
10.6 BERT REGISTER DEFINITIONS.................................................................................................260
11. FUNCTIONAL TIMING...................................................................................................268 11.1 T1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................268
11.2 T1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................273
11.3 E1 RECEIVER FUNCTIONAL TIMING DIAGRAMS..........................................................................278
11.4 E1 TRANSMITTER FUNCTIONAL TIMING DIAGRAMS....................................................................282
12. OPERATING PARAMETERS.........................................................................................287 12.1 THERMAL CHARACTERISTICS....................................................................................................288
12.2 LINE INTERFACE CHARACTERISTICS..........................................................................................288
DS26519 16-Port T1/E1/J1 Transceiver
13. AC TIMING CHARACTERISTICS..................................................................................289 13.1 MICROPROCESSOR BUS AC CHARACTERISTICS........................................................................289
13.1.1 SPI Bus Mode....................................................................................................................................289
13.2 JTAG INTERFACE TIMING.........................................................................................................300
13.3 SYSTEM CLOCK AC CHARACTERISTICS....................................................................................301
14. JTAG BOUNDARY SCAN AND TEST ACCESS PORT................................................302 14.1 TAP CONTROLLER STATE MACHINE.........................................................................................303
14.1.1 Test-Logic-Reset................................................................................................................................303
14.1.2 Run-Test-Idle.....................................................................................................................................303
14.1.3 Select-DR-Scan.................................................................................................................................303
14.1.4 Capture-DR........................................................................................................................................303
14.1.5 Shift-DR..............................................................................................................................................303
14.1.6 Exit1-DR.............................................................................................................................................303
14.1.7 Pause-DR...........................................................................................................................................303
14.1.8 Exit2-DR.............................................................................................................................................303
14.1.9 Update-DR.........................................................................................................................................303
14.1.10 Select-IR-Scan...............................................................................................................................303
14.1.11 Capture-IR......................................................................................................................................304
14.1.12 Shift-IR............................................................................................................................................304
14.1.13 Exit1-IR...........................................................................................................................................304
14.1.14 Pause-IR.........................................................................................................................................304
14.1.15 Exit2-IR...........................................................................................................................................304
14.1.16 Update-IR.......................................................................................................................................304
14.2 INSTRUCTION REGISTER...........................................................................................................306
14.2.1 SAMPLE:PRELOAD..........................................................................................................................306
14.2.2 BYPASS.............................................................................................................................................306
14.2.3 EXTEST.............................................................................................................................................306
14.2.4 CLAMP...............................................................................................................................................306
14.2.5 HIGHZ................................................................................................................................................306
14.2.6 IDCODE.............................................................................................................................................306
14.3 JTAG ID CODES......................................................................................................................307
14.4 TEST REGISTERS.....................................................................................................................307
14.4.1 Boundary Scan Register....................................................................................................................307
14.4.2 Bypass Register.................................................................................................................................307
14.4.3 Identification Register.........................................................................................................................307
15. PIN CONFIGURATION...................................................................................................308 15.1 PIN CONFIGURATION—484-BALL HSBGA................................................................................308
16. PACKAGE INFORMATION............................................................................................309 16.1 484-BALL HSBGA (56-G6038-002).........................................................................................309
17. DOCUMENT REVISION HISTORY................................................................................310 DS26519 16-Port T1/E1/J1 Transceiver
LIST OF FIGURES Figure 7-1. Block Diagram.........................................................................................................................................18
Figure 7-2. Detailed Block Diagram...........................................................................................................................19
Figure 9-1. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 0...............................................34
Figure 9-2. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 0...............................................34
Figure 9-3. SPI Serial Port Access for Read Mode, SPI_CPOL = 0, SPI_CPHA = 1...............................................34
Figure 9-4. SPI Serial Port Access for Read Mode, SPI_CPOL = 1, SPI_CPHA = 1...............................................34
Figure 9-5. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 0...............................................35
Figure 9-6. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 0...............................................35
Figure 9-7. SPI Serial Port Access for Write Mode, SPI_CPOL = 0, SPI_CPHA = 1...............................................35
Figure 9-8. SPI Serial Port Access for Write Mode, SPI_CPOL = 1, SPI_CPHA = 1...............................................35
Figure 9-9. Backplane Clock Generation...................................................................................................................36
Figure 9-10. GPIO Mux Control.................................................................................................................................40
Figure 9-11. Device Interrupt Information Flow Diagram...........................................................................................42
Figure 9-12. IBO Multiplexer Equivalent Circuit—4.096MHz....................................................................................47
Figure 9-13. IBO Multiplexer Equivalent Circuit—8.192MHz....................................................................................48
Figure 9-14. IBO Multiplexer Equivalent Circuit—16.384MHz..................................................................................49
Figure 9-15. RSYNCn Input in H.100 (CT Bus) Mode...............................................................................................56
Figure 9-16. TSSYNCIOn (Input Mode) Input in H.100 (CT Bus) Mode...................................................................56
Figure 9-17. CRC-4 Recalculate Method..................................................................................................................80
Figure 9-18. HDLC Message Receive Example........................................................................................................86
Figure 9-19. HDLC Message Transmit Example.......................................................................................................88
Figure 9-20. Network Connection—Longitudinal Protection.....................................................................................91
Figure 9-21. T1/J1 Transmit Pulse Templates..........................................................................................................94
Figure 9-22. E1 Transmit Pulse Templates...............................................................................................................95
Figure 9-23. Receive LIU Termination Options.........................................................................................................97
Figure 9-24. Typical Monitor Application...................................................................................................................98
Figure 9-25. HPS Block Diagram.............................................................................................................................101
Figure 9-26. Jitter Attenuation.................................................................................................................................102
Figure 9-27. Loopback Diagram..............................................................................................................................103
Figure 9-28. Analog Loopback.................................................................................................................................103
Figure 9-29. Local Loopback...................................................................................................................................104
Figure 9-30. Remote Loopback 2............................................................................................................................104
Figure 9-31. Dual Loopback....................................................................................................................................105
Figure 11-1. T1 Receive-Side D4 Timing................................................................................................................268
Figure 11-2. T1 Receive-Side ESF Timing..............................................................................................................268
Figure 11-3. T1 Receive-Side Boundary Timing (Elastic Store Disabled)...............................................................269
Figure 11-4. T1 Receive-Side 1.544MHz Boundary Timing (Elastic Store Enabled)..............................................269
Figure 11-5. T1 Receive-Side 2.048MHz Boundary Timing (Elastic Store Enabled)..............................................270
Figure 11-6. T1 Receive-Side Interleave Bus Operation—BYTE Mode..................................................................271
Figure 11-7. T1 Receive-Side Interleave Bus Operation—FRAME Mode..............................................................272
Figure 11-8. T1 Receive-Side RCHCLKn Gapped Mode During F-Bit....................................................................272
Figure 11-9. T1 Transmit-Side D4 Timing...............................................................................................................273
Figure 11-10. T1 Transmit-Side ESF Timing...........................................................................................................273
Figure 11-11. T1 Transmit-Side Boundary Timing (Elastic Store Disabled)............................................................274
Figure 11-12. T1 Transmit-Side 1.544MHz Boundary Timing (Elastic Store Enabled)...........................................274
Figure 11-13. T1 Transmit-Side 2.048MHz Boundary Timing (Elastic Store Enabled)...........................................275
